diff --git a/XilinxProcessorIPLib/drivers/coresightps_dcc/data/coresightps_dcc.mdd b/XilinxProcessorIPLib/drivers/coresightps_dcc/data/coresightps_dcc.mdd index 37955ea5..9ff6a9cd 100755 --- a/XilinxProcessorIPLib/drivers/coresightps_dcc/data/coresightps_dcc.mdd +++ b/XilinxProcessorIPLib/drivers/coresightps_dcc/data/coresightps_dcc.mdd @@ -34,7 +34,7 @@ BEGIN driver coresightps_dcc OPTION copyfiles = all; OPTION driver_state = ACTIVE; -OPTION supported_peripherals = (ps7_coresight_comp); +OPTION supported_peripherals = (ps7_coresight_comp psu_coresight_0); OPTION VERSION = 1.1; OPTION NAME = coresightps_dcc; diff --git a/XilinxProcessorIPLib/drivers/coresightps_dcc/src/Makefile b/XilinxProcessorIPLib/drivers/coresightps_dcc/src/Makefile index 007162d8..083581ee 100644 --- a/XilinxProcessorIPLib/drivers/coresightps_dcc/src/Makefile +++ b/XilinxProcessorIPLib/drivers/coresightps_dcc/src/Makefile @@ -8,6 +8,10 @@ LIB=libxil.a CC_FLAGS = $(COMPILER_FLAGS) ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) +ifeq ($(notdir $(COMPILER)), arm-none-eabi-gcc) +ECC_FLAGS += -mcpu=cortex-r5 +endif + RELEASEDIR=../../../lib INCLUDEDIR=../../../include INCLUDES=-I./. -I${INCLUDEDIR} diff --git a/XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.c b/XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.c index 687a9f63..e65a7bdb 100644 --- a/XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.c +++ b/XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.c @@ -49,6 +49,7 @@ * Ver Who Date Changes * ----- ----- -------- ----------------------------------------------- * 1.00 kvn 02/14/15 First release +* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP. * * * @@ -88,7 +89,9 @@ void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data) (void) BaseAddress; while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX) dsb(); -#if defined (__GNUC__) || defined (__ICCARM__) +#ifdef __aarch64__ + asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data)); +#elif defined (__GNUC__) || defined (__ICCARM__) asm volatile("mcr p14, 0, %0, c0, c5, 0" : : "r" (Data)); #else @@ -124,7 +127,9 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX)) dsb(); -#if defined (__GNUC__) || defined (__ICCARM__) +#ifdef __aarch64__ + asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data)); +#elif defined (__GNUC__) || defined (__ICCARM__) asm volatile("mrc p14, 0, %0, c0, c5, 0" : "=r" (Data)); #else @@ -154,7 +159,10 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) static INLINE u32 XCoresightPs_DccGetStatus(void) { u32 Status; -#if defined (__GNUC__) || defined (__ICCARM__) + +#ifdef __aarch64__ + asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status)); +#elif defined (__GNUC__) || defined (__ICCARM__) asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (Status) : : "cc"); #else diff --git a/XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.h b/XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.h index bfd78c32..7f477ca3 100644 --- a/XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.h +++ b/XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.h @@ -53,6 +53,7 @@ * Ver Who Date Changes * ----- ----- -------- ----------------------------------------------- * 1.00 kvn 02/14/15 First release +* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP. * * *