From bcdb65d21bc7b368dce4e10d35ef6a8cfc053fce Mon Sep 17 00:00:00 2001 From: Kedareswara rao Appana Date: Mon, 24 Aug 2015 12:48:47 +0530 Subject: [PATCH] axidma: Mark only BD Memory region as uncacheable This patch updates the Xil_SetTlbAttributes to mark the BD memory region only uncaheable and updated the cache flush/invalidate api's for a53 case. Signed-off-by: Kedareswara rao Appana Acked by: Anirudha Sarangi --- .../drivers/axidma/examples/xaxidma_example_sg_intr.c | 11 +++++++++++ .../drivers/axidma/examples/xaxidma_example_sg_poll.c | 8 +++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c index a69e6b85..b67b3875 100644 --- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c +++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c @@ -162,6 +162,7 @@ extern void xil_printf(const char *format, ...); * Buffer and Buffer Descriptor related constant definition */ #define MAX_PKT_LEN 0x100 +#define MARK_UNCACHEABLE 0x701 /* * Number of BDs in the transfer example @@ -276,6 +277,10 @@ int main(void) #endif xil_printf("\r\n--- Entering main() --- \r\n"); +#ifdef __aarch64__ + Xil_SetTlbAttributes(TX_BD_SPACE_BASE, MARK_UNCACHEABLE); + Xil_SetTlbAttributes(RX_BD_SPACE_BASE, MARK_UNCACHEABLE); +#endif Config = XAxiDma_LookupConfig(DMA_DEV_ID); if (!Config) { @@ -428,7 +433,9 @@ static int CheckData(int Length, u8 StartValue) /* Invalidate the DestBuffer before receiving the data, in case the * Data Cache is enabled */ +#ifndef __aarch64__ Xil_DCacheInvalidateRange((u32)RxPacket, Length); +#endif for(Index = 0; Index < Length; Index++) { if (RxPacket[Index] != Value) { @@ -1113,6 +1120,10 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr) */ Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER); +#ifdef __aarch64__ + Xil_DCacheFlushRange((UINTPTR)RX_BUFFER_BASE, MAX_PKT_LEN * + NUMBER_OF_BDS_TO_TRANSFER); +#endif Status = XAxiDma_BdRingAlloc(TxRingPtr, NUMBER_OF_BDS_TO_TRANSFER, &BdPtr); diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c index 5c4e3716..941244d3 100644 --- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c +++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c @@ -200,7 +200,8 @@ int main(void) xil_printf("\r\n--- Entering main() --- \r\n"); #ifdef __aarch64__ - Xil_SetTlbAttributes(MEM_BASE_ADDR, MARK_UNCACHEABLE); + Xil_SetTlbAttributes(TX_BD_SPACE_BASE, MARK_UNCACHEABLE); + Xil_SetTlbAttributes(RX_BD_SPACE_BASE, MARK_UNCACHEABLE); #endif Config = XAxiDma_LookupConfig(DMA_DEV_ID); @@ -515,6 +516,9 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr) * is enabled */ Xil_DCacheFlushRange((UINTPTR)TxPacket, MAX_PKT_LEN); +#ifdef __aarch64__ + Xil_DCacheFlushRange((UINTPTR)RX_BUFFER_BASE, MAX_PKT_LEN); +#endif /* Allocate a BD */ @@ -597,7 +601,9 @@ static int CheckData(void) /* Invalidate the DestBuffer before receiving the data, in case the * Data Cache is enabled */ +#ifndef __aarch64__ Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_PKT_LEN); +#endif for(Index = 0; Index < MAX_PKT_LEN; Index++) { if (RxPacket[Index] != Value) {