diff --git a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c
index 858df0ec..de7eea3c 100644
--- a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c
@@ -107,39 +107,29 @@
 /************************** Constant Definitions *****************************/
 
 const static XNandPsu_EccMatrix EccMatrix[] = {
-	/*
-	 * 512 byte page
-	 */
+	/* 512 byte page */
 	{XNANDPSU_PAGE_SIZE_512, 9U, 1U, XNANDPSU_HAMMING, 0x20DU, 0x3U},
 	{XNANDPSU_PAGE_SIZE_512, 9U, 4U, XNANDPSU_BCH, 0x209U, 0x7U},
 	{XNANDPSU_PAGE_SIZE_512, 9U, 8U, XNANDPSU_BCH, 0x203U, 0xDU},
-	/*
-	 * 2K byte page
-	 */
+	/* 2K byte page */
 	{XNANDPSU_PAGE_SIZE_2K, 9U, 1U, XNANDPSU_HAMMING, 0x834U, 0xCU},
 	{XNANDPSU_PAGE_SIZE_2K, 9U, 4U, XNANDPSU_BCH, 0x826U, 0x1AU},
 	{XNANDPSU_PAGE_SIZE_2K, 9U, 8U, XNANDPSU_BCH, 0x80cU, 0x34U},
 	{XNANDPSU_PAGE_SIZE_2K, 9U, 12U, XNANDPSU_BCH, 0x822U, 0x4EU},
 	{XNANDPSU_PAGE_SIZE_2K, 10U, 24U, XNANDPSU_BCH, 0x81cU, 0x54U},
-	/*
-	 * 4K byte page
-	 */
+	/* 4K byte page */
 	{XNANDPSU_PAGE_SIZE_4K, 9U, 1U, XNANDPSU_HAMMING, 0x1068U, 0x18U},
 	{XNANDPSU_PAGE_SIZE_4K, 9U, 4U, XNANDPSU_BCH, 0x104cU, 0x34U},
 	{XNANDPSU_PAGE_SIZE_4K, 9U, 8U, XNANDPSU_BCH, 0x1018U, 0x68U},
 	{XNANDPSU_PAGE_SIZE_4K, 9U, 12U, XNANDPSU_BCH, 0x1044U, 0x9CU},
 	{XNANDPSU_PAGE_SIZE_4K, 10U, 24U, XNANDPSU_BCH, 0x1038U, 0xA8U},
-	/*
-	 * 8K byte page
-	 */
+	/* 8K byte page */
 	{XNANDPSU_PAGE_SIZE_8K, 9U, 1U, XNANDPSU_HAMMING, 0x20d0U, 0x30U},
 	{XNANDPSU_PAGE_SIZE_8K, 9U, 4U, XNANDPSU_BCH, 0x2098U, 0x68U},
 	{XNANDPSU_PAGE_SIZE_8K, 9U, 8U, XNANDPSU_BCH, 0x2030U, 0xD0U},
 	{XNANDPSU_PAGE_SIZE_8K, 9U, 12U, XNANDPSU_BCH, 0x2088U, 0x138U},
 	{XNANDPSU_PAGE_SIZE_8K, 10U, 24U, XNANDPSU_BCH, 0x2070U, 0x150U},
-	/*
-	 * 16K byte page
-	 */
+	/* 16K byte page */
 	{XNANDPSU_PAGE_SIZE_16K, 9U, 1U, XNANDPSU_HAMMING, 0x4460U, 0x60U},
 	{XNANDPSU_PAGE_SIZE_16K, 9U, 4U, XNANDPSU_BCH, 0x43f0U, 0xD0U},
 	{XNANDPSU_PAGE_SIZE_16K, 9U, 8U, XNANDPSU_BCH, 0x4320U, 0x1A0U},
@@ -238,24 +228,16 @@ s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
 {
 	s32 Status = XST_FAILURE;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(ConfigPtr != NULL);
 
-	/*
-	 * Initialize InstancePtr Config structure
-	 */
+	/* Initialize InstancePtr Config structure */
 	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
 	InstancePtr->Config.BaseAddress = EffectiveAddr;
-	/*
-	 * Operate in Polling Mode
-	 */
+	/* Operate in Polling Mode */
 	InstancePtr->Mode = XNANDPSU_POLLING;
-	/*
-	 * Enable MDMA mode by default
-	 */
+	/* Enable MDMA mode by default */
 	InstancePtr->DmaMode = XNANDPSU_MDMA;
 	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 
@@ -270,9 +252,7 @@ s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
 					CSU_VER_PLATFORM_QEMU_VAL) {
 		isQemuPlatform = 1U;
 	}
-	/*
-	 * Initialize the NAND flash targets
-	 */
+	/* Initialize the NAND flash targets */
 	Status = XNandPsu_FlashInit(InstancePtr);
 	if (Status != XST_SUCCESS) {
 #ifdef XNANDPSU_DEBUG
@@ -280,9 +260,7 @@ s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
 #endif
 		goto Out;
 	}
-	/*
-	 * Set ECC mode
-	 */
+	/* Set ECC mode */
 	if (InstancePtr->Features.EzNand != 0U) {
 		InstancePtr->EccMode = XNANDPSU_EZNAND;
 	} else if (InstancePtr->Features.OnDie != 0U) {
@@ -296,9 +274,7 @@ s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
 		goto Out;
 	}
 
-	/*
-	 * Initialize Ecc Error flip counters
-	 */
+	/* Initialize Ecc Error flip counters */
 	 InstancePtr->Ecc_Stat_PerPage_flips = 0U;
 	 InstancePtr->Ecc_Stats_total_flips = 0U;
 
@@ -346,14 +322,10 @@ static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr)
 	u32 PrmPgLen;
 	OnfiExtPrmPage ExtParam __attribute__ ((aligned(64)));
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/*
-	 * Clear Data Interface Register
-	 */
+	/* Clear Data Interface Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_DATA_INTF_OFFSET, 0U);
 
@@ -362,16 +334,12 @@ static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr)
 			XNANDPSU_DMA_BUF_BND_OFFSET, 0U);
 
 	for (Target = 0U; Target < XNANDPSU_MAX_TARGETS; Target++) {
-		/*
-		 * Reset the Target
-		 */
+		/* Reset the Target */
 		Status = XNandPsu_OnfiReset(InstancePtr, Target);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
-		/*
-		 * Read ONFI ID
-		 */
+		/* Read ONFI ID */
 		Status = XNandPsu_OnfiReadId(InstancePtr, Target,
 						ONFI_READ_ID_ADDR,
 						ONFI_SIG_LEN,
@@ -454,9 +422,7 @@ static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr)
 					if (Status != XST_SUCCESS) {
 						goto Out;
 					}
-					/*
-					 * Check CRC
-					 */
+					/* Check CRC */
 					Crc = XNandPsu_OnfiParamPageCrc(
 							(u8 *)&ExtParam,
 							2U,
@@ -469,9 +435,7 @@ static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr)
 						Status = XST_FAILURE;
 						goto Out;
 					}
-					/*
-					 * Initialize Extended ECC info
-					 */
+					/* Initialize Extended ECC info */
 					Status = XNandPsu_InitExtEcc(
 							InstancePtr,
 							&ExtParam);
@@ -487,9 +451,7 @@ static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr)
 		}
 		InstancePtr->Geometry.NumTargets++;
 	}
-	/*
-	 * Calculate total number of blocks and total size of flash
-	 */
+	/* Calculate total number of blocks and total size of flash */
 	InstancePtr->Geometry.NumPages = InstancePtr->Geometry.NumTargets *
 					InstancePtr->Geometry.NumTargetPages;
 	InstancePtr->Geometry.NumBlocks = InstancePtr->Geometry.NumTargets *
@@ -519,9 +481,7 @@ Out:
 ******************************************************************************/
 static void XNandPsu_InitGeometry(XNandPsu *InstancePtr, OnfiParamPage *Param)
 {
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertVoid(Param != NULL);
 
 	InstancePtr->Geometry.BytesPerPage = Param->BytesPerPage;
@@ -585,9 +545,7 @@ static void XNandPsu_InitGeometry(XNandPsu *InstancePtr, OnfiParamPage *Param)
 ******************************************************************************/
 static void XNandPsu_InitFeatures(XNandPsu *InstancePtr, OnfiParamPage *Param)
 {
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertVoid(Param != NULL);
 
 	InstancePtr->Features.NvDdr = ((Param->Features & (1U << 5)) != 0U) ?
@@ -619,9 +577,7 @@ static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param)
 	u8 EccSetFeature[4] = {0x08U, 0x00U, 0x00U, 0x00U};
 	u8 EccGetFeature[4] ={0U};
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Param != NULL);
 
 	/*
@@ -637,38 +593,28 @@ static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param)
 	 *		 MT29F8G08ADADA, MT29F8G16ADADA
 	 */
 
-	/*
-	 * Read JEDEC ID
-	 */
+	/* Read JEDEC ID */
 	Status = XNandPsu_OnfiReadId(InstancePtr, 0U, 0x00U, 2U, &JedecId[0]);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
 
 	if ((JedecId[0] == 0x2CU) &&
-	/*
-	 * 1 Gb flash devices
-	 */
+	/* 1 Gb flash devices */
 	((JedecId[1] == 0xF1U) ||
 	(JedecId[1] == 0xA1U) ||
 	(JedecId[1] == 0xB1U) ||
-	/*
-	 * 2 Gb flash devices
-	 */
+	/* 2 Gb flash devices */
 	(JedecId[1] == 0xAAU) ||
 	(JedecId[1] == 0xBAU) ||
 	(JedecId[1] == 0xDAU) ||
 	(JedecId[1] == 0xCAU) ||
-	/*
-	 * 4 Gb flash devices
-	 */
+	/* 4 Gb flash devices */
 	(JedecId[1] == 0xACU) ||
 	(JedecId[1] == 0xBCU) ||
 	(JedecId[1] == 0xDCU) ||
 	(JedecId[1] == 0xCCU) ||
-	/*
-	 * 8 Gb flash devices
-	 */
+	/* 8 Gb flash devices */
 	(JedecId[1] == 0xA3U) ||
 	(JedecId[1] == 0xB3U) ||
 	(JedecId[1] == 0xD3U) ||
@@ -677,9 +623,7 @@ static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param)
 		xil_printf("%s: Ondie flash detected, jedec id 0x%x 0x%x\r\n",
 					__func__, JedecId[0], JedecId[1]);
 #endif
-		/*
-		 * On-Die Set Feature
-		 */
+		/* On-Die Set Feature */
 		Status = XNandPsu_SetFeature(InstancePtr, 0U, 0x90U,
 						&EccSetFeature[0]);
 		if (Status != XST_SUCCESS) {
@@ -689,9 +633,7 @@ static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param)
 #endif
 			goto Out;
 		}
-		/*
-		 * Check to see if ECC feature is set
-		 */
+		/* Check to see if ECC feature is set */
 		Status = XNandPsu_GetFeature(InstancePtr, 0U, 0x90U,
 						&EccGetFeature[0]);
 		if (Status != XST_SUCCESS) {
@@ -706,9 +648,7 @@ static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param)
 			Status = XST_SUCCESS;
 		}
 	} else {
-		/*
-		 * On-Die flash not found
-		 */
+		/* On-Die flash not found */
 		Status = XST_FAILURE;
 	}
 Out:
@@ -730,9 +670,7 @@ Out:
 ******************************************************************************/
 void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr)
 {
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
@@ -754,9 +692,7 @@ void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr)
 ******************************************************************************/
 void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr)
 {
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
@@ -778,9 +714,7 @@ void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr)
 ******************************************************************************/
 void XNandPsu_EnableEccMode(XNandPsu *InstancePtr)
 {
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
@@ -802,9 +736,7 @@ void XNandPsu_EnableEccMode(XNandPsu *InstancePtr)
 ******************************************************************************/
 void XNandPsu_DisableEccMode(XNandPsu *InstancePtr)
 {
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
@@ -872,15 +804,11 @@ static s32 XNandPsu_PollRegTimeout(XNandPsu *InstancePtr, u32 RegOffset,
 static void XNandPsu_SetPktSzCnt(XNandPsu *InstancePtr, u32 PktSize,
 						u32 PktCount)
 {
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertVoid(PktSize <= XNANDPSU_MAX_PKT_SIZE);
 	Xil_AssertVoid(PktCount <= XNANDPSU_MAX_PKT_COUNT);
 
-	/*
-	 * Update Packet Register with pkt size and count
-	 */
+	/* Update Packet Register with pkt size and count */
 	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_PKT_OFFSET,
 				((u32)XNANDPSU_PKT_PKT_SIZE_MASK |
 				(u32)XNANDPSU_PKT_PKT_CNT_MASK),
@@ -906,17 +834,13 @@ static void XNandPsu_SetPktSzCnt(XNandPsu *InstancePtr, u32 PktSize,
 ******************************************************************************/
 static void XNandPsu_SetPageColAddr(XNandPsu *InstancePtr, u32 Page, u16 Col)
 {
-	/*
-	 * Program Memory Address Register 1
-	 */
+	/* Program Memory Address Register 1 */
 	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
 				XNANDPSU_MEM_ADDR1_OFFSET,
 				(((u32)Col & XNANDPSU_MEM_ADDR1_COL_ADDR_MASK) |
 				((Page << (u32)XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT) &
 				XNANDPSU_MEM_ADDR1_PG_ADDR_MASK)));
-	/*
-	 * Program Memory Address Register 2
-	 */
+	/* Program Memory Address Register 2 */
 	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
 				XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK,
 				((Page >> XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT) &
@@ -941,9 +865,7 @@ static void XNandPsu_SetPageSize(XNandPsu *InstancePtr)
 	u32 PageSizeMask = 0;
 	u32 PageSize = InstancePtr->Geometry.BytesPerPage;
 
-	/*
-	 * Calculate page size mask
-	 */
+	/* Calculate page size mask */
 	switch(PageSize) {
 		case XNANDPSU_PAGE_SIZE_512:
 			PageSizeMask = (0U << XNANDPSU_CMD_PG_SIZE_SHIFT);
@@ -964,14 +886,10 @@ static void XNandPsu_SetPageSize(XNandPsu *InstancePtr)
 			PageSizeMask = (5U << XNANDPSU_CMD_PG_SIZE_SHIFT);
 			break;
 		default:
-			/*
-			 * Not supported
-			 */
+			/* Not supported */
 			break;
 	}
-	/*
-	 * Update Command Register
-	 */
+	/* Update Command Register */
 	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_CMD_OFFSET,
 				XNANDPSU_CMD_PG_SIZE_MASK, PageSizeMask);
 }
@@ -1038,9 +956,7 @@ static void XNandPsu_SetEccAddrSize(XNandPsu *InstancePtr)
 		} else {
 			InstancePtr->EccCfg.IsBCH = 1U;
 		}
-		/*
-		 * Write ECC register
-		 */
+		/* Write ECC register */
 		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
 				(u32)XNANDPSU_ECC_OFFSET,
 				((u32)InstancePtr->EccCfg.EccAddr |
@@ -1048,9 +964,7 @@ static void XNandPsu_SetEccAddrSize(XNandPsu *InstancePtr)
 				((u32)InstancePtr->EccCfg.IsBCH << (u32)27)));
 
 		if (EccMatrix[Found].IsBCH == XNANDPSU_BCH) {
-			/*
-			 * Write memory address register 2
-			 */
+			/* Write memory address register 2 */
 			switch(InstancePtr->EccCfg.NumEccBits) {
 				case 16U:
 					BchModeVal = 0x0U;
@@ -1117,9 +1031,7 @@ static void XNandPsu_SetEccSpareCmd(XNandPsu *InstancePtr, u16 SpareCmd,
 ******************************************************************************/
 static void XNandPsu_SelectChip(XNandPsu *InstancePtr, u32 Target)
 {
-	/*
-	 * Update Memory Address2 register with chip select
-	 */
+	/* Update Memory Address2 register with chip select */
 	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
 			XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK,
 			((Target << XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT) &
@@ -1145,35 +1057,23 @@ static s32 XNandPsu_OnfiReset(XNandPsu *InstancePtr, u32 Target)
 {
 	s32 Status = XST_FAILURE;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 
-	/*
-	 * Enable Transfer Complete Interrupt in Interrupt Status Register
-	 */
+	/* Enable Transfer Complete Interrupt in Interrupt Status Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 		XNANDPSU_INTR_STS_EN_OFFSET,
 		XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
-	/*
-	 * Program Command Register
-	 */
+	/* Program Command Register */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RST, ONFI_CMD_INVALID, 0U,
 			0U, 0U);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Set Reset in Program Register
-	 */
+	/* Set Reset in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 		XNANDPSU_PROG_OFFSET, XNANDPSU_PROG_RST_MASK);
 
-	/*
-	 * Poll for Transfer Complete event
-	 */
+	/* Poll for Transfer Complete event */
 	Status = XNandPsu_WaitFor_Transfer_Complete(InstancePtr);
 
 	return Status;
@@ -1200,46 +1100,30 @@ static s32 XNandPsu_OnfiReadStatus(XNandPsu *InstancePtr, u32 Target,
 {
 	s32 Status = XST_FAILURE;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(OnfiStatus != NULL);
-	/*
-	 * Enable Transfer Complete Interrupt in Interrupt Status Register
-	 */
+	/* Enable Transfer Complete Interrupt in Interrupt Status Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 		XNANDPSU_INTR_STS_EN_OFFSET,
 		XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
-	/*
-	 * Program Command Register
-	 */
+	/* Program Command Register */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_STS, ONFI_CMD_INVALID,
 				0U, 0U, 0U);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	if(InstancePtr->DataInterface == XNANDPSU_SDR)
 		XNandPsu_SetPktSzCnt(InstancePtr, 1U, 1U);
 	else
 		XNandPsu_SetPktSzCnt(InstancePtr, 2U, 1U);
 
-	/*
-	 * Set Read Status in Program Register
-	 */
+	/* Set Read Status in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_STS_MASK);
-	/*
-	 * Poll for Transfer Complete event
-	 */
+	/* Poll for Transfer Complete event */
 	Status = XNandPsu_WaitFor_Transfer_Complete(InstancePtr);
-	/*
-	 * Read Flash Status
-	 */
+	/* Read Flash Status */
 	*OnfiStatus = (u16) XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
 						XNANDPSU_FLASH_STS_OFFSET);
 
@@ -1272,9 +1156,7 @@ static s32 XNandPsu_OnfiReadId(XNandPsu *InstancePtr, u32 Target, u8 IdAddr,
 	u32 RegVal;
 	u32 RemIdx;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Buf != NULL);
 
@@ -1285,33 +1167,21 @@ static s32 XNandPsu_OnfiReadId(XNandPsu *InstancePtr, u32 Target, u8 IdAddr,
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 		XNANDPSU_INTR_STS_EN_OFFSET,
 		XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
-	/*
-	 * Program Command
-	 */
+	/* Program Command */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_ID, ONFI_CMD_INVALID, 0U,
 					0U, ONFI_READ_ID_ADDR_CYCLES);
 
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, 0U, IdAddr);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, IdLen, 1U);
-	/*
-	 * Set Read ID in Program Register
-	 */
+	/* Set Read ID in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_ID_MASK);
 
-	/*
-	 * Poll for Buffer Read Ready event
-	 */
+	/* Poll for Buffer Read Ready event */
 	Status = XNandPsu_PollRegTimeout(
 		InstancePtr,
 		XNANDPSU_INTR_STS_OFFSET,
@@ -1340,9 +1210,7 @@ static s32 XNandPsu_OnfiReadId(XNandPsu *InstancePtr, u32 Target, u8 IdAddr,
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_INTR_STS_OFFSET,
 			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
-	/*
-	 * Read Packet Data from Data Port Register
-	 */
+	/* Read Packet Data from Data Port Register */
 	for (Index = 0U; Index < (IdLen/4); Index++) {
 		*(BufPtr+Index) = XNandPsu_ReadReg(
 					InstancePtr->Config.BaseAddress,
@@ -1387,9 +1255,7 @@ static s32 XNandPsu_OnfiReadParamPage(XNandPsu *InstancePtr, u32 Target,
 {
 	s32 Status = XST_FAILURE;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Buf != NULL);
 
@@ -1400,26 +1266,16 @@ static s32 XNandPsu_OnfiReadParamPage(XNandPsu *InstancePtr, u32 Target,
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 		XNANDPSU_INTR_STS_EN_OFFSET,
 		XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
-	/*
-	 * Program Command
-	 */
+	/* Program Command */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_PRM_PG, ONFI_CMD_INVALID,
 					0U, 0U, ONFI_PRM_PG_ADDR_CYCLES);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, 0U, 0U);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, ONFI_PRM_PG_LEN, 1U);
-	/*
-	 * Set Read Parameter Page in Program Register
-	 */
+	/* Set Read Parameter Page in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_PRM_PG_MASK);
 
@@ -1463,14 +1319,10 @@ static s32 XNandPsu_CalculateLength(XNandPsu *InstancePtr, u64 Offset,
 			Status = XST_FAILURE;
 			goto Out;
 		}
-		/*
-		 * Check if the block is bad
-		 */
+		/* Check if the block is bad */
 		Status = XNandPsu_IsBlockBad(InstancePtr, Block);
 		if (Status != XST_SUCCESS) {
-			/*
-			 * Good block
-			 */
+			/* Good block */
 			TempLen += BlockLen;
 		}
 		OffsetVar += BlockLen;
@@ -1513,9 +1365,7 @@ s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 	u64 OffsetVar = Offset;
 	u64 LengthVar = Length;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(SrcBuf != NULL);
@@ -1543,9 +1393,7 @@ s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 			OffsetVar += (u64)InstancePtr->Geometry.BlockSize;
 			continue;
 		}
-		/*
-		 * Calculate Page and Column address values
-		 */
+		/* Calculate Page and Column address values */
 		Page = (u32) (OffsetVar/InstancePtr->Geometry.BytesPerPage);
 		Col = (u32) (OffsetVar &
 				(InstancePtr->Geometry.BytesPerPage - 1U));
@@ -1566,9 +1414,7 @@ s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 			Page %= InstancePtr->Geometry.NumTargetPages;
 		}
 
-		/*
-		 * Check if partial write
-		 */
+		/* Check if partial write */
 		if (PartialBytes > 0U) {
 			BufPtr = &InstancePtr->PartialDataBuf[0];
 			(void)memset(BufPtr, 0xFF,
@@ -1583,9 +1429,7 @@ s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 					InstancePtr->Geometry.BytesPerPage :
 					(u32)LengthVar;
 		}
-		/*
-		 * Program page
-		 */
+		/* Program page */
 		Status = XNandPsu_ProgramPage(InstancePtr, Target, Page, 0U,
 								BufPtr);
 		if (Status != XST_SUCCESS)
@@ -1636,9 +1480,7 @@ s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
 	u64 OffsetVar = Offset;
 	u64 LengthVar = Length;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(LengthVar != 0U);
@@ -1665,9 +1507,7 @@ s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
 			OffsetVar += (u64)InstancePtr->Geometry.BlockSize;
 			continue;
 		}
-		/*
-		 * Calculate Page and Column address values
-		 */
+		/* Calculate Page and Column address values */
 		Page = (u32) (OffsetVar/InstancePtr->Geometry.BytesPerPage);
 		Col = (u32) (OffsetVar &
 				(InstancePtr->Geometry.BytesPerPage - 1U));
@@ -1687,9 +1527,7 @@ s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
 		if (Page > InstancePtr->Geometry.NumTargetPages) {
 			Page %= InstancePtr->Geometry.NumTargetPages;
 		}
-		/*
-		 * Check if partial read
-		 */
+		/* Check if partial read */
 		if (PartialBytes > 0U) {
 			BufPtr = &InstancePtr->PartialDataBuf[0];
 			NumBytes = PartialBytes;
@@ -1700,9 +1538,7 @@ s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
 					InstancePtr->Geometry.BytesPerPage :
 					(u32)LengthVar;
 		}
-		/*
-		 * Read page
-		 */
+		/* Read page */
 		Status = XNandPsu_ReadPage(InstancePtr, Target, Page, 0U,
 								BufPtr);
 		if (Status != XST_SUCCESS) {
@@ -1753,9 +1589,7 @@ s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length)
 	u64 OffsetVar = Offset;
 	u64 LengthVar = Length;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(LengthVar != 0U);
@@ -1770,9 +1604,7 @@ s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length)
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
-	/*
-	 * Calculate number of blocks to erase
-	 */
+	/* Calculate number of blocks to erase */
 	StartBlock = (u32) (OffsetVar/InstancePtr->Geometry.BlockSize);
 
 	while (LengthVar > 0U) {
@@ -1853,9 +1685,7 @@ static s32 XNandPsu_ProgramPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 	u32 IsrValue;
 	u32 Index;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Page < InstancePtr->Geometry.NumPages);
 	Xil_AssertNonvoid(Buf != NULL);
 
@@ -1880,32 +1710,20 @@ static s32 XNandPsu_ProgramPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 
 		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			   XNANDPSU_INTR_STS_EN_OFFSET, IsrValue);
-	/*
-	 * Program Page Size
-	 */
+	/* Program Page Size */
 	XNandPsu_SetPageSize(InstancePtr);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, Page, (u16)Col);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Set ECC
-	 */
+	/* Set ECC */
 	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
 		XNandPsu_SetEccSpareCmd(InstancePtr, ONFI_CMD_CHNG_WR_COL,
 					InstancePtr->Geometry.ColAddrCycles);
 	}
-	/*
-	 * Set Page Program in Program Register
-	 */
+	/* Set Page Program in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_PG_PROG_MASK);
 
@@ -1954,9 +1772,7 @@ s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 	u32 PageVar = Page;
 	u32 RegVal;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(PageVar < InstancePtr->Geometry.NumPages);
@@ -1965,9 +1781,7 @@ s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 	PageVar %= InstancePtr->Geometry.NumTargetPages;
 
 	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
-		/*
-		 * Calculate ECC free positions before and after ECC code
-		 */
+		/* Calculate ECC free positions before and after ECC code */
 		PreEccSpareCol = 0x0U;
 		PreEccSpareWrCnt = InstancePtr->EccCfg.EccAddr -
 				(u16)InstancePtr->Geometry.BytesPerPage;
@@ -1996,9 +1810,7 @@ s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 							PostEccSpareCol;
 			BufPtr = (u32 *)(Buf + Col);
 		} else {
-			/*
-			 * No free spare bytes available for writing
-			 */
+			/* No free spare bytes available for writing */
 			Status = XST_FAILURE;
 			goto Out;
 		}
@@ -2014,9 +1826,7 @@ s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 
 		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			   XNANDPSU_INTR_STS_EN_OFFSET, RegVal);
-	/*
-	 * Program Command hack for change write column
-	 */
+	/* Program Command hack for change write column */
 	if (PostWrite > 0U) {
 		Cmd.Command1 = 0x80U;
 		Cmd.Command2 = 0x00U;
@@ -2027,25 +1837,15 @@ s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 		XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_PG_PROG1,
 				ONFI_CMD_PG_PROG2, 0U , 1U, (u8)AddrCycles);
 	}
-	/*
-	 * Program Page Size
-	 */
+	/* Program Page Size */
 	XNandPsu_SetPageSize(InstancePtr);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Set Page Program in Program Register
-	 */
+	/* Set Page Program in Program Register */
 	if (PostWrite > 0U) {
 		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,((u32)XNANDPSU_PROG_PG_PROG_MASK |
@@ -2103,9 +1903,7 @@ static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 	s32 Status = XST_FAILURE;
 	u32 Index, RegVal;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Page < InstancePtr->Geometry.NumPages);
 	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 
@@ -2134,25 +1932,15 @@ static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 
 		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			   XNANDPSU_INTR_STS_EN_OFFSET, RegVal);
-	/*
-	 * Program Page Size
-	 */
+	/* Program Page Size */
 	XNandPsu_SetPageSize(InstancePtr);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, Page, (u16)Col);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Set ECC
-	 */
+	/* Set ECC */
 	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
 		XNandPsu_SetEccSpareCmd(InstancePtr,
 					(ONFI_CMD_CHNG_RD_COL1 |
@@ -2160,22 +1948,16 @@ static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 					InstancePtr->Geometry.ColAddrCycles);
 	}
 
-	/*
-	 * Set Read command in Program Register
-	 */
+	/* Set Read command in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 				XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
 
 	Status = XNandPsu_Data_ReadWrite(InstancePtr, Buf, PktCount, PktSize, 0, 1);
 
 CheckEccError:
-	/*
-	 * Check ECC Errors
-	 */
+	/* Check ECC Errors */
 	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
-		/*
-		 * Hamming Multi Bit Errors
-		 */
+		/* Hamming Multi Bit Errors */
 		if (((u32)XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
 				XNANDPSU_INTR_STS_OFFSET) &
 			(u32)XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK) != 0U) {
@@ -2197,9 +1979,7 @@ CheckEccError:
 					InstancePtr->Ecc_Stat_PerPage_flips;
 			Status = XST_FAILURE;
 		}
-		/*
-		 * Hamming Single Bit or BCH Errors
-		 */
+		/* Hamming Single Bit or BCH Errors */
 		if (((u32)XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
 				XNANDPSU_INTR_STS_OFFSET) &
 			(u32)XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK) != 0U) {
@@ -2256,9 +2036,7 @@ s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 	u32 PageVar = Page;
 	u32 RegVal;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(PageVar < InstancePtr->Geometry.NumPages);
@@ -2275,30 +2053,18 @@ s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 	}
 		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			   XNANDPSU_INTR_STS_EN_OFFSET, RegVal);
-	/*
-	 * Program Command
-	 */
+	/* Program Command */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD1, ONFI_CMD_RD2, 0U,
 						1U, (u8)AddrCycles);
-	/*
-	 * Program Page Size
-	 */
+	/* Program Page Size */
 	XNandPsu_SetPageSize(InstancePtr);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Set Read command in Program Register
-	 */
+	/* Set Read command in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 				XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
 
@@ -2331,9 +2097,7 @@ s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block)
 	u32 ErasePage;
 	u32 EraseCol;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
@@ -2351,27 +2115,17 @@ s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block)
 			XNANDPSU_INTR_STS_EN_OFFSET,
 			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 
-	/*
-	 * Program Command
-	 */
+	/* Program Command */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_BLK_ERASE1,
 			ONFI_CMD_BLK_ERASE2, 0U , 0U, (u8)AddrCycles);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, ErasePage, (u16)EraseCol);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Set Block Erase in Program Register
-	 */
+	/* Set Block Erase in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_BLK_ERASE_MASK);
-	/*
-	 * Poll for Transfer Complete event
-	 */
+	/* Poll for Transfer Complete event */
 	Status = XNandPsu_WaitFor_Transfer_Complete(InstancePtr);
 	return Status;
 }
@@ -2402,9 +2156,7 @@ s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 	u32 PktCount = 1;
 	u32 *BufPtr = (u32 *)(void *)Buf;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Buf != NULL);
 
 	if (InstancePtr->DataInterface == XNANDPSU_NVDDR) {
@@ -2418,26 +2170,16 @@ s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_INTR_STS_EN_OFFSET,
 			XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
-	/*
-	 * Program Command
-	 */
+	/* Program Command */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_GET_FEATURES,
 				ONFI_CMD_INVALID, 0U, 0U, 1U);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, 0x0U, Feature);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
-	/*
-	 * Set Read Parameter Page in Program Register
-	 */
+	/* Set Read Parameter Page in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_GET_FEATURES_MASK);
 
@@ -2472,9 +2214,7 @@ s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 	u32 PktCount = 1U;
 	u32 *BufPtr = (u32 *)(void *)Buf;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Buf != NULL);
 	if (InstancePtr->DataInterface == XNANDPSU_NVDDR) {
 		PktSize = 8U;
@@ -2491,26 +2231,16 @@ s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 			XNANDPSU_INTR_STS_EN_OFFSET,
 			XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
 
-	/*
-	 * Program Command
-	 */
+	/* Program Command */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_SET_FEATURES,
 				ONFI_CMD_INVALID, 0U , 0U, 1U);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, 0x0U, Feature);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
-	/*
-	 * Set Read Parameter Page in Program Register
-	 */
+	/* Set Read Parameter Page in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_SET_FEATURES_MASK);
 
@@ -2534,9 +2264,7 @@ s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 ******************************************************************************/
 static void XNandPsu_ChangeClockFreq(XNandPsu *InstancePtr, u32 ClockFreq)
 {
-	/*
-	 * Not implemented
-	 */
+	/* Not implemented */
 }
 /*****************************************************************************/
 /**
@@ -2567,15 +2295,11 @@ s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 	u32 SetFeature = 0U;
 	u32 NewModeVar = (u32)NewMode;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/*
-	 * Check for valid input arguments
-	 */
+	/* Check for valid input arguments */
 	if(((NewIntf != XNANDPSU_SDR) && (NewIntf != XNANDPSU_NVDDR)) ||
 			(NewModeVar > 5U)){
 		Status = XST_FAILURE;
@@ -2585,15 +2309,11 @@ s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 	if(NewIntf == XNANDPSU_NVDDR){
 		NewModeVar = NewModeVar | (u32)0x10;
 	}
-	/*
-	 * Get current data interface type and timing mode
-	 */
+	/* Get current data interface type and timing mode */
 	XNandPsu_DataInterface CurIntf = InstancePtr->DataInterface;
 	XNandPsu_TimingMode CurMode = InstancePtr->TimingMode;
 
-	/*
-	 * Check if the flash is in same mode
-	 */
+	/* Check if the flash is in same mode */
 	if ((CurIntf == NewIntf) && (CurMode == NewModeVar)) {
 		Status = XST_SUCCESS;
 		goto Out;
@@ -2603,14 +2323,10 @@ s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 
 		NewModeVar = XNANDPSU_SDR0;
 
-		/*
-		 * Change the clock frequency
-		 */
+		/* Change the clock frequency */
 		XNandPsu_ChangeClockFreq(InstancePtr, XNANDPSU_SDR_CLK);
 
-		/*
-		 * Update Data Interface Register
-		 */
+		/* Update Data Interface Register */
 		RegVal = ((NewModeVar % 6U) << ((NewIntf == XNANDPSU_NVDDR) ? 3U : 0U)) |
 				((u32)NewIntf << XNANDPSU_DATA_INTF_DATA_INTF_SHIFT);
 		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
@@ -2624,9 +2340,7 @@ s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 			}
 		}
 
-		/*
-		 * Set Feature
-		 */
+		/* Set Feature */
 		for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
 								Target++) {
 			Status = XNandPsu_SetFeature(InstancePtr, Target, 0x01U,
@@ -2646,9 +2360,7 @@ s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
-			/*
-			 * Check if set_feature was successful
-			 */
+			/* Check if set_feature was successful */
 			if (*Feature != NewModeVar) {
 				Status = XST_FAILURE;
 				goto Out;
@@ -2662,9 +2374,7 @@ s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 	if((CurIntf == XNANDPSU_NVDDR) && (NewIntf == XNANDPSU_NVDDR)){
 		SetFeature |= SetFeature << 8U;
 	}
-	/*
-	 * Set Feature
-	 */
+	/* Set Feature */
 	for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
 							Target++) {
 		Status = XNandPsu_SetFeature(InstancePtr, Target, 0x01U,
@@ -2676,17 +2386,13 @@ s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 
 	InstancePtr->DataInterface = NewIntf;
 	InstancePtr->TimingMode = NewModeVar;
-	/*
-	 * Update Data Interface Register
-	 */
+	/* Update Data Interface Register */
 	RegVal = ((NewMode % 6U) << ((NewIntf == XNANDPSU_NVDDR) ? 3U : 0U)) |
 			((u32)NewIntf << XNANDPSU_DATA_INTF_DATA_INTF_SHIFT);
 	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
 				XNANDPSU_DATA_INTF_OFFSET, RegVal);
 
-	/*
-	 * Get Feature
-	 */
+	/* Get Feature */
 	for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
 							Target++) {
 		Status = XNandPsu_GetFeature(InstancePtr, Target, 0x01U,
@@ -2695,9 +2401,7 @@ s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
 			goto Out;
 		}
 
-		/*
-		 * Check if set_feature was successful
-		 */
+		/* Check if set_feature was successful */
 		if (*Feature != NewModeVar) {
 			Status = XST_FAILURE;
 			goto Out;
@@ -2739,9 +2443,7 @@ static s32 XNandPsu_ChangeReadColumn(XNandPsu *InstancePtr, u32 Target,
 	u32 Index;
 	u32 RegVal;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Buf != NULL);
 
@@ -2756,30 +2458,18 @@ static s32 XNandPsu_ChangeReadColumn(XNandPsu *InstancePtr, u32 Target,
 
 		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			   XNANDPSU_INTR_STS_EN_OFFSET, RegVal);
-	/*
-	 * Program Command
-	 */
+	/* Program Command */
 	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_CHNG_RD_COL1,
 			ONFI_CMD_CHNG_RD_COL2, 0U , 1U, (u8)AddrCycles);
-	/*
-	 * Program Page Size
-	 */
+	/* Program Page Size */
 	XNandPsu_SetPageSize(InstancePtr);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, 0U, (u16)Col);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Set Read command in Program Register
-	 */
+	/* Set Read command in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
 
@@ -2820,9 +2510,7 @@ static s32 XNandPsu_ChangeWriteColumn(XNandPsu *InstancePtr, u32 Target,
 	u32 Index;
 	u32 RegVal;
 
-	/*
-	 * Assert the input arguments.
-	 */
+	/* Assert the input arguments. */
 	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Buf != NULL);
 
@@ -2840,33 +2528,21 @@ static s32 XNandPsu_ChangeWriteColumn(XNandPsu *InstancePtr, u32 Target,
 
 		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 			   XNANDPSU_INTR_STS_EN_OFFSET, RegVal);
-	/*
-	 * Change write column hack
-	 */
+	/* Change write column hack */
 	OnfiCommand.Command1 = 0x85U;
 	OnfiCommand.Command2 = 0x10U;
 	XNandPsu_Prepare_Cmd(InstancePtr, OnfiCommand.Command1,
 				OnfiCommand.Command2, 0U , 0U, (u8)AddrCycles);
 
-	/*
-	 * Program Page Size
-	 */
+	/* Program Page Size */
 	XNandPsu_SetPageSize(InstancePtr);
-	/*
-	 * Program Column, Page, Block address
-	 */
+	/* Program Column, Page, Block address */
 	XNandPsu_SetPageColAddr(InstancePtr, 0U, (u16)Col);
-	/*
-	 * Program Packet Size and Packet Count
-	 */
+	/* Program Packet Size and Packet Count */
 	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
-	/*
-	 * Program Memory Address Register2 for chip select
-	 */
+	/* Program Memory Address Register2 for chip select */
 	XNandPsu_SelectChip(InstancePtr, Target);
-	/*
-	 * Set Page Program in Program Register
-	 */
+	/* Set Page Program in Program Register */
 	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
 		XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK);
 
diff --git a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h
index 6a54706f..221c3697 100644
--- a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h
@@ -301,9 +301,7 @@ typedef struct {
  * The XNandPsu_Geometry structure contains the ONFI geometry information.
  */
 typedef struct {
-	/*
-	 * Parameter page information
-	 */
+	/* Parameter page information */
 	u32 BytesPerPage;	/**< Number of bytes per page */
 	u16 SpareBytesPerPage;	/**< Number of spare bytes per page */
 	u32 PagesPerBlock;	/**< Number of pages per block */
@@ -314,9 +312,7 @@ typedef struct {
 	u8 NumBitsPerCell;	/**< Number of bits per cell (Hamming/BCH) */
 	u8 NumBitsECC;		/**< Number of bits ECC correctability */
 	u32 EccCodeWordSize;	/**< ECC codeword size */
-	/*
-	 * Driver specific information
-	 */
+	/* Driver specific information */
 	u32 BlockSize;		/**< Block size */
 	u32 NumTargetPages;	/**< Total number of pages in a Target */
 	u32 NumTargetBlocks;	/**< Total number of blocks in a Target */
@@ -560,9 +556,7 @@ void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
 void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
 			u8 DmaMode, u8 AddrCycles);
 
-/*
- * XNandPsu_LookupConfig in xnandpsu_sinit.c
- */
+/* XNandPsu_LookupConfig in xnandpsu_sinit.c */
 XNandPsu_Config *XNandPsu_LookupConfig(u16 DevID);
 
 
diff --git a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.c b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.c
index 18f003b5..fe36ae7f 100644
--- a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.c
@@ -105,9 +105,7 @@ void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr)
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/*
-	 * Initialize primary Bad Block Table(BBT)
-	 */
+	/* Initialize primary Bad Block Table(BBT) */
 	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
 		InstancePtr->BbtDesc.PageOffset[Index] =
 						XNANDPSU_BBT_DESC_PAGE_OFFSET;
@@ -127,17 +125,13 @@ void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr)
 	}
 	InstancePtr->BbtDesc.Valid = 0U;
 
-	/*
-	 * Assuming that the flash device will have at least 4 blocks.
-	 */
+	/* Assuming that the flash device will have at least 4 blocks. */
 	if (InstancePtr->Geometry.NumTargetBlocks <= InstancePtr->
 							BbtDesc.MaxBlocks){
 		InstancePtr->BbtDesc.MaxBlocks = 4U;
 	}
 
-	/*
-	 * Initialize mirror Bad Block Table(BBT)
-	 */
+	/* Initialize mirror Bad Block Table(BBT) */
 	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
 		InstancePtr->BbtMirrorDesc.PageOffset[Index] =
 						XNANDPSU_BBT_DESC_PAGE_OFFSET;
@@ -161,17 +155,13 @@ void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr)
 	}
 	InstancePtr->BbtMirrorDesc.Valid = 0U;
 
-	/*
-	 * Assuming that the flash device will have at least 4 blocks.
-	 */
+	/* Assuming that the flash device will have at least 4 blocks. */
 	if (InstancePtr->Geometry.NumTargetBlocks <= InstancePtr->
 						BbtMirrorDesc.MaxBlocks){
 		InstancePtr->BbtMirrorDesc.MaxBlocks = 4U;
 	}
 
-	/*
-	 * Initialize Bad block search pattern structure
-	 */
+	/* Initialize Bad block search pattern structure */
 	if (InstancePtr->Geometry.BytesPerPage > 512U) {
 		/* For flash page size > 512 bytes */
 		InstancePtr->BbPattern.Options = XNANDPSU_BBT_SCAN_2ND_PAGE;
@@ -216,32 +206,22 @@ static void XNandPsu_CreateBbt(XNandPsu *InstancePtr, u32 Target)
 	u32 NumBlocks = InstancePtr->Geometry.NumTargetBlocks;
 	s32 Status;
 
-	/*
-	 * Number of pages to search for bad block pattern
-	 */
+	/* Number of pages to search for bad block pattern */
 	if ((InstancePtr->BbPattern.Options & XNANDPSU_BBT_SCAN_2ND_PAGE) != 0U)
 	{
 		NumPages = 2U;
 	} else {
 		NumPages = 1U;
 	}
-	/*
-	 * Scan all the blocks for factory marked bad blocks
-	 */
+	/* Scan all the blocks for factory marked bad blocks */
 	for(BlockIndex = StartBlock; BlockIndex < (StartBlock + NumBlocks);
 							BlockIndex++) {
-		/*
-		 * Block offset in Bad Block Table(BBT) entry
-		 */
+		/* Block offset in Bad Block Table(BBT) entry */
 		BlockOffset = BlockIndex >> XNANDPSU_BBT_BLOCK_SHIFT;
-		/*
-		 * Block shift value in the byte
-		 */
+		/* Block shift value in the byte */
 		BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
 		Page = BlockIndex * InstancePtr->Geometry.PagesPerBlock;
-		/*
-		 * Search for the bad block pattern
-		 */
+		/* Search for the bad block pattern */
 		for(PageIndex = 0U; PageIndex < NumPages; PageIndex++) {
 			Status = XNandPsu_ReadSpareBytes(InstancePtr,
 					(Page + PageIndex), &Buf[0]);
@@ -297,9 +277,7 @@ s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr)
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	/*
-	 * Zero the RAM based Bad Block Table(BBT) entries
-	 */
+	/* Zero the RAM based Bad Block Table(BBT) entries */
 	BbtLen = InstancePtr->Geometry.NumBlocks >>
 					XNANDPSU_BBT_BLOCK_SHIFT;
 	(void)memset(&InstancePtr->Bbt[0], 0, BbtLen);
@@ -307,22 +285,16 @@ s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr)
 	for (Index = 0U; Index < InstancePtr->Geometry.NumTargets; Index++) {
 
 		if (XNandPsu_ReadBbt(InstancePtr, Index) != XST_SUCCESS) {
-			/*
-			 * Create memory based Bad Block Table(BBT)
-			 */
+			/* Create memory based Bad Block Table(BBT) */
 			XNandPsu_CreateBbt(InstancePtr, Index);
-			/*
-			 * Write the Bad Block Table(BBT) to the flash
-			 */
+			/* Write the Bad Block Table(BBT) to the flash */
 			Status = XNandPsu_WriteBbt(InstancePtr,
 					&InstancePtr->BbtDesc,
 					&InstancePtr->BbtMirrorDesc, Index);
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
-			/*
-			 * Write the Mirror Bad Block Table(BBT) to the flash
-			 */
+			/* Write the Mirror Bad Block Table(BBT) to the flash */
 			Status = XNandPsu_WriteBbt(InstancePtr,
 					&InstancePtr->BbtMirrorDesc,
 					&InstancePtr->BbtDesc, Index);
@@ -379,13 +351,9 @@ static void XNandPsu_ConvertBbt(XNandPsu *InstancePtr, u8 *Buf, u32 Target)
 	for(BlockOffset = StartBlock; BlockOffset < (StartBlock + BbtLen);
 						BlockOffset++) {
 		Data = *(Buf + BlockOffset);
-		/*
-		 * Clear the RAM based Bad Block Table(BBT) contents
-		 */
+		/* Clear the RAM based Bad Block Table(BBT) contents */
 		InstancePtr->Bbt[BlockOffset] = 0x0U;
-		/*
-		 * Loop through the every 4 blocks in the bitmap
-		 */
+		/* Loop through the every 4 blocks in the bitmap */
 		for(BlockIndex = 0U; BlockIndex < XNANDPSU_BBT_ENTRY_NUM_BLOCKS;
 				BlockIndex++) {
 			BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
@@ -447,9 +415,7 @@ static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target)
 	XNandPsu_BbtDesc *MirrorDesc = &InstancePtr->BbtMirrorDesc;
 	BufLen = InstancePtr->Geometry.NumBlocks >>
 			XNANDPSU_BBT_BLOCK_SHIFT;
-	/*
-	 * Search the Bad Block Table(BBT) in flash
-	 */
+	/* Search the Bad Block Table(BBT) in flash */
 	Status1 = XNandPsu_SearchBbt(InstancePtr, Desc, Target);
 	Status2 = XNandPsu_SearchBbt(InstancePtr, MirrorDesc, Target);
 	if ((Status1 != XST_SUCCESS) && (Status2 != XST_SUCCESS)) {
@@ -462,13 +428,9 @@ static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target)
 #ifdef XNANDPSU_DEBUG
 	xil_printf("%s: Bad block table found\r\n",__func__);
 #endif
-	/*
-	 * Bad Block Table found
-	 */
+	/* Bad Block Table found */
 	if ((Desc->Valid != 0U) && (MirrorDesc->Valid != 0U)) {
-		/*
-		 * Valid BBT & Mirror BBT found
-		 */
+		/* Valid BBT & Mirror BBT found */
 		if (Desc->Version[Target] > MirrorDesc->Version[Target]) {
 			Offset = (u64)Desc->PageOffset[Target] *
 				(u64)InstancePtr->Geometry.BytesPerPage;
@@ -477,15 +439,11 @@ static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target)
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
-			/*
-			 * Convert flash BBT to memory based BBT
-			 */
+			/* Convert flash BBT to memory based BBT */
 			XNandPsu_ConvertBbt(InstancePtr, &Buf[0], Target);
 			MirrorDesc->Version[Target] = Desc->Version[Target];
 
-			/*
-			 * Write the BBT to Mirror BBT location in flash
-			 */
+			/* Write the BBT to Mirror BBT location in flash */
 			Status = XNandPsu_WriteBbt(InstancePtr, MirrorDesc,
 							Desc, Target);
 			if (Status != XST_SUCCESS) {
@@ -500,15 +458,11 @@ static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target)
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
-			/*
-			 * Convert flash BBT to memory based BBT
-			 */
+			/* Convert flash BBT to memory based BBT */
 			XNandPsu_ConvertBbt(InstancePtr, &Buf[0], Target);
 			Desc->Version[Target] = MirrorDesc->Version[Target];
 
-			/*
-			 * Write the Mirror BBT to BBT location in flash
-			 */
+			/* Write the Mirror BBT to BBT location in flash */
 			Status = XNandPsu_WriteBbt(InstancePtr, Desc,
 							MirrorDesc, Target);
 			if (Status != XST_SUCCESS) {
@@ -523,54 +477,40 @@ static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target)
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
-			/*
-			 * Convert flash BBT to memory based BBT
-			 */
+			/* Convert flash BBT to memory based BBT */
 			XNandPsu_ConvertBbt(InstancePtr, &Buf[0], Target);
 		}
 	} else if (Desc->Valid != 0U) {
-		/*
-		 * Valid Primary BBT found
-		 */
+		/* Valid Primary BBT found */
 		Offset = (u64)Desc->PageOffset[Target] *
 			(u64)InstancePtr->Geometry.BytesPerPage;
 		Status = XNandPsu_Read(InstancePtr, Offset, BufLen, &Buf[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
-		/*
-		 * Convert flash BBT to memory based BBT
-		 */
+		/* Convert flash BBT to memory based BBT */
 		XNandPsu_ConvertBbt(InstancePtr, &Buf[0], Target);
 		MirrorDesc->Version[Target] = Desc->Version[Target];
 
-		/*
-		 * Write the BBT to Mirror BBT location in flash
-		 */
+		/* Write the BBT to Mirror BBT location in flash */
 		Status = XNandPsu_WriteBbt(InstancePtr, MirrorDesc, Desc,
 								Target);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
 	} else {
-		/*
-		 * Valid Mirror BBT found
-		 */
+		/* Valid Mirror BBT found */
 		Offset = (u64)MirrorDesc->PageOffset[Target] *
 			(u64)InstancePtr->Geometry.BytesPerPage;
 		Status = XNandPsu_Read(InstancePtr, Offset, BufLen, &Buf[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
-		/*
-		 * Convert flash BBT to memory based BBT
-		 */
+		/* Convert flash BBT to memory based BBT */
 		XNandPsu_ConvertBbt(InstancePtr, &Buf[0], Target);
 		Desc->Version[Target] = MirrorDesc->Version[Target];
 
-		/*
-		 * Write the Mirror BBT to BBT location in flash
-		 */
+		/* Write the Mirror BBT to BBT location in flash */
 		Status = XNandPsu_WriteBbt(InstancePtr, Desc, MirrorDesc,
 								Target);
 		if (Status != XST_SUCCESS) {
@@ -617,9 +557,7 @@ static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 	MaxBlocks = Desc->MaxBlocks;
 	SigLength = Desc->SigLength;
 
-	/*
-	 * Read the last 4 blocks for Bad Block Table(BBT) signature
-	 */
+	/* Read the last 4 blocks for Bad Block Table(BBT) signature */
 	for(Block = 0U; Block < MaxBlocks; Block++) {
 		PageOff = (StartBlock - Block) *
 			InstancePtr->Geometry.PagesPerBlock;
@@ -628,9 +566,7 @@ static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 		if (Status != XST_SUCCESS) {
 			continue;
 		}
-		/*
-		 * Check the Bad Block Table(BBT) signature
-		 */
+		/* Check the Bad Block Table(BBT) signature */
 		for(Offset = 0U; Offset < SigLength; Offset++) {
 			if (Buf[Offset + SigOffset] !=
 				(u8)(Desc->Signature[Offset]))
@@ -639,9 +575,7 @@ static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 			}
 		}
 		if (Offset >= SigLength) {
-			/*
-			 * Bad Block Table(BBT) found
-			 */
+			/* Bad Block Table(BBT) found */
 			Desc->PageOffset[Target] = PageOff;
 			Desc->Version[Target] = Buf[VerOffset];
 			Desc->Valid = 1U;
@@ -650,9 +584,7 @@ static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 			goto Out;
 		}
 	}
-	/*
-	 * Bad Block Table(BBT) not found
-	 */
+	/* Bad Block Table(BBT) not found */
 	Status = XST_FAILURE;
 Out:
 	return Status;
@@ -691,9 +623,7 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 	u8 BlockType;
 	u32 BbtLen = InstancePtr->Geometry.NumBlocks >>
 						XNANDPSU_BBT_BLOCK_SHIFT;
-	/*
-	 * Find a valid block to write the Bad Block Table(BBT)
-	 */
+	/* Find a valid block to write the Bad Block Table(BBT) */
 	if ((!Desc->Valid) != 0U) {
 		for(Index = 0U; Index < Desc->MaxBlocks; Index++) {
 			Block  = (EndBlock - Index);
@@ -720,9 +650,7 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 			}
 		}
 
-		/*
-		 * Block not found for writing Bad Block Table(BBT)
-		 */
+		/* Block not found for writing Bad Block Table(BBT) */
 		if (Index >= Desc->MaxBlocks) {
 #ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Blocks unavailable for writing BBT\r\n",
@@ -735,19 +663,13 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 		Block = Desc->PageOffset[Target] /
 					InstancePtr->Geometry.PagesPerBlock;
 	}
-	/*
-	 * Convert the memory based BBT to flash based table
-	 */
+	/* Convert the memory based BBT to flash based table */
 	(void)memset(Buf, 0xff, BbtLen);
 
-	/*
-	 * Loop through the number of blocks
-	 */
+	/* Loop through the number of blocks */
 	for(BlockOffset = 0U; BlockOffset < BbtLen; BlockOffset++) {
 		Data = InstancePtr->Bbt[BlockOffset];
-		/*
-		 * Calculate the bit mask for 4 blocks at a time in loop
-		 */
+		/* Calculate the bit mask for 4 blocks at a time in loop */
 		for(BlockIndex = 0U; BlockIndex < XNANDPSU_BBT_ENTRY_NUM_BLOCKS;
 				BlockIndex++) {
 			BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
@@ -757,9 +679,7 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 			Data >>= XNANDPSU_BBT_BLOCK_SHIFT;
 		}
 	}
-	/*
-	 * Write the Bad Block Table(BBT) to flash
-	 */
+	/* Write the Bad Block Table(BBT) to flash */
 	Status = XNandPsu_EraseBlock(InstancePtr, 0U, Block);
 	if (Status != XST_SUCCESS) {
 		goto Out;
@@ -811,9 +731,7 @@ static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target)
 	s32 Status;
 	u8 Version;
 
-	/*
-	 * Update the version number
-	 */
+	/* Update the version number */
 	Version = InstancePtr->BbtDesc.Version[Target];
 	InstancePtr->BbtDesc.Version[Target] = (u8)(((u16)Version +
 							(u16)1) % (u16)256U);
@@ -821,9 +739,7 @@ static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target)
 	Version = InstancePtr->BbtMirrorDesc.Version[Target];
 	InstancePtr->BbtMirrorDesc.Version[Target] = (u8)(((u16)Version +
 							(u16)1) % (u16)256);
-	/*
-	 * Update the primary Bad Block Table(BBT) in flash
-	 */
+	/* Update the primary Bad Block Table(BBT) in flash */
 	Status = XNandPsu_WriteBbt(InstancePtr, &InstancePtr->BbtDesc,
 						&InstancePtr->BbtMirrorDesc,
 						Target);
@@ -831,9 +747,7 @@ static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target)
 		goto Out;
 	}
 
-	/*
-	 * Update the mirrored Bad Block Table(BBT) in flash
-	 */
+	/* Update the mirrored Bad Block Table(BBT) in flash */
 	Status = XNandPsu_WriteBbt(InstancePtr, &InstancePtr->BbtMirrorDesc,
 						&InstancePtr->BbtDesc,
 						Target);
@@ -870,9 +784,7 @@ static s32 XNandPsu_MarkBbt(XNandPsu* InstancePtr, XNandPsu_BbtDesc *Desc,
 	u32 UpdateBbt = 0U;
 	u32 Index;
 
-	/*
-	 * Mark the last four blocks as Reserved
-	 */
+	/* Mark the last four blocks as Reserved */
 	BlockIndex = ((Target + (u32)1) * InstancePtr->Geometry.NumTargetBlocks) -
 						Desc->MaxBlocks - (u32)1;
 
@@ -891,9 +803,7 @@ static s32 XNandPsu_MarkBbt(XNandPsu* InstancePtr, XNandPsu_BbtDesc *Desc,
 		BlockIndex++;
 	}
 
-	/*
-	 * Update the BBT to flash
-	 */
+	/* Update the BBT to flash */
 	if (UpdateBbt != 0U) {
 		Status = XNandPsu_UpdateBbt(InstancePtr, Target);
 		if (Status != XST_SUCCESS) {
@@ -980,18 +890,14 @@ s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block)
 	BlockShift = XNandPsu_BbtBlockShift(Block);
 	Data = InstancePtr->Bbt[BlockOffset];	/* Block information in BBT */
 
-	/*
-	 * Mark the block as bad in the RAM based Bad Block Table
-	 */
+	/* Mark the block as bad in the RAM based Bad Block Table */
 	OldVal = Data;
 	Data &= ~(XNANDPSU_BLOCK_TYPE_MASK << BlockShift);
 	Data |= (XNANDPSU_BLOCK_BAD << BlockShift);
 	NewVal = Data;
 	InstancePtr->Bbt[BlockOffset] = Data;
 
-	/*
-	 * Update the Bad Block Table(BBT) in flash
-	 */
+	/* Update the Bad Block Table(BBT) in flash */
 	if (OldVal != NewVal) {
 		Status = XNandPsu_UpdateBbt(InstancePtr, Target);
 		if (Status != XST_SUCCESS) {
diff --git a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.h b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.h
index 1d563fa7..d8e5d3e9 100644
--- a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.h
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.h
@@ -104,17 +104,13 @@ extern "C" {
 #include "xnandpsu.h"
 
 /************************** Constant Definitions *****************************/
-/*
- * Block definitions for RAM based Bad Block Table (BBT)
- */
+/* Block definitions for RAM based Bad Block Table (BBT) */
 #define XNANDPSU_BLOCK_GOOD			0x0U	/**< Block is good */
 #define XNANDPSU_BLOCK_BAD			0x1U	/**< Block is bad */
 #define XNANDPSU_BLOCK_RESERVED			0x2U	/**< Reserved block */
 #define XNANDPSU_BLOCK_FACTORY_BAD		0x3U	/**< Factory marked bad
 							  block */
-/*
- * Block definitions for FLASH based Bad Block Table (BBT)
- */
+/* Block definitions for FLASH based Bad Block Table (BBT) */
 #define XNANDPSU_FLASH_BLOCK_GOOD		0x3U	/**< Block is good */
 #define XNANDPSU_FLASH_BLOCK_BAD		0x2U	/**< Block is bad */
 #define XNANDPSU_FLASH_BLOCK_RESERVED		0x1U	/**< Reserved block */
diff --git a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.h b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.h
index bb143089..dd7de63d 100644
--- a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.h
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.h
@@ -60,12 +60,8 @@ extern "C" {
 #include "xil_types.h"
 
 /************************** Constant Definitions *****************************/
-/*
- * Standard ONFI 3.1 Commands
- */
-/*
- * ONFI 3.1 Mandatory Commands
- */
+/* Standard ONFI 3.1 Commands */
+/* ONFI 3.1 Mandatory Commands */
 #define ONFI_CMD_RD1			0x00U	/**< Read (1st cycle) */
 #define ONFI_CMD_RD2			0x30U	/**< Read (2nd cycle) */
 #define ONFI_CMD_CHNG_RD_COL1		0x05U	/**< Change Read Column
@@ -81,9 +77,7 @@ extern "C" {
 #define ONFI_CMD_RD_ID			0x90U	/**< Read ID */
 #define ONFI_CMD_RD_PRM_PG		0xECU	/**< Read Parameter Page */
 #define ONFI_CMD_RST			0xFFU	/**< Reset */
-/*
- * ONFI 3.1 Optional Commands
- */
+/* ONFI 3.1 Optional Commands */
 #define ONFI_CMD_MUL_RD1		0x00U	/**< Multiplane Read
 						  (1st cycle) */
 #define ONFI_CMD_MUL_RD2		0x32U	/**< Multiplane Read
@@ -140,9 +134,7 @@ extern "C" {
 #define ONFI_CMD_RST_LUN		0xFAU	/**< Reset LUN */
 #define ONFI_CMD_SYN_RST		0xFCU	/**< Synchronous Reset */
 
-/*
- * ONFI Status Register bit offsets
- */
+/* ONFI Status Register bit offsets */
 #define ONFI_STS_FAIL			0x01U	/**< FAIL */
 #define ONFI_STS_FAILC			0x02U	/**< FAILC */
 #define ONFI_STS_CSP			0x08U	/**< CSP */
@@ -151,9 +143,7 @@ extern "C" {
 #define ONFI_STS_RDY			0x40U	/**< RDY */
 #define ONFI_STS_WP			0x80U	/**< WP_n */
 
-/*
- * ONFI constants
- */
+/* ONFI constants */
 #define ONFI_CRC_LEN			254U	/**< ONFI CRC Buf Length */
 #define ONFI_PRM_PG_LEN			256U	/**< Parameter Page Length */
 #define ONFI_MND_PRM_PGS		3U	/**< Number of mandatory
@@ -209,13 +199,9 @@ enum OnfiCommandList {
 };
 
 /**************************** Type Definitions *******************************/
-/*
- * Parameter page structure of ONFI 3.1 specification.
- */
+/* Parameter page structure of ONFI 3.1 specification. */
 typedef struct {
-	/*
-	 * Revision information and features block
-	 */
+	/* Revision information and features block */
 	u8 Signature[4];		/**< Parameter page signature */
 	u16 Revision;			/**< Revision Number */
 	u16 Features;			/**< Features supported */
@@ -226,17 +212,13 @@ typedef struct {
 	u16 ExtParamPageLen;		/**< Extended Parameter Page Length */
 	u8 NumOfParamPages;		/**< Number of Parameter Pages */
 	u8 Reserved1[17];		/**< Reserved (15-31) */
-	/*
-	 * Manufacturer information block
-	 */
+	/* Manufacturer information block */
 	u8 DeviceManufacturer[12];	/**< Device manufacturer */
 	u8 DeviceModel[20];		/**< Device model */
 	u8 JedecManufacturerId;		/**< JEDEC Manufacturer ID */
 	u8 DateCode[2];			/**< Date code */
 	u8 Reserved2[13];		/**< Reserved (67-79) */
-	/*
-	 * Memory organization block
-	*/
+	/* Memory organization block */
 	u32 BytesPerPage;		/**< Number of data bytes per page */
 	u16 SpareBytesPerPage;		/**< Number of spare bytes per page */
 	u32 BytesPerPartialPage;	/**< Number of data bytes per
@@ -263,9 +245,7 @@ typedef struct {
 					  attributes */
 	u8 EzNandSupport;		/**< EZ NAND support */
 	u8 Reserved3[12];		/**< Reserved (116 - 127) */
-	/*
-	 * Electrical parameters block
-	*/
+	/* Electrical parameters block */
 	u8 IOPinCapacitance;		/**< I/O pin capacitance, maximum */
 	u16 SDRTimingMode;		/**< SDR Timing mode support */
 	u16 SDRPagecacheTimingMode;	/**< SDR Program cache timing mode */
@@ -290,17 +270,13 @@ typedef struct {
 	u8 NVDDR2Features;		/**< NVDDR2 Features */
 	u8 NVDDR2WarmupCycles;		/**< NVDDR2 Warmup Cycles */
 	u8 Reserved4[4];		/**< Reserved (160 - 163) */
-	/*
-	 * Vendor block
-	 */
+	/* Vendor block */
 	u16 VendorRevisionNum;		/**< Vendor specific revision number */
 	u8 VendorSpecific[88];		/**< Vendor specific */
 	u16 Crc;			/**< Integrity CRC */
 }__attribute__((packed))OnfiParamPage;
 
-/*
- * ONFI extended parameter page structure.
- */
+/* ONFI extended parameter page structure. */
 typedef struct {
 	u16 Crc;
 	u8 Sig[4];
@@ -313,9 +289,7 @@ typedef struct {
 	u8 SectionData[256];
 }__attribute__((packed))OnfiExtPrmPage;
 
-/*
- * Driver extended parameter page information.
- */
+/* Driver extended parameter page information. */
 typedef struct {
 	u8 NumEccBits;
 	u8 CodeWordSize;