diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdprx.c b/XilinxProcessorIPLib/drivers/dp/src/xdprx.c
index f3769afb..531ed0e6 100644
--- a/XilinxProcessorIPLib/drivers/dp/src/xdprx.c
+++ b/XilinxProcessorIPLib/drivers/dp/src/xdprx.c
@@ -94,7 +94,10 @@ u32 XDprx_InitializeRx(XDprx *InstancePtr)
 	XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG, 0x02);
 
 	/* Wait until all lane CPLLs have locked. */
-	XDprx_WaitPhyReady(InstancePtr, 0x30);
+	Status = XDprx_WaitPhyReady(InstancePtr, 0x30);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
 
 	/* Remove the reset from the PHY. */
 	XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG, 0x00);
@@ -291,7 +294,7 @@ void XDprx_WaitUs(XDprx *InstancePtr, u32 MicroSeconds)
 *******************************************************************************/
 static u32 XDprx_WaitPhyReady(XDprx *InstancePtr, u8 Mask)
 {
-	u32 Timeout = 100;
+	u16 Timeout = 20000;
 	u32 PhyStatus;
 
 	/* Wait until the PHY is ready. */
diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx.c b/XilinxProcessorIPLib/drivers/dp/src/xdptx.c
index 11b1df15..c48f968f 100644
--- a/XilinxProcessorIPLib/drivers/dp/src/xdptx.c
+++ b/XilinxProcessorIPLib/drivers/dp/src/xdptx.c
@@ -2623,7 +2623,7 @@ static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed)
 *******************************************************************************/
 static u32 XDptx_WaitPhyReady(XDptx *InstancePtr)
 {
-	u32 Timeout = 100;
+	u16 Timeout = 20000;
 	u32 PhyStatus;
 	u32 Mask;