From c8eeadf710a21580cd7635925910765eedec0c89 Mon Sep 17 00:00:00 2001 From: P L Sai Krishna Date: Thu, 23 Jul 2015 12:32:32 +0530 Subject: [PATCH] sdps: Modified the code according to MISRAC-2012. This patch modifies the source code according to MISRAC-2012. Signed-off-by: P L Sai Krishna Reviewed-by: Harini Katakam --- XilinxProcessorIPLib/drivers/sdps/src/xsdps.c | 314 ++--- XilinxProcessorIPLib/drivers/sdps/src/xsdps.h | 34 +- .../drivers/sdps/src/xsdps_hw.h | 1079 +++++++++-------- .../drivers/sdps/src/xsdps_options.c | 252 ++-- .../drivers/sdps/src/xsdps_sinit.c | 7 +- 5 files changed, 866 insertions(+), 820 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/sdps/src/xsdps.c b/XilinxProcessorIPLib/drivers/sdps/src/xsdps.c index acf304a2..e18a50f9 100644 --- a/XilinxProcessorIPLib/drivers/sdps/src/xsdps.c +++ b/XilinxProcessorIPLib/drivers/sdps/src/xsdps.c @@ -58,6 +58,7 @@ * Inhibit mask in Cmd Transfer API. * Added Support for SD Card v1.0 * 2.5 sg 07/09/15 Added SD 3.0 features +* kvn 07/15/15 Modified the code according to MISRAC-2012. * * ******************************************************************************/ @@ -81,41 +82,34 @@ #endif /************************** Constant Definitions *****************************/ -#define XSDPS_CMD8_VOL_PATTERN 0x1AA -#define XSDPS_RESPOCR_READY 0x80000000 -#define XSDPS_ACMD41_HCS 0x40000000 -#define XSDPS_ACMD41_3V3 0x00300000 -#define XSDPS_CMD1_HIGH_VOL 0x00FF8000 -#define XSDPS_CMD1_DUAL_VOL 0x00FF8010 +#define XSDPS_CMD8_VOL_PATTERN 0x1AAU +#define XSDPS_RESPOCR_READY 0x80000000U +#define XSDPS_ACMD41_HCS 0x40000000U +#define XSDPS_ACMD41_3V3 0x00300000U +#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U +#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U #define HIGH_SPEED_SUPPORT 0x2U #define WIDTH_4_BIT_SUPPORT 0x4U #define SD_CLK_25_MHZ 25000000U #define SD_CLK_26_MHZ 26000000U -#define EXT_CSD_DEVICE_TYPE_BYTE 196 -#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2 -#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED_DDR_1V8 0x4 -#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED_DDR_1V2 0x8 -#define EXT_CSD_DEVICE_TYPE_HS200_SDR_1V8 0x10 -#define EXT_CSD_DEVICE_TYPE_HS200_SDR_1V2 0x20 +#define EXT_CSD_DEVICE_TYPE_BYTE 196U +#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U +#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U +#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U +#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U +#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U /**************************** Type Definitions *******************************/ /***************** Macros (Inline Functions) Definitions *********************/ -#ifdef __ICCARM__ -#pragma data_alignment = 32 -static u8 ExtCsd[512]; -#pragma data_alignment = 4 -#else -static u8 ExtCsd[512] __attribute__ ((aligned(32))); -#endif /************************** Function Prototypes ******************************/ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd); -int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); +s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); -extern int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); -static int XSdPs_IdentifyCard(XSdPs *InstancePtr); -static int XSdPs_Switch_Voltage(XSdPs *InstancePtr); +extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); +static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr); +static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr); /*****************************************************************************/ /** @@ -149,11 +143,12 @@ static int XSdPs_Switch_Voltage(XSdPs *InstancePtr); * 32 bit ADMA2 is selected. Defualt Block size is 512 bytes. * ******************************************************************************/ -int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, +s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, u32 EffectiveAddr) { - u32 Status; + s32 Status; u8 PowerLevel; + u8 ReadReg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); @@ -167,22 +162,26 @@ int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, /* Disable bus power */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, - XSDPS_POWER_CTRL_OFFSET, 0); + XSDPS_POWER_CTRL_OFFSET, 0U); /* Delay to poweroff card */ - sleep(1); + (void)sleep(1U); /* "Software reset for all" is initiated */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET, XSDPS_SWRST_ALL_MASK); /* Proceed with initialization only after reset is complete */ - while (XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, - XSDPS_SW_RST_OFFSET) & XSDPS_SWRST_ALL_MASK); + ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, + XSDPS_SW_RST_OFFSET); + while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) { + ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, + XSDPS_SW_RST_OFFSET); + } /* Host Controller version is read. */ InstancePtr->HC_Version = - XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK; + (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK); /* * Read capabilities register and update it in Instance pointer. @@ -203,12 +202,14 @@ int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, goto RETURN_PATH ; } - if (InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) { + if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) { PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK; - } else if (InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) { + } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) { PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK; - } else if (InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) { + } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) { PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK; + } else { + PowerLevel = 0U; } /* Select voltage based on capability and enable bus power. */ @@ -231,9 +232,9 @@ int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, /* Disable all interrupt signals by default. */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0); + XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0); + XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U); /* * Transfer mode register - default value @@ -280,32 +281,32 @@ RETURN_PATH: * CMD9 is sent to read the card specific data. * ******************************************************************************/ -int XSdPs_SdCardInitialize(XSdPs *InstancePtr) +s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) { u32 PresentStateReg; - u32 Status; - u32 RespOCR = 0x0; + s32 Status; + u32 RespOCR; u32 CSD[4]; u32 Arg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - if(InstancePtr->Config.CardDetect) { + if(InstancePtr->Config.CardDetect != 0U) { /* * Check the present state register to make sure * card is inserted and detected by host controller */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); - if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0) { + if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } } /* CMD0 no response expected */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0, 0); + Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -316,7 +317,7 @@ int XSdPs_SdCardInitialize(XSdPs *InstancePtr) * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, - XSDPS_CMD8_VOL_PATTERN, 0); + XSDPS_CMD8_VOL_PATTERN, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -331,23 +332,23 @@ int XSdPs_SdCardInitialize(XSdPs *InstancePtr) InstancePtr->Card_Version = XSDPS_SD_VER_2_0; } - RespOCR = 0; + RespOCR = 0U; /* Send ACMD41 while card is still busy with power up */ - while ((RespOCR & XSDPS_RESPOCR_READY) == 0) { - Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0, 0); + while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) { + Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FF << 15); + Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { Arg |= XSDPS_OCR_S18; } /* 0x40300000 - Host High Capacity support & 3.3V window */ Status = XSdPs_CmdTransfer(InstancePtr, ACMD41, - Arg, 0); + Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -360,11 +361,12 @@ int XSdPs_SdCardInitialize(XSdPs *InstancePtr) } /* Update HCS support flag based on card capacity response */ - if (RespOCR & XSDPS_ACMD41_HCS) - InstancePtr->HCS = 1; + if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) { + InstancePtr->HCS = 1U; + } - if (RespOCR & XSDPS_OCR_S18) { - InstancePtr->Switch1v8 = 1; + if ((RespOCR & XSDPS_OCR_S18) != 0U) { + InstancePtr->Switch1v8 = 1U; Status = XSdPs_Switch_Voltage(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -374,7 +376,7 @@ int XSdPs_SdCardInitialize(XSdPs *InstancePtr) } /* CMD2 for Card ID */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -393,7 +395,7 @@ int XSdPs_SdCardInitialize(XSdPs *InstancePtr) XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_RESP3_OFFSET); do { - Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -405,10 +407,10 @@ int XSdPs_SdCardInitialize(XSdPs *InstancePtr) */ InstancePtr->RelCardAddr = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_RESP0_OFFSET) & 0xFFFF0000; - } while (InstancePtr->RelCardAddr == 0); + XSDPS_RESP0_OFFSET) & 0xFFFF0000U; + } while (InstancePtr->RelCardAddr == 0U); - Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -452,15 +454,22 @@ RETURN_PATH: * * ******************************************************************************/ -int XSdPs_CardInitialize(XSdPs *InstancePtr) { +s32 XSdPs_CardInitialize(XSdPs *InstancePtr) { u8 Tmp; u32 Cnt; u32 PresentStateReg; u32 CtrlReg; u32 CSD[4]; +#ifdef __ICCARM__ +#pragma data_alignment = 32 +static u8 ExtCsd[512]; +#pragma data_alignment = 4 +#else +static u8 ExtCsd[512] __attribute__ ((aligned(32))); +#endif u8 SCR[8] = { 0U }; u8 ReadBuff[64] = { 0U }; - s32 Status = XST_SUCCESS; + s32 Status; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -468,7 +477,7 @@ int XSdPs_CardInitialize(XSdPs *InstancePtr) { /* Default settings */ InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH; InstancePtr->CardType = XSDPS_CARD_SD; - InstancePtr->Switch1v8 = 0; + InstancePtr->Switch1v8 = 0U; InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ; if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && @@ -551,7 +560,7 @@ int XSdPs_CardInitialize(XSdPs *InstancePtr) { } } - if (InstancePtr->Switch1v8 && + if ((InstancePtr->Switch1v8 != 0U) && (InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) { /* Set UHS-I SDR104 mode */ Status = XSdPs_Uhs_ModeInit(InstancePtr, @@ -598,7 +607,8 @@ int XSdPs_CardInitialize(XSdPs *InstancePtr) { goto RETURN_PATH; } - if (ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & EXT_CSD_DEVICE_TYPE_HIGH_SPEED) { + if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -637,9 +647,9 @@ int XSdPs_CardInitialize(XSdPs *InstancePtr) { goto RETURN_PATH; } - if (ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - (EXT_CSD_DEVICE_TYPE_HS200_SDR_1V8 | - EXT_CSD_DEVICE_TYPE_HS200_SDR_1V2)) { + if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | + EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -678,10 +688,11 @@ RETURN_PATH: * @param InstancePtr is a pointer to the XSdPs instance. * ******************************************************************************/ -static int XSdPs_IdentifyCard(XSdPs *InstancePtr) +static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr) { - int Status = XST_SUCCESS; + s32 Status; u32 OperCondReg; + u8 ReadReg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -701,7 +712,7 @@ static int XSdPs_IdentifyCard(XSdPs *InstancePtr) #endif /* CMD0 no response expected */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -709,7 +720,7 @@ static int XSdPs_IdentifyCard(XSdPs *InstancePtr) /* Host High Capacity support & High voltage window */ Status = XSdPs_CmdTransfer(InstancePtr, CMD1, - XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0); + XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); if (Status != XST_SUCCESS) { InstancePtr->CardType = XSDPS_CARD_SD; } else { @@ -726,8 +737,12 @@ static int XSdPs_IdentifyCard(XSdPs *InstancePtr) XSDPS_SWRST_CMD_LINE_MASK); /* Proceed with initialization only after reset is complete */ - while (XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, - XSDPS_SW_RST_OFFSET) & XSDPS_SWRST_CMD_LINE_MASK); + ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, + XSDPS_SW_RST_OFFSET); + while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) { + ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, + XSDPS_SW_RST_OFFSET); + } Status = XST_SUCCESS; @@ -744,21 +759,26 @@ RETURN_PATH: * @param InstancePtr is a pointer to the XSdPs instance. * ******************************************************************************/ -static int XSdPs_Switch_Voltage(XSdPs *InstancePtr) +static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) { - u32 Status; + s32 Status; u16 CtrlReg; + u32 ReadReg; /* Send switch voltage command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; } /* Wait for CMD and DATA line to go low */ - while (XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PRES_STATE_OFFSET) - & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)); + ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | + XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) { + ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + } /* Stop the clock */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, @@ -768,7 +788,7 @@ static int XSdPs_Switch_Voltage(XSdPs *InstancePtr) CtrlReg); /* Wait minimum 5mSec */ - usleep(5000); + (void)usleep(5000U); /* Enabling 1.8V in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, @@ -785,10 +805,13 @@ static int XSdPs_Switch_Voltage(XSdPs *InstancePtr) } /* Wait for CMD and DATA line to go high */ - while ((XSdPs_ReadReg(InstancePtr->Config.BaseAddress, - XSDPS_PRES_STATE_OFFSET) - & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) - != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)); + ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) + != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) { + ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + } RETURN_PATH: return Status; @@ -811,12 +834,12 @@ RETURN_PATH: * is in progress or command or data inhibit is set * ******************************************************************************/ -int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) +s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) { u32 PresentStateReg; u32 CommandReg; u32 StatusReg; - u32 Status; + s32 Status; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -827,17 +850,17 @@ int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); - if (PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) { + if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) { Status = XST_FAILURE; goto RETURN_PATH; } /* Write block count register */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_BLK_CNT_OFFSET, BlkCnt); + XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt); XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, - XSDPS_TIMEOUT_CTRL_OFFSET, 0xE); + XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU); /* Write argument register */ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, @@ -855,35 +878,35 @@ int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) * This is necessary because 0x80000000 is used by this software to * distinguish between ACMD and CMD of same number */ - CommandReg = CommandReg & 0x3FFF; + CommandReg = CommandReg & 0x3FFFU; /* Check for data inhibit in case of command using DAT lines */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); - if ((PresentStateReg & XSDPS_PSR_INHIBIT_DAT_MASK) && - (CommandReg & XSDPS_DAT_PRESENT_SEL_MASK)) { + if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK | + XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) && + ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) { Status = XST_FAILURE; goto RETURN_PATH; } XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET, - CommandReg); + (u16)CommandReg); /* Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { - - /* Write to clear error bits */ + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { + /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } - } while((StatusReg & XSDPS_INTR_CC_MASK) == 0); + } while((StatusReg & XSDPS_INTR_CC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, @@ -937,7 +960,7 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) break; case CMD6: if (InstancePtr->CardType == XSDPS_CARD_SD) { - RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK; + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; } else { RetVal |= RESP_R1B; } @@ -952,7 +975,7 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) if (InstancePtr->CardType == XSDPS_CARD_SD) { RetVal |= RESP_R1; } else { - RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK; + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; } break; case CMD9: @@ -969,13 +992,13 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) case CMD18: case CMD19: case CMD21: - RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK; + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; break; case CMD23: case ACMD23: case CMD24: case CMD25: - RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK; + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; case ACMD41: RetVal |= RESP_R3; break; @@ -983,7 +1006,7 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) RetVal |= RESP_R1; break; case ACMD51: - RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK; + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; break; case CMD52: case CMD55: @@ -991,6 +1014,9 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) break; case CMD58: break; + default : + RetVal |= Cmd; + break; } return RetVal; @@ -1012,17 +1038,17 @@ u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) * is in progress or command or data inhibit is set * ******************************************************************************/ -int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) +s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) { - u32 Status; + s32 Status; u32 PresentStateReg; u32 StatusReg; - if(InstancePtr->Config.CardDetect) { + if(InstancePtr->Config.CardDetect != 0U) { /* Check status to ensure card is initialized */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); - if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0) { + if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) { Status = XST_FAILURE; goto RETURN_PATH; } @@ -1047,7 +1073,7 @@ int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK); - Xil_DCacheInvalidateRange(Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); + Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); /* Send block read command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); @@ -1060,7 +1086,7 @@ int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, @@ -1068,12 +1094,12 @@ int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) Status = XST_FAILURE; goto RETURN_PATH; } - } while((StatusReg & XSDPS_INTR_TC_MASK) == 0); + } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); - Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; @@ -1098,17 +1124,17 @@ RETURN_PATH: * is in progress or command or data inhibit is set * ******************************************************************************/ -int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) +s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) { - u32 Status; + s32 Status; u32 PresentStateReg; u32 StatusReg; - if(InstancePtr->Config.CardDetect) { + if(InstancePtr->Config.CardDetect != 0U) { /* Check status to ensure card is initialized */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); - if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0) { + if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) { Status = XST_FAILURE; goto RETURN_PATH; } @@ -1127,7 +1153,7 @@ int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); - Xil_DCacheFlushRange(Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); + Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, @@ -1149,7 +1175,7 @@ int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, @@ -1157,7 +1183,7 @@ int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) Status = XST_FAILURE; goto RETURN_PATH; } - } while((StatusReg & XSDPS_INTR_TC_MASK) == 0); + } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -1184,13 +1210,13 @@ int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) * @note None. * ******************************************************************************/ -int XSdPs_Select_Card (XSdPs *InstancePtr) +s32 XSdPs_Select_Card (XSdPs *InstancePtr) { - u32 Status = 0; + s32 Status = 0; /* Send CMD7 - Select card */ Status = XSdPs_CmdTransfer(InstancePtr, CMD7, - InstancePtr->RelCardAddr, 0); + InstancePtr->RelCardAddr, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -1218,9 +1244,9 @@ RETURN_PATH: ******************************************************************************/ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) { - u32 TotalDescLines = 0; - u32 DescNum = 0; - u32 BlkSize = 0; + u32 TotalDescLines = 0U; + u32 DescNum = 0U; + u32 BlkSize = 0U; /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */ BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, @@ -1229,17 +1255,18 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) { - TotalDescLines = 1; + TotalDescLines = 1U; }else { TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH); - if ((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) - TotalDescLines += 1; + if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) { + TotalDescLines += 1U; + } } - for (DescNum = 0; DescNum < (TotalDescLines-1); DescNum++) { + for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) { InstancePtr->Adma2_DescrTbl[DescNum].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); InstancePtr->Adma2_DescrTbl[DescNum].Attribute = @@ -1256,14 +1283,14 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length = - (BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH); + (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH)); XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0])); - Xil_DCacheFlushRange(&(InstancePtr->Adma2_DescrTbl[0]), - sizeof(XSdPs_Adma2Descriptor) * 32); + Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), + sizeof(XSdPs_Adma2Descriptor) * 32U); } @@ -1290,43 +1317,43 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) * CMD9 is sent to read the card specific data. * ******************************************************************************/ -int XSdPs_MmcCardInitialize(XSdPs *InstancePtr) +s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr) { u32 PresentStateReg; - u32 Status; - u32 RespOCR = 0x0; + s32 Status; + u32 RespOCR; u32 CSD[4]; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - if(InstancePtr->Config.CardDetect) { + if(InstancePtr->Config.CardDetect != 0U) { /* * Check the present state register to make sure * card is inserted and detected by host controller */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); - if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0) { + if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } } /* CMD0 no response expected */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - RespOCR = 0; + RespOCR = 0U; /* Send CMD1 while card is still busy with power up */ - while ((RespOCR & XSDPS_RESPOCR_READY) == 0) { + while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) { /* Host High Capacity support & High volage window */ Status = XSdPs_CmdTransfer(InstancePtr, CMD1, - XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0); + XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -1339,11 +1366,12 @@ int XSdPs_MmcCardInitialize(XSdPs *InstancePtr) } /* Update HCS support flag based on card capacity response */ - if (RespOCR & XSDPS_ACMD41_HCS) - InstancePtr->HCS = 1; + if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) { + InstancePtr->HCS = 1U; + } /* CMD2 for Card ID */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -1363,14 +1391,14 @@ int XSdPs_MmcCardInitialize(XSdPs *InstancePtr) XSDPS_RESP3_OFFSET); /* Set relative card address */ - InstancePtr->RelCardAddr = 0x12340000; - Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0); + InstancePtr->RelCardAddr = 0x12340000U; + Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; diff --git a/XilinxProcessorIPLib/drivers/sdps/src/xsdps.h b/XilinxProcessorIPLib/drivers/sdps/src/xsdps.h index fd3bc653..e56ecf94 100644 --- a/XilinxProcessorIPLib/drivers/sdps/src/xsdps.h +++ b/XilinxProcessorIPLib/drivers/sdps/src/xsdps.h @@ -117,6 +117,7 @@ * Inhibit mask in Cmd Transfer API. * Added Support for SD Card v1.0 * 2.5 sg 07/09/15 Added SD 3.0 features +* kvn 07/15/15 Modified the code according to MISRAC-2012. * * * @@ -130,6 +131,9 @@ extern "C" { #endif +#include "xil_printf.h" +#include "xil_cache.h" +#include "sleep.h" #include "xstatus.h" #include "xsdps_hw.h" #include @@ -190,22 +194,22 @@ typedef struct { /************************** Function Prototypes ******************************/ XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); -int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, +s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, u32 EffectiveAddr); -int XSdPs_SdCardInitialize(XSdPs *InstancePtr); -int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); -int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); -int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize); -int XSdPs_Select_Card (XSdPs *InstancePtr); -int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq); -int XSdPs_Change_BusWidth(XSdPs *InstancePtr); -int XSdPs_Change_BusSpeed(XSdPs *InstancePtr); -int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR); -int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff); -int XSdPs_Pullup(XSdPs *InstancePtr); -int XSdPs_MmcCardInitialize(XSdPs *InstancePtr); -int XSdPs_CardInitialize(XSdPs *InstancePtr); -int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); +s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); +s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize); +s32 XSdPs_Select_Card (XSdPs *InstancePtr); +s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq); +s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr); +s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr); +s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR); +s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Pullup(XSdPs *InstancePtr); +s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_CardInitialize(XSdPs *InstancePtr); +s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); #ifdef __cplusplus } diff --git a/XilinxProcessorIPLib/drivers/sdps/src/xsdps_hw.h b/XilinxProcessorIPLib/drivers/sdps/src/xsdps_hw.h index 4e76a428..a5399223 100644 --- a/XilinxProcessorIPLib/drivers/sdps/src/xsdps_hw.h +++ b/XilinxProcessorIPLib/drivers/sdps/src/xsdps_hw.h @@ -47,6 +47,7 @@ * ----- --- -------- ----------------------------------------------- * 1.00a hk/sg 10/17/13 Initial release * 2.5 sg 07/09/15 Added SD 3.0 features +* kvn 07/15/15 Modified the code according to MISRAC-2012. * * ******************************************************************************/ @@ -73,82 +74,82 @@ extern "C" { * @{ */ -#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00 /**< SDMA System Address +#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address Register */ #define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET /**< SDMA System Address Low Register */ -#define XSDPS_ARGMT2_LO_OFFSET 0x00 /**< Argument2 Low Register */ -#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02 /**< SDMA System Address +#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */ +#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address High Register */ -#define XSDPS_ARGMT2_HI_OFFSET 0x02 /**< Argument2 High Register */ +#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */ -#define XSDPS_BLK_SIZE_OFFSET 0x04 /**< Block Size Register */ -#define XSDPS_BLK_CNT_OFFSET 0x06 /**< Block Count Register */ -#define XSDPS_ARGMT_OFFSET 0x08 /**< Argument Register */ +#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */ +#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */ +#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */ #define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET /**< Argument1 Register */ -#define XSDPS_ARGMT1_HI_OFFSET 0x0A /**< Argument1 Register */ +#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */ -#define XSDPS_XFER_MODE_OFFSET 0x0C /**< Transfer Mode Register */ -#define XSDPS_CMD_OFFSET 0x0E /**< Command Register */ -#define XSDPS_RESP0_OFFSET 0x10 /**< Response0 Register */ -#define XSDPS_RESP1_OFFSET 0x14 /**< Response1 Register */ -#define XSDPS_RESP2_OFFSET 0x18 /**< Response2 Register */ -#define XSDPS_RESP3_OFFSET 0x1C /**< Response3 Register */ -#define XSDPS_BUF_DAT_PORT_OFFSET 0x20 /**< Buffer Data Port */ -#define XSDPS_PRES_STATE_OFFSET 0x24 /**< Present State */ -#define XSDPS_HOST_CTRL1_OFFSET 0x28 /**< Host Control 1 */ -#define XSDPS_POWER_CTRL_OFFSET 0x29 /**< Power Control */ -#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2A /**< Block Gap Control */ -#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2B /**< Wake Up Control */ -#define XSDPS_CLK_CTRL_OFFSET 0x2C /**< Clock Control */ -#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2E /**< Timeout Control */ -#define XSDPS_SW_RST_OFFSET 0x2F /**< Software Reset */ -#define XSDPS_NORM_INTR_STS_OFFSET 0x30 /**< Normal Interrupt +#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */ +#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */ +#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */ +#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */ +#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */ +#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */ +#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */ +#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */ +#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */ +#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */ +#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */ +#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */ +#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */ +#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */ +#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */ +#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt Status Register */ -#define XSDPS_ERR_INTR_STS_OFFSET 0x32 /**< Error Interrupt +#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt Status Register */ -#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34 /**< Normal Interrupt +#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt Status Enable Register */ -#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36 /**< Error Interrupt +#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt Status Enable Register */ -#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38 /**< Normal Interrupt +#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt Signal Enable Register */ -#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3A /**< Error Interrupt +#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt Signal Enable Register */ -#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3C /**< Auto CMD12 Error Status +#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status Register */ -#define XSDPS_HOST_CTRL2_OFFSET 0x3E /**< Host Control2 Register */ -#define XSDPS_CAPS_OFFSET 0x40 /**< Capabilities Register */ -#define XSDPS_CAPS_EXT_OFFSET 0x44 /**< Capabilities Extended */ -#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48 /**< Maximum Current +#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */ +#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */ +#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */ +#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current Capabilities Register */ -#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4C /**< Maximum Current +#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current Capabilities Ext Register */ -#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52 /**< Force Event for +#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for Error Interrupt Status */ -#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50 /**< Auto CM12 Error Interrupt +#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt Status Register */ -#define XSDPS_ADMA_ERR_STS_OFFSET 0x54 /**< ADMA Error Status +#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status Register */ -#define XSDPS_ADMA_SAR_OFFSET 0x58 /**< ADMA System Address +#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address Register */ -#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5C /**< ADMA System Address +#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address Extended Register */ -#define XSDPS_PRE_VAL_1_OFFSET 0x60 /**< Preset Value Register */ -#define XSDPS_PRE_VAL_2_OFFSET 0x64 /**< Preset Value Register */ -#define XSDPS_PRE_VAL_3_OFFSET 0x68 /**< Preset Value Register */ -#define XSDPS_PRE_VAL_4_OFFSET 0x6C /**< Preset Value Register */ -#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70 /**< Boot timeout control +#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */ +#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control register */ -#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0 /**< Shared Bus Control +#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control Register */ -#define XSDPS_SLOT_INTR_STS_OFFSET 0xFC /**< Slot Interrupt Status +#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status Register */ -#define XSDPS_HOST_CTRL_VER_OFFSET 0xFE /**< Host Controller Version +#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version Register */ /* @} */ @@ -161,38 +162,38 @@ extern "C" { * @{ */ -#define XSDPS_HC_LED_MASK 0x00000001 /**< LED Control */ -#define XSDPS_HC_WIDTH_MASK 0x00000002 /**< Bus width */ -#define XSDPS_HC_BUS_WIDTH_4 0x00000002 -#define XSDPS_HC_SPEED_MASK 0x00000004 /**< High Speed */ -#define XSDPS_HC_DMA_MASK 0x00000018 /**< DMA Mode Select */ -#define XSDPS_HC_DMA_SDMA_MASK 0x00000000 /**< SDMA Mode */ -#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008 /**< ADMA1 Mode */ -#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010 /**< ADMA2 Mode - 32 bit */ -#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018 /**< ADMA2 Mode - 64 bit */ -#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020 /**< Bus width - 8 bit */ -#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040 /**< Card Detect Tst Lvl */ -#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080 /**< Card Detect Sig Det */ +#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */ +#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */ +#define XSDPS_HC_BUS_WIDTH_4 0x00000002U +#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */ +#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */ +#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */ +#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */ +#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */ +#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */ +#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */ +#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */ +#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */ -#define XSDPS_PC_BUS_PWR_MASK 0x00000001 /**< Bus Power Control */ -#define XSDPS_PC_BUS_VSEL_MASK 0x0000000E /**< Bus Voltage Select */ -#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000E /**< Bus Voltage 3.3V */ -#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000C /**< Bus Voltage 3.0V */ -#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000A /**< Bus Voltage 1.8V */ -#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010 /**< HW reset for eMMC */ +#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */ +#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */ +#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */ +#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */ +#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */ +#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */ -#define XSDPS_BGC_STP_REQ_MASK 0x00000001 /**< Block Gap Stop Req */ -#define XSDPS_BGC_CNT_REQ_MASK 0x00000002 /**< Block Gap Cont Req */ -#define XSDPS_BGC_RWC_MASK 0x00000004 /**< Block Gap Rd Wait */ -#define XSDPS_BGC_INTR_MASK 0x00000008 /**< Block Gap Intr */ -#define XSDPS_BGC_SPI_MODE_MASK 0x00000010 /**< Block Gap SPI Mode */ -#define XSDPS_BGC_BOOT_EN_MASK 0x00000020 /**< Block Gap Boot Enb */ -#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040 /**< Block Gap Alt BootEn */ -#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080 /**< Block Gap Boot Ack */ +#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */ +#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */ +#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */ +#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */ +#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */ +#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */ +#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */ +#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */ -#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001 /**< Wakeup Card Intr */ -#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002 /**< Wakeup Card Insert */ -#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004 /**< Wakeup Card Removal */ +#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */ +#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */ +#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */ /* @} */ @@ -204,33 +205,33 @@ extern "C" { * @{ */ -#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001 -#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002 -#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004 -#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020 -#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0 -#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00 -#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000 -#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000 -#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000 -#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000 -#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800 -#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400 -#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200 -#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100 -#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000 -#define XSDPS_CC_MAX_DIV_CNT 256 -#define XSDPS_CC_EXT_MAX_DIV_CNT 2046 -#define XSDPS_CC_EXT_DIV_SHIFT 6 +#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U +#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U +#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U +#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U +#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U +#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U +#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U +#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U +#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U +#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U +#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U +#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U +#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U +#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U +#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U +#define XSDPS_CC_MAX_DIV_CNT 256U +#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U +#define XSDPS_CC_EXT_DIV_SHIFT 6U -#define XSDPS_TC_CNTR_VAL_MASK 0x0000000F +#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU -#define XSDPS_SWRST_ALL_MASK 0x00000001 -#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002 -#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004 +#define XSDPS_SWRST_ALL_MASK 0x00000001U +#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U +#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U -#define XSDPS_CC_MAX_NUM_OF_DIV 9 -#define XSDPS_CC_DIV_SHIFT 8 +#define XSDPS_CC_MAX_NUM_OF_DIV 9U +#define XSDPS_CC_DIV_SHIFT 8U /* @} */ @@ -257,42 +258,42 @@ extern "C" { * @{ */ -#define XSDPS_INTR_CC_MASK 0x00000001 /**< Command Complete */ -#define XSDPS_INTR_TC_MASK 0x00000002 /**< Transfer Complete */ -#define XSDPS_INTR_BGE_MASK 0x00000004 /**< Block Gap Event */ -#define XSDPS_INTR_DMA_MASK 0x00000008 /**< DMA Interrupt */ -#define XSDPS_INTR_BWR_MASK 0x00000010 /**< Buffer Write Ready */ -#define XSDPS_INTR_BRR_MASK 0x00000020 /**< Buffer Read Ready */ -#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040 /**< Card Insert */ -#define XSDPS_INTR_CARD_REM_MASK 0x00000080 /**< Card Remove */ -#define XSDPS_INTR_CARD_MASK 0x00000100 /**< Card Interrupt */ -#define XSDPS_INTR_INT_A_MASK 0x00000200 /**< INT A Interrupt */ -#define XSDPS_INTR_INT_B_MASK 0x00000400 /**< INT B Interrupt */ -#define XSDPS_INTR_INT_C_MASK 0x00000800 /**< INT C Interrupt */ -#define XSDPS_INTR_RE_TUNING_MASK 0x00001000 /**< Re-Tuning Interrupt */ -#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000 /**< Boot Ack Recv +#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */ +#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */ +#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */ +#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */ +#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */ +#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */ +#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */ +#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */ +#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */ +#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */ +#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */ +#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */ +#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */ +#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv Interrupt */ -#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000 /**< Boot Terminate +#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate Interrupt */ -#define XSDPS_INTR_ERR_MASK 0x00008000 /**< Error Interrupt */ -#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFF +#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */ +#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU -#define XSDPS_INTR_ERR_CT_MASK 0x00000001 /**< Command Timeout +#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout Error */ -#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002 /**< Command CRC Error */ -#define XSDPS_INTR_ERR_CEB_MASK 0x00000004 /**< Command End Bit +#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */ +#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit Error */ -#define XSDPS_INTR_ERR_CI_MASK 0x00000008 /**< Command Index Error */ -#define XSDPS_INTR_ERR_DT_MASK 0x00000010 /**< Data Timeout Error */ -#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020 /**< Data CRC Error */ -#define XSDPS_INTR_ERR_DEB_MASK 0x00000040 /**< Data End Bit Error */ -#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080 /**< Current Limit Error */ -#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100 /**< Auto CMD12 Error */ -#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200 /**< ADMA Error */ -#define XSDPS_INTR_ERR_TR_MASK 0x00001000 /**< Tuning Error */ -#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000 /**< Vendor Specific +#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */ +#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */ +#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */ +#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */ +#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */ +#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */ +#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */ +#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */ +#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific Error */ -#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FF /**< Mask for error bits */ +#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */ /* @} */ /** @name Block Size and Block Count Register @@ -303,11 +304,11 @@ extern "C" { * @{ */ -#define XSDPS_BLK_SIZE_MASK 0x00000FFF /**< Transfer Block Size */ -#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000 /**< Host SDMA Buffer Size */ -#define XSDPS_BLK_SIZE_1024 0x400 -#define XSDPS_BLK_SIZE_2048 0x800 -#define XSDPS_BLK_CNT_MASK 0x0000FFFF /**< Block Count for +#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */ +#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */ +#define XSDPS_BLK_SIZE_1024 0x400U +#define XSDPS_BLK_SIZE_2048 0x800U +#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for Current Transfer */ /* @} */ @@ -320,33 +321,33 @@ extern "C" { * @{ */ -#define XSDPS_TM_DMA_EN_MASK 0x00000001 /**< DMA Enable */ -#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002 /**< Block Count Enable */ -#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004 /**< Auto CMD12 Enable */ -#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010 /**< Data Transfer +#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */ +#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */ +#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */ +#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer Direction Select */ -#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020 /**< Multi/Single +#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single Block Select */ -#define XSDPS_CMD_RESP_SEL_MASK 0x00000003 /**< Response Type +#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type Select */ -#define XSDPS_CMD_RESP_NONE_MASK 0x00000000 /**< No Response */ -#define XSDPS_CMD_RESP_L136_MASK 0x00000001 /**< Response length 138 */ -#define XSDPS_CMD_RESP_L48_MASK 0x00000002 /**< Response length 48 */ -#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003 /**< Response length 48 & +#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */ +#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */ +#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */ +#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 & check busy after response */ -#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008 /**< Command CRC Check +#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check Enable */ -#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010 /**< Command Index Check +#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check Enable */ -#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020 /**< Data Present Select */ -#define XSDPS_CMD_TYPE_MASK 0x000000C0 /**< Command Type */ -#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000 /**< CMD Type - Normal */ -#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040 /**< CMD Type - Suspend */ -#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080 /**< CMD Type - Resume */ -#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0 /**< CMD Type - Abort */ -#define XSDPS_CMD_MASK 0x00003F00 /**< Command Index Mask - +#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */ +#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */ +#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */ +#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */ +#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */ +#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */ +#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask - Set to CMD0-63, AMCD0-63 */ @@ -359,15 +360,15 @@ extern "C" { * Read Only * @{ */ -#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001 /**< Auto CMD12 Not +#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not executed */ -#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002 /**< Auto CMD Timeout +#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout Error */ -#define XSDPS_AUTO_CMD_CRC_MASK 0x0004 /**< Auto CMD CRC Error */ -#define XSDPS_AUTO_CMD_EB_MASK 0x0008 /**< Auto CMD End Bit +#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit Error */ -#define XSDPS_AUTO_CMD_IND_MASK 0x0010 /**< Auto CMD Index Error */ -#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080 /**< Command not issued by +#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by Auto CMD12 Error */ /* @} */ @@ -377,25 +378,25 @@ extern "C" { * Read Write * @{ */ -#define XSDPS_HC2_UHS_MODE_MASK 0x0007 /**< UHS Mode select bits */ -#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000 /**< SDR12 UHS Mode */ -#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001 /**< SDR25 UHS Mode */ -#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002 /**< SDR50 UHS Mode */ -#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003 /**< SDR104 UHS Mode */ -#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004 /**< DDR50 UHS Mode */ -#define XSDPS_HC2_1V8_EN_MASK 0x0008 /**< 1.8V Signal Enable */ -#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030 /**< Driver Strength +#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */ +#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */ +#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */ +#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength Selection */ -#define XSDPS_HC2_DRV_STR_B_MASK 0x0000 /**< Driver Strength B */ -#define XSDPS_HC2_DRV_STR_A_MASK 0x0010 /**< Driver Strength A */ -#define XSDPS_HC2_DRV_STR_C_MASK 0x0020 /**< Driver Strength C */ -#define XSDPS_HC2_DRV_STR_D_MASK 0x0030 /**< Driver Strength D */ -#define XSDPS_HC2_EXEC_TNG_MASK 0x0040 /**< Execute Tuning */ -#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080 /**< Sampling Clock +#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */ +#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */ +#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */ +#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */ +#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */ +#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock Selection */ -#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000 /**< Asynchronous Interrupt +#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt Enable */ -#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000 /**< Preset Value Enable */ +#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */ /* @} */ @@ -407,63 +408,63 @@ extern "C" { * Read Only * @{ */ -#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003F /**< Timeout clock freq +#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq select */ -#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080 /**< Timeout clock unit - +#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit - MHz/KHz */ -#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000 /**< Max block length */ -#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000 /**< Max block 512 bytes */ -#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000 /**< Max block 1024 bytes */ -#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000 /**< Max block 2048 bytes */ -#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000 /**< Max block 4096 bytes */ +#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */ +#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */ +#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */ +#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */ +#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */ -#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000 /**< Extended media bus */ -#define XSDPS_CAP_ADMA2_MASK 0x00080000 /**< ADMA2 support */ -#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000 /**< High speed support */ -#define XSDPS_CAP_SDMA_MASK 0x00400000 /**< SDMA support */ -#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000 /**< Suspend/Resume +#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */ +#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */ +#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */ +#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */ +#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume support */ -#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000 /**< 3.3V support */ -#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000 /**< 3.0V support */ -#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000 /**< 1.8V support */ +#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */ +#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */ +#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */ -#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000 /**< 64 bit system bus +#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus support */ /* Spec 2.0 */ -#define XSDPS_CAP_INTR_MODE_MASK 0x08000000 /**< Interrupt mode +#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode support */ -#define XSDPS_CAP_SPI_MODE_MASK 0x20000000 /**< SPI mode */ -#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000 /**< SPI block mode */ +#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */ +#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */ /* Spec 3.0 */ -#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000 /**< Async Interrupt +#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt support */ -#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000 /**< Slot Type */ -#define XSDPS_CAPS_REM_CARD 0x00000000 /**< Removable Slot */ -#define XSDPS_CAPS_EMB_SLOT 0x40000000 /**< Embedded Slot */ -#define XSDPS_CAPS_SHR_BUS 0x80000000 /**< Shared Bus Slot */ +#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */ +#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */ +#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */ +#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */ -#define XSDPS_ECAPS_SDR50_MASK 0x00000001 /**< SDR50 Mode support */ -#define XSDPS_ECAPS_SDR104_MASK 0x00000002 /**< SDR104 Mode support */ -#define XSDPS_ECAPS_DDR50_MASK 0x00000004 /**< DDR50 Mode support */ -#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010 /**< DriverType A support */ -#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020 /**< DriverType C support */ -#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040 /**< DriverType D support */ -#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00 /**< Timer Count for +#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */ +#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */ +#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */ +#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */ +#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */ +#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */ +#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for Re-tuning */ -#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000 /**< SDR50 Mode needs +#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs tuning */ -#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000 /**< Re-tuning modes +#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes support */ -#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000 /**< Re-tuning mode 1 */ -#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000 /**< Re-tuning mode 2 */ -#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000 /**< Re-tuning mode 3 */ -#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000 /**< Clock Multiplier value +#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */ +#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */ +#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */ +#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value for Programmable clock mode */ -#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000 /**< SPI mode */ -#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000 /**< SPI block mode */ +#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */ +#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */ /* @} */ @@ -474,22 +475,22 @@ extern "C" { * @{ */ -#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001 /**< Command inhibit - CMD */ -#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002 /**< Command Inhibit - DAT */ -#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004 /**< DAT line active */ -#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008 /**< Re-tuning request */ -#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100 /**< Write transfer active */ -#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200 /**< Read transfer active */ -#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400 /**< Buffer write enable */ -#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800 /**< Buffer read enable */ -#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000 /**< Card inserted */ -#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000 /**< Card state stable */ -#define XSDPS_PSR_CARD_DPL_MASK 0x00040000 /**< Card detect pin level */ -#define XSDPS_PSR_WPS_PL_MASK 0x00080000 /**< Write protect switch +#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */ +#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */ +#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */ +#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */ +#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */ +#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */ +#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */ +#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */ +#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */ +#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */ +#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */ +#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch pin level */ -#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000 /**< Data 3:0 signal lvl */ -#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000 /**< Cmd Line signal lvl */ -#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000 /**< Data 7:4 signal lvl */ +#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */ +#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */ +#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */ /* @} */ @@ -500,11 +501,11 @@ extern "C" { * Read Only * @{ */ -#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00 /**< Maximum Current +#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current Capability at 1.8V */ -#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0 /**< Maximum Current +#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current Capability at 3.0V */ -#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000F /**< Maximum Current +#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current Capability at 3.3V */ /* @} */ @@ -516,15 +517,15 @@ extern "C" { * Write Only * @{ */ -#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001 /**< Auto CMD12 Not +#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not executed */ -#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002 /**< Auto CMD Timeout +#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout Error */ -#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004 /**< Auto CMD CRC Error */ -#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008 /**< Auto CMD End Bit +#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit Error */ -#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010 /**< Auto CMD Index Error */ -#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080 /**< Command not issued by +#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by Auto CMD12 Error */ /* @} */ @@ -537,20 +538,20 @@ extern "C" { * Write Only * @{ */ -#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001 /**< Command Timeout +#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout Error */ -#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002 /**< Command CRC Error */ -#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004 /**< Command End Bit +#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */ +#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit Error */ -#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008 /**< Command Index Error */ -#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010 /**< Data Timeout Error */ -#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020 /**< Data CRC Error */ -#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040 /**< Data End Bit Error */ -#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080 /**< Current Limit Error */ -#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100 /**< Auto CMD Error */ -#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200 /**< ADMA Error */ -#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000 /**< Target Reponse */ -#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000 /**< Vendor Specific +#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */ +#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */ +#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */ +#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */ +#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */ +#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */ +#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */ +#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */ +#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific Error */ /* @} */ @@ -562,14 +563,14 @@ extern "C" { * Read Only * @{ */ -#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04 /**< ADMA Length Mismatch +#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch Error */ -#define XSDPS_ADMA_ERR_STATE_MASK 0x03 /**< ADMA Error State */ -#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00 /**< ADMA Error State +#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */ +#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State STOP */ -#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01 /**< ADMA Error State +#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State FDS */ -#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03 /**< ADMA Error State +#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State TFR */ /* @} */ @@ -580,11 +581,11 @@ extern "C" { * Read Only * @{ */ -#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FF /**< SDCLK Frequency +#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency Select Value */ -#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400 /**< Clock Generator +#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator Mode Select */ -#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000 /**< Driver Strength +#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength Select Value */ /* @} */ @@ -596,7 +597,7 @@ extern "C" { * Read Only * @{ */ -#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007 /**< Interrupt Signal +#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal mask */ /* @} */ @@ -608,15 +609,15 @@ extern "C" { * Read Only * @{ */ -#define XSDPS_HC_VENDOR_VER 0xFF00 /**< Vendor +#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor Specification version mask */ -#define XSDPS_HC_SPEC_VER_MASK 0x00FF /**< Host +#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host Specification version mask */ -#define XSDPS_HC_SPEC_V3 0x0002 -#define XSDPS_HC_SPEC_V2 0x0001 -#define XSDPS_HC_SPEC_V1 0x0000 +#define XSDPS_HC_SPEC_V3 0x0002U +#define XSDPS_HC_SPEC_V2 0x0001U +#define XSDPS_HC_SPEC_V1 0x0000U /** @name Block size mask for 512 bytes * @@ -624,7 +625,7 @@ extern "C" { * @{ */ -#define XSDPS_BLK_SIZE_512_MASK 0x200 +#define XSDPS_BLK_SIZE_512_MASK 0x200U /* @} */ @@ -634,265 +635,265 @@ extern "C" { * @{ */ -#define XSDPS_APP_CMD_PREFIX 0x8000 -#define CMD0 0x0000 -#define CMD1 0x0100 -#define CMD2 0x0200 -#define CMD3 0x0300 -#define CMD4 0x0400 -#define CMD5 0x0500 -#define CMD6 0x0600 -#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600) -#define CMD7 0x0700 -#define CMD8 0x0800 -#define CMD9 0x0900 -#define CMD10 0x0A00 -#define CMD11 0x0B00 -#define CMD12 0x0C00 -#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00) -#define CMD16 0x1000 -#define CMD17 0x1100 -#define CMD18 0x1200 -#define CMD19 0x1300 -#define CMD21 0x1500 -#define CMD23 0x1700 -#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700) -#define CMD24 0x1800 -#define CMD25 0x1900 -#define CMD41 0x2900 -#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900) -#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00) -#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300) -#define CMD52 0x3400 -#define CMD55 0x3700 -#define CMD58 0x3A00 +#define XSDPS_APP_CMD_PREFIX 0x8000U +#define CMD0 0x0000U +#define CMD1 0x0100U +#define CMD2 0x0200U +#define CMD3 0x0300U +#define CMD4 0x0400U +#define CMD5 0x0500U +#define CMD6 0x0600U +#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U) +#define CMD7 0x0700U +#define CMD8 0x0800U +#define CMD9 0x0900U +#define CMD10 0x0A00U +#define CMD11 0x0B00U +#define CMD12 0x0C00U +#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U) +#define CMD16 0x1000U +#define CMD17 0x1100U +#define CMD18 0x1200U +#define CMD19 0x1300U +#define CMD21 0x1500U +#define CMD23 0x1700U +#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U) +#define CMD24 0x1800U +#define CMD25 0x1900U +#define CMD41 0x2900U +#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U) +#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U) +#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U) +#define CMD52 0x3400U +#define CMD55 0x3700U +#define CMD58 0x3A00U -#define RESP_NONE XSDPS_CMD_RESP_NONE_MASK -#define RESP_R1 XSDPS_CMD_RESP_L48_MASK | XSDPS_CMD_CRC_CHK_EN_MASK | \ - XSDPS_CMD_INX_CHK_EN_MASK +#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK +#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \ + (u32)XSDPS_CMD_INX_CHK_EN_MASK -#define RESP_R1B XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ - XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK +#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK -#define RESP_R2 XSDPS_CMD_RESP_L136_MASK | XSDPS_CMD_CRC_CHK_EN_MASK -#define RESP_R3 XSDPS_CMD_RESP_L48_MASK +#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK +#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK -#define RESP_R6 XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ - XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK +#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK /* @} */ /* Card Interface Conditions Definitions */ -#define XSDPS_CIC_CHK_PATTERN 0xAA -#define XSDPS_CIC_VOLT_MASK (0xF<<8) -#define XSDPS_CIC_VOLT_2V7_3V6 (1<<8) -#define XSDPS_CIC_VOLT_LOW (1<<9) +#define XSDPS_CIC_CHK_PATTERN 0xAAU +#define XSDPS_CIC_VOLT_MASK (0xFU<<8) +#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8) +#define XSDPS_CIC_VOLT_LOW (1U<<9) /* Operation Conditions Register Definitions */ -#define XSDPS_OCR_PWRUP_STS (1<<31) -#define XSDPS_OCR_CC_STS (1<<30) -#define XSDPS_OCR_S18 (1<<24) -#define XSDPS_OCR_3V5_3V6 (1<<23) -#define XSDPS_OCR_3V4_3V5 (1<<22) -#define XSDPS_OCR_3V3_3V4 (1<<21) -#define XSDPS_OCR_3V2_3V3 (1<<20) -#define XSDPS_OCR_3V1_3V2 (1<<19) -#define XSDPS_OCR_3V0_3V1 (1<<18) -#define XSDPS_OCR_2V9_3V0 (1<<17) -#define XSDPS_OCR_2V8_2V9 (1<<16) -#define XSDPS_OCR_2V7_2V8 (1<<15) -#define XSDPS_OCR_1V7_1V95 (1<<7) -#define XSDPS_OCR_HIGH_VOL 0x00FF8000 -#define XSDPS_OCR_LOW_VOL 0x00000080 +#define XSDPS_OCR_PWRUP_STS (1U<<31) +#define XSDPS_OCR_CC_STS (1U<<30) +#define XSDPS_OCR_S18 (1U<<24) +#define XSDPS_OCR_3V5_3V6 (1U<<23) +#define XSDPS_OCR_3V4_3V5 (1U<<22) +#define XSDPS_OCR_3V3_3V4 (1U<<21) +#define XSDPS_OCR_3V2_3V3 (1U<<20) +#define XSDPS_OCR_3V1_3V2 (1U<<19) +#define XSDPS_OCR_3V0_3V1 (1U<<18) +#define XSDPS_OCR_2V9_3V0 (1U<<17) +#define XSDPS_OCR_2V8_2V9 (1U<<16) +#define XSDPS_OCR_2V7_2V8 (1U<<15) +#define XSDPS_OCR_1V7_1V95 (1U<<7) +#define XSDPS_OCR_HIGH_VOL 0x00FF8000U +#define XSDPS_OCR_LOW_VOL 0x00000080U /* SD Card Configuration Register Definitions */ -#define XSDPS_SCR_REG_LEN 8 -#define XSDPS_SCR_STRUCT_MASK (0xF<<28) -#define XSDPS_SCR_SPEC_MASK (0xF<<24) -#define XSDPS_SCR_SPEC_1V0 0 -#define XSDPS_SCR_SPEC_1V1 (1<<24) -#define XSDPS_SCR_SPEC_2V0_3V0 (2<<24) -#define XSDPS_SCR_MEM_VAL_AF_ERASE (1<<23) -#define XSDPS_SCR_SEC_SUPP_MASK (7<<20) -#define XSDPS_SCR_SEC_SUPP_NONE 0 -#define XSDPS_SCR_SEC_SUPP_1V1 (2<<20) -#define XSDPS_SCR_SEC_SUPP_2V0 (3<<20) -#define XSDPS_SCR_SEC_SUPP_3V0 (4<<20) -#define XSDPS_SCR_BUS_WIDTH_MASK (0xF<<16) -#define XSDPS_SCR_BUS_WIDTH_1 (1<<16) -#define XSDPS_SCR_BUS_WIDTH_4 (4<<16) -#define XSDPS_SCR_SPEC3_MASK (1<<12) -#define XSDPS_SCR_SPEC3_2V0 0 -#define XSDPS_SCR_SPEC3_3V0 (1<<12) -#define XSDPS_SCR_CMD_SUPP_MASK 0x3 -#define XSDPS_SCR_CMD23_SUPP (1<<1) -#define XSDPS_SCR_CMD20_SUPP (1<<0) +#define XSDPS_SCR_REG_LEN 8U +#define XSDPS_SCR_STRUCT_MASK (0xFU<<28) +#define XSDPS_SCR_SPEC_MASK (0xFU<<24) +#define XSDPS_SCR_SPEC_1V0 0U +#define XSDPS_SCR_SPEC_1V1 (1U<<24) +#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24) +#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23) +#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20) +#define XSDPS_SCR_SEC_SUPP_NONE 0U +#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20) +#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20) +#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20) +#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16) +#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16) +#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16) +#define XSDPS_SCR_SPEC3_MASK (1U<<12) +#define XSDPS_SCR_SPEC3_2V0 0U +#define XSDPS_SCR_SPEC3_3V0 (1U<<12) +#define XSDPS_SCR_CMD_SUPP_MASK 0x3U +#define XSDPS_SCR_CMD23_SUPP (1U<<1) +#define XSDPS_SCR_CMD20_SUPP (1U<<0) /* Card Status Register Definitions */ -#define XSDPS_CD_STS_OUT_OF_RANGE (1<<31) -#define XSDPS_CD_STS_ADDR_ERR (1<<30) -#define XSDPS_CD_STS_BLK_LEN_ERR (1<<29) -#define XSDPS_CD_STS_ER_SEQ_ERR (1<<28) -#define XSDPS_CD_STS_ER_PRM_ERR (1<<27) -#define XSDPS_CD_STS_WP_VIO (1<<26) -#define XSDPS_CD_STS_IS_LOCKED (1<<25) -#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1<<24) -#define XSDPS_CD_STS_CMD_CRC_ERR (1<<23) -#define XSDPS_CD_STS_ILGL_CMD (1<<22) -#define XSDPS_CD_STS_CARD_ECC_FAIL (1<<21) -#define XSDPS_CD_STS_CC_ERR (1<<20) -#define XSDPS_CD_STS_ERR (1<<19) -#define XSDPS_CD_STS_CSD_OVRWR (1<<16) -#define XSDPS_CD_STS_WP_ER_SKIP (1<<15) -#define XSDPS_CD_STS_CARD_ECC_DIS (1<<14) -#define XSDPS_CD_STS_ER_RST (1<<13) -#define XSDPS_CD_STS_CUR_STATE (0xF<<9) -#define XSDPS_CD_STS_RDY_FOR_DATA (1<<8) -#define XSDPS_CD_STS_APP_CMD (1<<5) -#define XSDPS_CD_STS_AKE_SEQ_ERR (1<<2) +#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31) +#define XSDPS_CD_STS_ADDR_ERR (1U<<30) +#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29) +#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28) +#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27) +#define XSDPS_CD_STS_WP_VIO (1U<<26) +#define XSDPS_CD_STS_IS_LOCKED (1U<<25) +#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24) +#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23) +#define XSDPS_CD_STS_ILGL_CMD (1U<<22) +#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21) +#define XSDPS_CD_STS_CC_ERR (1U<<20) +#define XSDPS_CD_STS_ERR (1U<<19) +#define XSDPS_CD_STS_CSD_OVRWR (1U<<16) +#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15) +#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14) +#define XSDPS_CD_STS_ER_RST (1U<<13) +#define XSDPS_CD_STS_CUR_STATE (0xFU<<9) +#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8) +#define XSDPS_CD_STS_APP_CMD (1U<<5) +#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2) /* Switch Function Definitions CMD6 */ -#define XSDPS_SWITCH_SD_RESP_LEN 64 +#define XSDPS_SWITCH_SD_RESP_LEN 64U -#define XSDPS_SWITCH_FUNC_SWITCH (1<<31) -#define XSDPS_SWITCH_FUNC_CHECK 0 +#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31) +#define XSDPS_SWITCH_FUNC_CHECK 0U -#define XSDPS_MODE_FUNC_GRP1 1 -#define XSDPS_MODE_FUNC_GRP2 2 -#define XSDPS_MODE_FUNC_GRP3 3 -#define XSDPS_MODE_FUNC_GRP4 4 -#define XSDPS_MODE_FUNC_GRP5 5 -#define XSDPS_MODE_FUNC_GRP6 6 +#define XSDPS_MODE_FUNC_GRP1 1U +#define XSDPS_MODE_FUNC_GRP2 2U +#define XSDPS_MODE_FUNC_GRP3 3U +#define XSDPS_MODE_FUNC_GRP4 4U +#define XSDPS_MODE_FUNC_GRP5 5U +#define XSDPS_MODE_FUNC_GRP6 6U -#define XSDPS_FUNC_GRP_DEF_VAL 0xF -#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFF +#define XSDPS_FUNC_GRP_DEF_VAL 0xFU +#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU -#define XSDPS_ACC_MODE_DEF_SDR12 0 -#define XSDPS_ACC_MODE_HS_SDR25 1 -#define XSDPS_ACC_MODE_SDR50 2 -#define XSDPS_ACC_MODE_SDR104 3 -#define XSDPS_ACC_MODE_DDR50 4 +#define XSDPS_ACC_MODE_DEF_SDR12 0U +#define XSDPS_ACC_MODE_HS_SDR25 1U +#define XSDPS_ACC_MODE_SDR50 2U +#define XSDPS_ACC_MODE_SDR104 3U +#define XSDPS_ACC_MODE_DDR50 4U -#define XSDPS_CMD_SYS_ARG_SHIFT 4 -#define XSDPS_CMD_SYS_DEF 0 -#define XSDPS_CMD_SYS_eC 1 -#define XSDPS_CMD_SYS_OTP 3 -#define XSDPS_CMD_SYS_ASSD 4 -#define XSDPS_CMD_SYS_VEND 5 +#define XSDPS_CMD_SYS_ARG_SHIFT 4U +#define XSDPS_CMD_SYS_DEF 0U +#define XSDPS_CMD_SYS_eC 1U +#define XSDPS_CMD_SYS_OTP 3U +#define XSDPS_CMD_SYS_ASSD 4U +#define XSDPS_CMD_SYS_VEND 5U -#define XSDPS_DRV_TYPE_ARG_SHIFT 8 -#define XSDPS_DRV_TYPE_B 0 -#define XSDPS_DRV_TYPE_A 1 -#define XSDPS_DRV_TYPE_C 2 -#define XSDPS_DRV_TYPE_D 3 +#define XSDPS_DRV_TYPE_ARG_SHIFT 8U +#define XSDPS_DRV_TYPE_B 0U +#define XSDPS_DRV_TYPE_A 1U +#define XSDPS_DRV_TYPE_C 2U +#define XSDPS_DRV_TYPE_D 3U -#define XSDPS_CUR_LIM_ARG_SHIFT 12 -#define XSDPS_CUR_LIM_200 0 -#define XSDPS_CUR_LIM_400 1 -#define XSDPS_CUR_LIM_600 2 -#define XSDPS_CUR_LIM_800 3 +#define XSDPS_CUR_LIM_ARG_SHIFT 12U +#define XSDPS_CUR_LIM_200 0U +#define XSDPS_CUR_LIM_400 1U +#define XSDPS_CUR_LIM_600 2U +#define XSDPS_CUR_LIM_800 3U /* EXT_CSD field definitions */ -#define XSDPS_EXT_CSD_SIZE 512 +#define XSDPS_EXT_CSD_SIZE 512U -#define EXT_CSD_WR_REL_PARAM_EN (1<<2) +#define EXT_CSD_WR_REL_PARAM_EN (1U<<2) -#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) -#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) -#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04) -#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) +#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U) +#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U) -#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) -#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) -#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3) -#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4) +#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U) +#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U) +#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U) +#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U) -#define EXT_CSD_PART_SUPPORT_PART_EN (0x1) +#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U) -#define EXT_CSD_CMD_SET_NORMAL (1<<0) -#define EXT_CSD_CMD_SET_SECURE (1<<1) -#define EXT_CSD_CMD_SET_CPSECURE (1<<2) +#define EXT_CSD_CMD_SET_NORMAL (1U<<0) +#define EXT_CSD_CMD_SET_SECURE (1U<<1) +#define EXT_CSD_CMD_SET_CPSECURE (1U<<2) -#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ -#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ -#define EXT_CSD_CARD_TYPE_MASK 0x3F /* Mask out reserved bits */ -#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */ /* DDR mode @1.8V or 3V I/O */ -#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */ /* DDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | EXT_CSD_CARD_TYPE_DDR_1_2V) -#define EXT_CSD_CARD_TYPE_SDR_1_8V (1<<4) /* Card can run at 200MHz */ -#define EXT_CSD_CARD_TYPE_SDR_1_2V (1<<5) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */ /* SDR mode @1.2V I/O */ -#define EXT_CSD_BUS_WIDTH_BYTE 183 -#define EXT_CSD_BUS_WIDTH_1_BIT 0 /* Card is in 1 bit mode */ -#define EXT_CSD_BUS_WIDTH_4_BIT 1 /* Card is in 4 bit mode */ -#define EXT_CSD_BUS_WIDTH_8_BIT 2 /* Card is in 8 bit mode */ -#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5 /* Card is in 4 bit DDR mode */ -#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6 /* Card is in 8 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_BYTE 183U +#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */ +#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */ -#define EXT_CSD_HS_TIMING_BYTE 185 -#define EXT_CSD_HS_TIMING_DEF 0 -#define EXT_CSD_HS_TIMING_HIGH 1 /* Card is in high speed mode */ -#define EXT_CSD_HS_TIMING_HS200 2 /* Card is in HS200 mode */ +#define EXT_CSD_HS_TIMING_BYTE 185U +#define EXT_CSD_HS_TIMING_DEF 0U +#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */ +#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */ -#define XSDPS_EXT_CSD_CMD_SET 0 -#define XSDPS_EXT_CSD_SET_BITS 1 -#define XSDPS_EXT_CSD_CLR_BITS 2 -#define XSDPS_EXT_CSD_WRITE_BYTE 3 +#define XSDPS_EXT_CSD_CMD_SET 0U +#define XSDPS_EXT_CSD_SET_BITS 1U +#define XSDPS_EXT_CSD_CLR_BITS 2U +#define XSDPS_EXT_CSD_WRITE_BYTE 3U -#define XSDPS_MMC_DEF_SPEED_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | (EXT_CSD_HS_TIMING_BYTE << 16) \ - | (EXT_CSD_HS_TIMING_DEF << 8)) +#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) -#define XSDPS_MMC_HIGH_SPEED_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | (EXT_CSD_HS_TIMING_BYTE << 16) \ - | (EXT_CSD_HS_TIMING_HIGH << 8)) +#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) -#define XSDPS_MMC_HS200_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | (EXT_CSD_HS_TIMING_BYTE << 16) \ - | (EXT_CSD_HS_TIMING_HS200 << 8)) +#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) -#define XSDPS_MMC_1_BIT_BUS_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | (EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | (EXT_CSD_BUS_WITH_1_BIT << 8)) +#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8)) -#define XSDPS_MMC_4_BIT_BUS_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | (EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | (EXT_CSD_BUS_WIDTH_4_BIT << 8)) +#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) -#define XSDPS_MMC_8_BIT_BUS_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | (EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | (EXT_CSD_BUS_WIDTH_8_BIT << 8)) +#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) -#define XSDPS_MMC_DDR_4_BIT_BUS_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | (EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | (EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) +#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) -#define XSDPS_MMC_DDR_8_BIT_BUS_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24) \ - | (EXT_CSD_BUS_WIDTH_BYTE << 16) \ - | (EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) +#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) -#define XSDPS_MMC_DELAY_FOR_SWITCH 1000 +#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U /* @} */ /* @400KHz, in usec */ -#define XSDPS_74CLK_DELAY 2960 -#define XSDPS_100CLK_DELAY 4000 -#define XSDPS_INIT_DELAY 10000 +#define XSDPS_74CLK_DELAY 2960U +#define XSDPS_100CLK_DELAY 4000U +#define XSDPS_INIT_DELAY 10000U #define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK -#define XSDPS_CARD_DEF_ADDR 0x1234 +#define XSDPS_CARD_DEF_ADDR 0x1234U -#define XSDPS_CARD_SD 1 -#define XSDPS_CARD_MMC 2 -#define XSDPS_CARD_SDIO 3 -#define XSDPS_CARD_SDCOMBO 4 -#define XSDPS_CHIP_EMMC 5 +#define XSDPS_CARD_SD 1U +#define XSDPS_CARD_MMC 2U +#define XSDPS_CARD_SDIO 3U +#define XSDPS_CARD_SDCOMBO 4U +#define XSDPS_CHIP_EMMC 5U /** @name ADMA2 Descriptor related definitions @@ -903,85 +904,85 @@ extern "C" { #define XSDPS_DESC_MAX_LENGTH 65536U -#define XSDPS_DESC_VALID (0x1 << 0) -#define XSDPS_DESC_END (0x1 << 1) -#define XSDPS_DESC_INT (0x1 << 2) -#define XSDPS_DESC_TRAN (0x2 << 4) +#define XSDPS_DESC_VALID (0x1U << 0) +#define XSDPS_DESC_END (0x1U << 1) +#define XSDPS_DESC_INT (0x1U << 2) +#define XSDPS_DESC_TRAN (0x2U << 4) /* @} */ /* For changing clock frequencies */ -#define XSDPS_CLK_400_KHZ 400000 /**< 400 KHZ */ -#define XSDPS_CLK_50_MHZ 50000000 /**< 50 MHZ */ -#define XSDPS_CLK_52_MHZ 52000000 /**< 52 MHZ */ -#define XSDPS_SD_VER_1_0 0x1 /**< SD ver 1 */ -#define XSDPS_SD_VER_2_0 0x2 /**< SD ver 2 */ -#define XSDPS_SCR_BLKCNT 1 -#define XSDPS_SCR_BLKSIZE 8 -#define XSDPS_1_BIT_WIDTH 0x1 -#define XSDPS_4_BIT_WIDTH 0x2 -#define XSDPS_8_BIT_WIDTH 0x3 -#define XSDPS_UHS_SPEED_MODE_SDR12 0x0 -#define XSDPS_UHS_SPEED_MODE_SDR25 0x1 -#define XSDPS_UHS_SPEED_MODE_SDR50 0x2 -#define XSDPS_UHS_SPEED_MODE_SDR104 0x3 -#define XSDPS_UHS_SPEED_MODE_DDR50 0x4 -#define XSDPS_SWITCH_CMD_BLKCNT 1 -#define XSDPS_SWITCH_CMD_BLKSIZE 64 -#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0 -#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1 -#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0 -#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1 -#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2 -#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3 -#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4 -#define XSDPS_EXT_CSD_CMD_BLKCNT 1 -#define XSDPS_EXT_CSD_CMD_BLKSIZE 512 -#define XSDPS_TUNING_CMD_BLKCNT 1 -#define XSDPS_TUNING_CMD_BLKSIZE 64 +#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */ +#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */ +#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */ +#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */ +#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */ +#define XSDPS_SCR_BLKCNT 1U +#define XSDPS_SCR_BLKSIZE 8U +#define XSDPS_1_BIT_WIDTH 0x1U +#define XSDPS_4_BIT_WIDTH 0x2U +#define XSDPS_8_BIT_WIDTH 0x3U +#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U +#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U +#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U +#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U +#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U +#define XSDPS_SWITCH_CMD_BLKCNT 1U +#define XSDPS_SWITCH_CMD_BLKSIZE 64U +#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U +#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U +#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U +#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U +#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U +#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U +#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U +#define XSDPS_EXT_CSD_CMD_BLKCNT 1U +#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U +#define XSDPS_TUNING_CMD_BLKCNT 1U +#define XSDPS_TUNING_CMD_BLKSIZE 64U -#define XSDPS_HIGH_SPEED_MAX_CLK 50000000 -#define XSDPS_UHS_SDR104_MAX_CLK 208000000 -#define XSDPS_UHS_SDR50_MAX_CLK 100000000 -#define XSDPS_UHS_DDR50_MAX_CLK 50000000 -#define XSDPS_UHS_SDR25_MAX_CLK 50000000 -#define XSDPS_UHS_SDR12_MAX_CLK 25000000 +#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U +#define XSDPS_UHS_SDR104_MAX_CLK 208000000U +#define XSDPS_UHS_SDR50_MAX_CLK 100000000U +#define XSDPS_UHS_DDR50_MAX_CLK 50000000U +#define XSDPS_UHS_SDR25_MAX_CLK 50000000U +#define XSDPS_UHS_SDR12_MAX_CLK 25000000U -#define SD_DRIVER_TYPE_B 0x01 -#define SD_DRIVER_TYPE_A 0x02 -#define SD_DRIVER_TYPE_C 0x04 -#define SD_DRIVER_TYPE_D 0x08 -#define SD_SET_CURRENT_LIMIT_200 0 -#define SD_SET_CURRENT_LIMIT_400 1 -#define SD_SET_CURRENT_LIMIT_600 2 -#define SD_SET_CURRENT_LIMIT_800 3 +#define SD_DRIVER_TYPE_B 0x01U +#define SD_DRIVER_TYPE_A 0x02U +#define SD_DRIVER_TYPE_C 0x04U +#define SD_DRIVER_TYPE_D 0x08U +#define SD_SET_CURRENT_LIMIT_200 0U +#define SD_SET_CURRENT_LIMIT_400 1U +#define SD_SET_CURRENT_LIMIT_600 2U +#define SD_SET_CURRENT_LIMIT_800 3U -#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200) -#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400) -#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600) -#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800) +#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) +#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) +#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) +#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) -#define XSDPS_SD_SDR12_MAX_CLK 25000000 -#define XSDPS_SD_SDR25_MAX_CLK 50000000 -#define XSDPS_SD_SDR50_MAX_CLK 100000000 -#define XSDPS_SD_DDR50_MAX_CLK 50000000 -#define XSDPS_SD_SDR104_MAX_CLK 208000000 -#define XSDPS_MMC_HS200_MAX_CLK 200000000 +#define XSDPS_SD_SDR12_MAX_CLK 25000000U +#define XSDPS_SD_SDR25_MAX_CLK 50000000U +#define XSDPS_SD_SDR50_MAX_CLK 100000000U +#define XSDPS_SD_DDR50_MAX_CLK 50000000U +#define XSDPS_SD_SDR104_MAX_CLK 208000000U +#define XSDPS_MMC_HS200_MAX_CLK 200000000U -#define XSDPS_CARD_STATE_IDLE 0 -#define XSDPS_CARD_STATE_RDY 1 -#define XSDPS_CARD_STATE_IDEN 2 -#define XSDPS_CARD_STATE_STBY 3 -#define XSDPS_CARD_STATE_TRAN 4 -#define XSDPS_CARD_STATE_DATA 5 -#define XSDPS_CARD_STATE_RCV 6 -#define XSDPS_CARD_STATE_PROG 7 -#define XSDPS_CARD_STATE_DIS 8 -#define XSDPS_CARD_STATE_BTST 9 -#define XSDPS_CARD_STATE_SLP 10 +#define XSDPS_CARD_STATE_IDLE 0U +#define XSDPS_CARD_STATE_RDY 1U +#define XSDPS_CARD_STATE_IDEN 2U +#define XSDPS_CARD_STATE_STBY 3U +#define XSDPS_CARD_STATE_TRAN 4U +#define XSDPS_CARD_STATE_DATA 5U +#define XSDPS_CARD_STATE_RCV 6U +#define XSDPS_CARD_STATE_PROG 7U +#define XSDPS_CARD_STATE_DIS 8U +#define XSDPS_CARD_STATE_BTST 9U +#define XSDPS_CARD_STATE_SLP 10U -#define XSDPS_SLOT_REM 0 -#define XSDPS_SLOT_EMB 1 +#define XSDPS_SLOT_REM 0U +#define XSDPS_SLOT_EMB 1U /**************************** Type Definitions *******************************/ diff --git a/XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c b/XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c index 675fca22..5ff1df87 100644 --- a/XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c +++ b/XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c @@ -50,6 +50,7 @@ * 2.3 sk 09/23/14 Use XSdPs_Change_ClkFreq API whenever changing * clock.CR# 816586. * 2.5 sg 07/09/15 Added SD 3.0 features +* kvn 07/15/15 Modified the code according to MISRAC-2012. * * * @@ -80,11 +81,11 @@ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Function Prototypes ******************************/ -int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); +s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); -int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); -static int XSdPs_Execute_Tuning(XSdPs *InstancePtr); -int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); +s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); +static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr); +s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); /*****************************************************************************/ /** @@ -96,10 +97,10 @@ int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); * @return None * ******************************************************************************/ -int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize) +s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize) { - u32 Status = 0; - u32 PresentStateReg = 0; + s32 Status; + u32 PresentStateReg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -107,28 +108,27 @@ int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize) PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); - if (PresentStateReg & (XSDPS_PSR_INHIBIT_CMD_MASK | - XSDPS_PSR_INHIBIT_DAT_MASK | - XSDPS_PSR_WR_ACTIVE_MASK | XSDPS_PSR_RD_ACTIVE_MASK)) { + if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK | + (u32)XSDPS_PSR_INHIBIT_DAT_MASK | + (u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) { Status = XST_FAILURE; goto RETURN_PATH; } /* Send block write command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); /* Set block size to the value passed */ - BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, - BlkSize); + BlkSize & XSDPS_BLK_SIZE_MASK); Status = XST_SUCCESS; @@ -153,24 +153,24 @@ int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize) * @note None. * ******************************************************************************/ -int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) +s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) { - u32 Status = 0; - u32 StatusReg = 0x0; + s32 Status; + u32 StatusReg; u16 BlkCnt; u16 BlkSize; - int LoopCnt; + s32 LoopCnt; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) { - SCR[LoopCnt] = 0; + SCR[LoopCnt] = 0U; } /* Send block write command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, - InstancePtr->RelCardAddr, 0); + InstancePtr->RelCardAddr, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -190,9 +190,9 @@ int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); - Xil_DCacheInvalidateRange(SCR, 8); + Xil_DCacheInvalidateRange((INTPTR)SCR, 8); - Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0, BlkCnt); + Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -205,7 +205,7 @@ int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, @@ -213,13 +213,13 @@ int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) Status = XST_FAILURE; goto RETURN_PATH; } - } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); - Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; @@ -244,11 +244,11 @@ int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) * @note None. * ******************************************************************************/ -int XSdPs_Change_BusWidth(XSdPs *InstancePtr) +s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) { - u32 Status = 0; - u32 StatusReg = 0x0; - u32 Arg = 0; + s32 Status; + u32 StatusReg; + u32 Arg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -257,7 +257,7 @@ int XSdPs_Change_BusWidth(XSdPs *InstancePtr) if (InstancePtr->CardType == XSDPS_CARD_SD) { Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, - 0); + 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -265,9 +265,9 @@ int XSdPs_Change_BusWidth(XSdPs *InstancePtr) InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH; - Arg = InstancePtr->BusWidth; + Arg = ((u32)InstancePtr->BusWidth); - Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0); + Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -288,7 +288,7 @@ int XSdPs_Change_BusWidth(XSdPs *InstancePtr) Arg = XSDPS_MMC_4_BIT_BUS_ARG; } - Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -320,9 +320,9 @@ int XSdPs_Change_BusWidth(XSdPs *InstancePtr) XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, - StatusReg); + (u8)StatusReg); - Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; @@ -349,20 +349,20 @@ int XSdPs_Change_BusWidth(XSdPs *InstancePtr) * @note None. * ******************************************************************************/ -int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) +s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) { - u32 Status = 0; - u32 StatusReg = 0x0; - u32 Arg = 0; + s32 Status; + u32 StatusReg; + u32 Arg; u16 BlkCnt; u16 BlkSize; - int LoopCnt; + s32 LoopCnt; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) { - ReadBuff[LoopCnt] = 0; + ReadBuff[LoopCnt] = 0U; } BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; @@ -379,9 +379,9 @@ int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) Arg = XSDPS_SWITCH_CMD_HS_GET; - Xil_DCacheInvalidateRange(ReadBuff, 64); + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); - Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -394,7 +394,7 @@ int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, @@ -402,13 +402,13 @@ int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) Status = XST_FAILURE; goto RETURN_PATH; } - } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); - Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; @@ -433,11 +433,11 @@ int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) * @note None. * ******************************************************************************/ -int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) +s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { - u32 Status = 0; - u32 StatusReg = 0x0; - u32 Arg = 0; + s32 Status; + u32 StatusReg; + u32 Arg; u32 ClockReg; u16 BlkCnt; u16 BlkSize; @@ -446,7 +446,7 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) u8 ReadBuff[64]; #pragma data_alignment = 4 #else - u8 ReadBuff[64] __attribute__ ((aligned(32))); + u8 ReadBuff[64] __attribute__ ((aligned(32))) = {0U}; #endif Xil_AssertNonvoid(InstancePtr != NULL); @@ -462,7 +462,7 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange(ReadBuff, 64); + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, @@ -470,7 +470,7 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) Arg = XSDPS_SWITCH_CMD_HS_SET; - Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -483,7 +483,7 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, @@ -491,7 +491,7 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) Status = XST_FAILURE; goto RETURN_PATH; } - } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -508,18 +508,22 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) } else if (InstancePtr->CardType == XSDPS_CARD_MMC) { Arg = XSDPS_MMC_HIGH_SPEED_ARG; - Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Change the clock frequency to 52 MHz */ InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ; - XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); + Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } else { Arg = XSDPS_MMC_HS200_ARG; - Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -528,7 +532,11 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) /* Change the clock frequency to 200 MHz */ InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; - XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); + Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } Status = XSdPs_Execute_Tuning(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -549,13 +557,13 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) #endif - StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, + StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL1_OFFSET,StatusReg); + XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); - Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); @@ -581,14 +589,15 @@ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) * or equal to the given value using the permissible dividors. * ******************************************************************************/ -int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) +s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) { u16 ClockReg; u16 DivCnt; - u16 Divisor; + u16 Divisor = 0U; u16 ExtDivisor; u16 ClkLoopCnt; - int Status; + s32 Status; + u16 ReadReg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -602,12 +611,11 @@ int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { /* Calculate divisor */ - for (DivCnt = 0x1; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;) { + for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) { if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) { Divisor = DivCnt >> 1; break; } - DivCnt++; } if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) { @@ -617,12 +625,13 @@ int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) } } else { /* Calculate divisor */ - for (DivCnt = 0x1; DivCnt <= XSDPS_CC_MAX_DIV_CNT;) { + DivCnt = 0x1U; + while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) { if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) { - Divisor = DivCnt / 2; + Divisor = DivCnt / 2U; break; } - DivCnt = DivCnt << 1; + DivCnt = DivCnt << 1U; } if (DivCnt > XSDPS_CC_MAX_DIV_CNT) { @@ -645,7 +654,7 @@ int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) Divisor <<= XSDPS_CC_DIV_SHIFT; Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK; - ClockReg |= Divisor | ExtDivisor | XSDPS_CC_INT_CLK_EN_MASK; + ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, ClockReg); } else { @@ -655,14 +664,18 @@ int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) Divisor <<= XSDPS_CC_DIV_SHIFT; Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK; - ClockReg |= Divisor | XSDPS_CC_INT_CLK_EN_MASK; + ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, ClockReg); } /* Wait for internal clock to stabilize */ - while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0); + ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET);; + } /* Enable SD clock */ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, @@ -693,21 +706,21 @@ RETURN_PATH: * @note None. * ******************************************************************************/ -int XSdPs_Pullup(XSdPs *InstancePtr) +s32 XSdPs_Pullup(XSdPs *InstancePtr) { - u32 Status = 0; + s32 Status; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Status = XSdPs_CmdTransfer(InstancePtr, CMD55, - InstancePtr->RelCardAddr, 0); + InstancePtr->RelCardAddr, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0, 0); + Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -736,20 +749,20 @@ int XSdPs_Pullup(XSdPs *InstancePtr) * @note None. * ******************************************************************************/ -int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) +s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) { - u32 Status = 0; - u32 StatusReg = 0x0; - u32 Arg = 0; + s32 Status; + u32 StatusReg; + u32 Arg = 0U; u16 BlkCnt; u16 BlkSize; - int LoopCnt; + s32 LoopCnt; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) { - ReadBuff[LoopCnt] = 0; + ReadBuff[LoopCnt] = 0U; } BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT; @@ -760,16 +773,15 @@ int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheInvalidateRange(ReadBuff, 512); + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); - Arg = 0; /* Send SEND_EXT_CSD command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1); + Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -782,7 +794,7 @@ int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, @@ -790,13 +802,13 @@ int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) Status = XST_FAILURE; goto RETURN_PATH; } - } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); - Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; @@ -823,12 +835,12 @@ int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) * @note None. * ******************************************************************************/ -int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) +s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) { - u32 Status = 0; - u16 StatusReg = 0; - u16 CtrlReg = 0; - u32 Arg = 0; + s32 Status; + u16 StatusReg; + u16 CtrlReg; + u32 Arg; u16 BlkCnt; u16 BlkSize; #ifdef __ICCARM__ @@ -836,7 +848,7 @@ int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) u8 ReadBuff[64]; #pragma data_alignment = 4 #else - u8 ReadBuff[64] __attribute__ ((aligned(32))); + u8 ReadBuff[64] __attribute__ ((aligned(32))) = {0U}; #endif Xil_AssertNonvoid(InstancePtr != NULL); @@ -853,29 +865,29 @@ int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange(ReadBuff, 64); + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); switch (Mode) { - case 0: + case 0U: Arg = XSDPS_SWITCH_CMD_SDR12_SET; InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK; break; - case 1: + case 1U: Arg = XSDPS_SWITCH_CMD_SDR25_SET; InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK; break; - case 2: + case 2U: Arg = XSDPS_SWITCH_CMD_SDR50_SET; InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK; break; - case 3: + case 3U: Arg = XSDPS_SWITCH_CMD_SDR104_SET; InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK; break; - case 4: + case 4U: Arg = XSDPS_SWITCH_CMD_DDR50_SET; InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK; break; @@ -885,7 +897,7 @@ int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) break; } - Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; @@ -898,14 +910,14 @@ int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } - } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -917,7 +929,7 @@ int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) /* Set UHS mode in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); - CtrlReg &= ~XSDPS_HC2_UHS_MODE_MASK; + CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK); CtrlReg |= Mode; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, CtrlReg); @@ -945,20 +957,20 @@ int XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) return Status; } -static int XSdPs_Execute_Tuning(XSdPs *InstancePtr) +static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) { - u32 Status = 0; - u32 StatusReg = 0x0; - u32 Arg = 0; + s32 Status; + u32 StatusReg; + u32 Arg; u16 BlkCnt; u16 BlkSize; - int LoopCnt; + s32 LoopCnt; #ifdef __ICCARM__ #pragma data_alignment = 32 u8 ReadBuff[128]; #pragma data_alignment = 4 #else - u8 ReadBuff[128] __attribute__ ((aligned(32))); + u8 ReadBuff[128] __attribute__ ((aligned(32))) = {0U}; #endif Xil_AssertNonvoid(InstancePtr != NULL); @@ -968,14 +980,14 @@ static int XSdPs_Execute_Tuning(XSdPs *InstancePtr) BlkSize = XSDPS_TUNING_CMD_BLKSIZE; if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { - BlkSize = BlkSize*2; + BlkSize = BlkSize*2U; } BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); - for (LoopCnt = 0; LoopCnt < BlkSize; LoopCnt++) { - ReadBuff[LoopCnt] = 0; + for (LoopCnt = 0; LoopCnt < (s32)BlkSize; LoopCnt++) { + ReadBuff[LoopCnt] = 0U; } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); @@ -983,12 +995,12 @@ static int XSdPs_Execute_Tuning(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); - Xil_DCacheInvalidateRange(ReadBuff, BlkSize); + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, BlkSize); if(InstancePtr->CardType == XSDPS_CARD_SD) { - Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0, 1); + Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U); } else { - Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0, 1); + Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U); } if (Status != XST_SUCCESS) { @@ -1003,14 +1015,14 @@ static int XSdPs_Execute_Tuning(XSdPs *InstancePtr) do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); - if (StatusReg & XSDPS_INTR_ERR_MASK) { + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } - } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, diff --git a/XilinxProcessorIPLib/drivers/sdps/src/xsdps_sinit.c b/XilinxProcessorIPLib/drivers/sdps/src/xsdps_sinit.c index baca2908..59657a7b 100644 --- a/XilinxProcessorIPLib/drivers/sdps/src/xsdps_sinit.c +++ b/XilinxProcessorIPLib/drivers/sdps/src/xsdps_sinit.c @@ -45,6 +45,7 @@ * Ver Who Date Changes * ----- --- -------- ----------------------------------------------- * 1.00a hk/sg 10/17/13 Initial release +* kvn 07/15/15 Modified the code according to MISRAC-2012. * * * @@ -85,14 +86,14 @@ extern XSdPs_Config XSdPs_ConfigTable[]; XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId) { XSdPs_Config *CfgPtr = NULL; - int Index; + u32 Index; - for (Index = 0; Index < XPAR_XSDPS_NUM_INSTANCES; Index++) { + for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) { if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) { CfgPtr = &XSdPs_ConfigTable[Index]; break; } } - return CfgPtr; + return (XSdPs_Config *)CfgPtr; } /** @} */