From c9796ae1ff6681f6c228490a4d4f0a70458da3b9 Mon Sep 17 00:00:00 2001 From: Rohit Consul Date: Wed, 27 May 2015 08:11:26 +0800 Subject: [PATCH] v_csc: Driver for CSC core HLS generated Layer 1 driver for csc core along with manually written layer 2. Pending update of driver tcl Signed-off-by: Rohit Consul --- .../drivers/v_csc/data/v_csc.mdd | 18 + .../drivers/v_csc/data/v_csc.tcl | 23 + .../drivers/v_csc/src/Makefile | 34 + .../drivers/v_csc/src/xv_csc.c | 744 ++++++++++ .../drivers/v_csc/src/xv_csc.h | 175 +++ .../drivers/v_csc/src/xv_csc_hw.h | 248 ++++ .../drivers/v_csc/src/xv_csc_l2.c | 1297 +++++++++++++++++ .../drivers/v_csc/src/xv_csc_l2.h | 397 +++++ .../drivers/v_csc/src/xv_csc_linux.c | 150 ++ .../drivers/v_csc/src/xv_csc_sinit.c | 45 + 10 files changed, 3131 insertions(+) create mode 100644 XilinxProcessorIPLib/drivers/v_csc/data/v_csc.mdd create mode 100644 XilinxProcessorIPLib/drivers/v_csc/data/v_csc.tcl create mode 100644 XilinxProcessorIPLib/drivers/v_csc/src/Makefile create mode 100644 XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.c create mode 100644 XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.h create mode 100644 XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_hw.h create mode 100644 XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.c create mode 100644 XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.h create mode 100644 XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_linux.c create mode 100644 XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_sinit.c diff --git a/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.mdd b/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.mdd new file mode 100644 index 00000000..c3aae35f --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.mdd @@ -0,0 +1,18 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +OPTION psf_version = 2.1; + +BEGIN driver v_csc + + OPTION supported_peripherals = (v_csc_v1_0 ); + OPTION driver_state = ACTIVE; + OPTION copyfiles = all; + OPTION name = v_csc; + OPTION version = 1.0; + +END driver diff --git a/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.tcl b/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.tcl new file mode 100644 index 00000000..d034c583 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/data/v_csc.tcl @@ -0,0 +1,23 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "XV_csc" \ + "NUM_INSTANCES" \ + "DEVICE_ID" \ + "C_S_AXI_CTRL_BASEADDR" \ + "C_S_AXI_CTRL_HIGHADDR" + + xdefine_config_file $drv_handle "xv_csc_g.c" "XV_csc" \ + "DEVICE_ID" \ + "C_S_AXI_CTRL_BASEADDR" + + xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_csc" \ + "DEVICE_ID" \ + "C_S_AXI_CTRL_BASEADDR" \ + "C_S_AXI_CTRL_HIGHADDR" +} diff --git a/XilinxProcessorIPLib/drivers/v_csc/src/Makefile b/XilinxProcessorIPLib/drivers/v_csc/src/Makefile new file mode 100644 index 00000000..926e6f73 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/src/Makefile @@ -0,0 +1,34 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + + +libs: + echo "Compiling v_csc" + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS) + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.c b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.c new file mode 100644 index 00000000..dd6dc72a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.c @@ -0,0 +1,744 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +/***************************** Include Files *********************************/ +#include "xv_csc.h" + +/************************** Function Implementation *************************/ +#ifndef __linux__ +int XV_csc_CfgInitialize(XV_csc *InstancePtr, XV_csc_Config *ConfigPtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + InstancePtr->Ctrl_BaseAddress = ConfigPtr->Ctrl_BaseAddress; + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} +#endif + +void XV_csc_Start(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL) & 0x80; + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, Data | 0x01); +} + +u32 XV_csc_IsDone(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL); + return (Data >> 1) & 0x1; +} + +u32 XV_csc_IsIdle(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL); + return (Data >> 2) & 0x1; +} + +u32 XV_csc_IsReady(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL); + // check ap_start to see if the pcore is ready for next input + return !(Data & 0x1); +} + +void XV_csc_EnableAutoRestart(XV_csc *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, 0x80); +} + +void XV_csc_DisableAutoRestart(XV_csc *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, 0); +} + +void XV_csc_Set_HwReg_InVideoFormat(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA, Data); +} + +u32 XV_csc_Get_HwReg_InVideoFormat(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA); + return Data; +} + +void XV_csc_Set_HwReg_OutVideoFormat(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA, Data); +} + +u32 XV_csc_Get_HwReg_OutVideoFormat(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA); + return Data; +} + +void XV_csc_Set_HwReg_width(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA, Data); +} + +u32 XV_csc_Get_HwReg_width(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA); + return Data; +} + +void XV_csc_Set_HwReg_height(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA, Data); +} + +u32 XV_csc_Get_HwReg_height(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA); + return Data; +} + +void XV_csc_Set_HwReg_ColStart(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA, Data); +} + +u32 XV_csc_Get_HwReg_ColStart(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA); + return Data; +} + +void XV_csc_Set_HwReg_ColEnd(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA, Data); +} + +u32 XV_csc_Get_HwReg_ColEnd(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA); + return Data; +} + +void XV_csc_Set_HwReg_RowStart(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA, Data); +} + +u32 XV_csc_Get_HwReg_RowStart(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA); + return Data; +} + +void XV_csc_Set_HwReg_RowEnd(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA, Data); +} + +u32 XV_csc_Get_HwReg_RowEnd(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K11(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K11(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K12(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K12(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K13(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K13(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K21(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K21(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K22(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K22(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K23(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K23(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K31(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K31(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K32(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K32(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K33(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K33(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_DATA); + return Data; +} + +void XV_csc_Set_HwReg_ROffset_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_ROffset_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_GOffset_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_GOffset_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_BOffset_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_BOffset_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_ClampMin_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_ClampMin_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_ClipMax_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_ClipMax_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K11_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K11_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K12_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K12_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K13_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K13_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K21_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K21_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K22_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K22_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K23_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K23_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K31_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K31_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K32_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K32_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_K33_2(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA, Data); +} + +u32 XV_csc_Get_HwReg_K33_2(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA); + return Data; +} + +void XV_csc_Set_HwReg_ROffset_2_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_ROffset_2_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_GOffset_2_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_GOffset_2_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_BOffset_2_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_BOffset_2_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_ClampMin_2_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_ClampMin_2_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA); + return Data; +} + +void XV_csc_Set_HwReg_ClipMax_2_V(XV_csc *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA, Data); +} + +u32 XV_csc_Get_HwReg_ClipMax_2_V(XV_csc *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA); + return Data; +} + +void XV_csc_InterruptGlobalEnable(XV_csc *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_GIE, 1); +} + +void XV_csc_InterruptGlobalDisable(XV_csc *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_GIE, 0); +} + +void XV_csc_InterruptEnable(XV_csc *InstancePtr, u32 Mask) { + u32 Register; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Register = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER); + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER, Register | Mask); +} + +void XV_csc_InterruptDisable(XV_csc *InstancePtr, u32 Mask) { + u32 Register; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Register = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER); + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER, Register & (~Mask)); +} + +void XV_csc_InterruptClear(XV_csc *InstancePtr, u32 Mask) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_ISR, Mask); +} + +u32 XV_csc_InterruptGetEnabled(XV_csc *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER); +} + +u32 XV_csc_InterruptGetStatus(XV_csc *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_ISR); +} diff --git a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.h b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.h new file mode 100644 index 00000000..be6c6aa5 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.h @@ -0,0 +1,175 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifndef XV_CSC_H +#define XV_CSC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#ifndef __linux__ +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xil_io.h" +#else +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif +#include "xv_csc_hw.h" + +/**************************** Type Definitions ******************************/ +#ifdef __linux__ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +#else +typedef struct { + u16 DeviceId; + u32 Ctrl_BaseAddress; +} XV_csc_Config; +#endif + +typedef struct { + u32 Ctrl_BaseAddress; + u32 IsReady; +} XV_csc; + +/***************** Macros (Inline Functions) Definitions *********************/ +#ifndef __linux__ +#define XV_csc_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) +#define XV_csc_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) +#else +#define XV_csc_WriteReg(BaseAddress, RegOffset, Data) \ + *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data) +#define XV_csc_ReadReg(BaseAddress, RegOffset) \ + *(volatile u32*)((BaseAddress) + (RegOffset)) + +#define Xil_AssertVoid(expr) assert(expr) +#define Xil_AssertNonvoid(expr) assert(expr) + +#define XST_SUCCESS 0 +#define XST_DEVICE_NOT_FOUND 2 +#define XST_OPEN_DEVICE_FAILED 3 +#define XIL_COMPONENT_IS_READY 1 +#endif + +/************************** Function Prototypes *****************************/ +#ifndef __linux__ +int XV_csc_Initialize(XV_csc *InstancePtr, u16 DeviceId); +XV_csc_Config* XV_csc_LookupConfig(u16 DeviceId); +int XV_csc_CfgInitialize(XV_csc *InstancePtr, XV_csc_Config *ConfigPtr); +#else +int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName); +int XV_csc_Release(XV_csc *InstancePtr); +#endif + +void XV_csc_Start(XV_csc *InstancePtr); +u32 XV_csc_IsDone(XV_csc *InstancePtr); +u32 XV_csc_IsIdle(XV_csc *InstancePtr); +u32 XV_csc_IsReady(XV_csc *InstancePtr); +void XV_csc_EnableAutoRestart(XV_csc *InstancePtr); +void XV_csc_DisableAutoRestart(XV_csc *InstancePtr); + +void XV_csc_Set_HwReg_InVideoFormat(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_InVideoFormat(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_OutVideoFormat(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_OutVideoFormat(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_width(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_width(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_height(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_height(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_ColStart(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_ColStart(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_ColEnd(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_ColEnd(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_RowStart(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_RowStart(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_RowEnd(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_RowEnd(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K11(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K11(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K12(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K12(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K13(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K13(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K21(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K21(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K22(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K22(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K23(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K23(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K31(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K31(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K32(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K32(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K33(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K33(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_ROffset_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_ROffset_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_GOffset_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_GOffset_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_BOffset_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_BOffset_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_ClampMin_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_ClampMin_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_ClipMax_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_ClipMax_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K11_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K11_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K12_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K12_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K13_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K13_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K21_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K21_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K22_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K22_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K23_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K23_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K31_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K31_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K32_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K32_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_K33_2(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_K33_2(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_ROffset_2_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_ROffset_2_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_GOffset_2_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_GOffset_2_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_BOffset_2_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_BOffset_2_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_ClampMin_2_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_ClampMin_2_V(XV_csc *InstancePtr); +void XV_csc_Set_HwReg_ClipMax_2_V(XV_csc *InstancePtr, u32 Data); +u32 XV_csc_Get_HwReg_ClipMax_2_V(XV_csc *InstancePtr); + +void XV_csc_InterruptGlobalEnable(XV_csc *InstancePtr); +void XV_csc_InterruptGlobalDisable(XV_csc *InstancePtr); +void XV_csc_InterruptEnable(XV_csc *InstancePtr, u32 Mask); +void XV_csc_InterruptDisable(XV_csc *InstancePtr, u32 Mask); +void XV_csc_InterruptClear(XV_csc *InstancePtr, u32 Mask); +u32 XV_csc_InterruptGetEnabled(XV_csc *InstancePtr); +u32 XV_csc_InterruptGetStatus(XV_csc *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_hw.h b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_hw.h new file mode 100644 index 00000000..a218f8a2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_hw.h @@ -0,0 +1,248 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +// CTRL +// 0x000 : Control signals +// bit 0 - ap_start (Read/Write/COH) +// bit 1 - ap_done (Read/COR) +// bit 2 - ap_idle (Read) +// bit 3 - ap_ready (Read) +// bit 7 - auto_restart (Read/Write) +// others - reserved +// 0x004 : Global Interrupt Enable Register +// bit 0 - Global Interrupt Enable (Read/Write) +// others - reserved +// 0x008 : IP Interrupt Enable Register (Read/Write) +// bit 0 - Channel 0 (ap_done) +// bit 1 - Channel 1 (ap_ready) +// others - reserved +// 0x00c : IP Interrupt Status Register (Read/TOW) +// bit 0 - Channel 0 (ap_done) +// bit 1 - Channel 1 (ap_ready) +// others - reserved +// 0x010 : Data signal of HwReg_InVideoFormat +// bit 7~0 - HwReg_InVideoFormat[7:0] (Read/Write) +// others - reserved +// 0x014 : reserved +// 0x018 : Data signal of HwReg_OutVideoFormat +// bit 7~0 - HwReg_OutVideoFormat[7:0] (Read/Write) +// others - reserved +// 0x01c : reserved +// 0x020 : Data signal of HwReg_width +// bit 15~0 - HwReg_width[15:0] (Read/Write) +// others - reserved +// 0x024 : reserved +// 0x028 : Data signal of HwReg_height +// bit 15~0 - HwReg_height[15:0] (Read/Write) +// others - reserved +// 0x02c : reserved +// 0x030 : Data signal of HwReg_ColStart +// bit 15~0 - HwReg_ColStart[15:0] (Read/Write) +// others - reserved +// 0x034 : reserved +// 0x038 : Data signal of HwReg_ColEnd +// bit 15~0 - HwReg_ColEnd[15:0] (Read/Write) +// others - reserved +// 0x03c : reserved +// 0x040 : Data signal of HwReg_RowStart +// bit 15~0 - HwReg_RowStart[15:0] (Read/Write) +// others - reserved +// 0x044 : reserved +// 0x048 : Data signal of HwReg_RowEnd +// bit 15~0 - HwReg_RowEnd[15:0] (Read/Write) +// others - reserved +// 0x04c : reserved +// 0x050 : Data signal of HwReg_K11 +// bit 15~0 - HwReg_K11[15:0] (Read/Write) +// others - reserved +// 0x054 : reserved +// 0x058 : Data signal of HwReg_K12 +// bit 15~0 - HwReg_K12[15:0] (Read/Write) +// others - reserved +// 0x05c : reserved +// 0x060 : Data signal of HwReg_K13 +// bit 15~0 - HwReg_K13[15:0] (Read/Write) +// others - reserved +// 0x064 : reserved +// 0x068 : Data signal of HwReg_K21 +// bit 15~0 - HwReg_K21[15:0] (Read/Write) +// others - reserved +// 0x06c : reserved +// 0x070 : Data signal of HwReg_K22 +// bit 15~0 - HwReg_K22[15:0] (Read/Write) +// others - reserved +// 0x074 : reserved +// 0x078 : Data signal of HwReg_K23 +// bit 15~0 - HwReg_K23[15:0] (Read/Write) +// others - reserved +// 0x07c : reserved +// 0x080 : Data signal of HwReg_K31 +// bit 15~0 - HwReg_K31[15:0] (Read/Write) +// others - reserved +// 0x084 : reserved +// 0x088 : Data signal of HwReg_K32 +// bit 15~0 - HwReg_K32[15:0] (Read/Write) +// others - reserved +// 0x08c : reserved +// 0x090 : Data signal of HwReg_K33 +// bit 15~0 - HwReg_K33[15:0] (Read/Write) +// others - reserved +// 0x094 : reserved +// 0x098 : Data signal of HwReg_ROffset_V +// bit 11~0 - HwReg_ROffset_V[11:0] (Read/Write) +// others - reserved +// 0x09c : reserved +// 0x0a0 : Data signal of HwReg_GOffset_V +// bit 11~0 - HwReg_GOffset_V[11:0] (Read/Write) +// others - reserved +// 0x0a4 : reserved +// 0x0a8 : Data signal of HwReg_BOffset_V +// bit 11~0 - HwReg_BOffset_V[11:0] (Read/Write) +// others - reserved +// 0x0ac : reserved +// 0x0b0 : Data signal of HwReg_ClampMin_V +// bit 9~0 - HwReg_ClampMin_V[9:0] (Read/Write) +// others - reserved +// 0x0b4 : reserved +// 0x0b8 : Data signal of HwReg_ClipMax_V +// bit 9~0 - HwReg_ClipMax_V[9:0] (Read/Write) +// others - reserved +// 0x0bc : reserved +// 0x0c0 : Data signal of HwReg_K11_2 +// bit 15~0 - HwReg_K11_2[15:0] (Read/Write) +// others - reserved +// 0x0c4 : reserved +// 0x0c8 : Data signal of HwReg_K12_2 +// bit 15~0 - HwReg_K12_2[15:0] (Read/Write) +// others - reserved +// 0x0cc : reserved +// 0x0d0 : Data signal of HwReg_K13_2 +// bit 15~0 - HwReg_K13_2[15:0] (Read/Write) +// others - reserved +// 0x0d4 : reserved +// 0x0d8 : Data signal of HwReg_K21_2 +// bit 15~0 - HwReg_K21_2[15:0] (Read/Write) +// others - reserved +// 0x0dc : reserved +// 0x0e0 : Data signal of HwReg_K22_2 +// bit 15~0 - HwReg_K22_2[15:0] (Read/Write) +// others - reserved +// 0x0e4 : reserved +// 0x0e8 : Data signal of HwReg_K23_2 +// bit 15~0 - HwReg_K23_2[15:0] (Read/Write) +// others - reserved +// 0x0ec : reserved +// 0x0f0 : Data signal of HwReg_K31_2 +// bit 15~0 - HwReg_K31_2[15:0] (Read/Write) +// others - reserved +// 0x0f4 : reserved +// 0x0f8 : Data signal of HwReg_K32_2 +// bit 15~0 - HwReg_K32_2[15:0] (Read/Write) +// others - reserved +// 0x0fc : reserved +// 0x100 : Data signal of HwReg_K33_2 +// bit 15~0 - HwReg_K33_2[15:0] (Read/Write) +// others - reserved +// 0x104 : reserved +// 0x108 : Data signal of HwReg_ROffset_2_V +// bit 11~0 - HwReg_ROffset_2_V[11:0] (Read/Write) +// others - reserved +// 0x10c : reserved +// 0x110 : Data signal of HwReg_GOffset_2_V +// bit 11~0 - HwReg_GOffset_2_V[11:0] (Read/Write) +// others - reserved +// 0x114 : reserved +// 0x118 : Data signal of HwReg_BOffset_2_V +// bit 11~0 - HwReg_BOffset_2_V[11:0] (Read/Write) +// others - reserved +// 0x11c : reserved +// 0x120 : Data signal of HwReg_ClampMin_2_V +// bit 9~0 - HwReg_ClampMin_2_V[9:0] (Read/Write) +// others - reserved +// 0x124 : reserved +// 0x128 : Data signal of HwReg_ClipMax_2_V +// bit 9~0 - HwReg_ClipMax_2_V[9:0] (Read/Write) +// others - reserved +// 0x12c : reserved +// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) + +#define XV_CSC_CTRL_ADDR_AP_CTRL 0x000 +#define XV_CSC_CTRL_ADDR_GIE 0x004 +#define XV_CSC_CTRL_ADDR_IER 0x008 +#define XV_CSC_CTRL_ADDR_ISR 0x00c +#define XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA 0x010 +#define XV_CSC_CTRL_BITS_HWREG_INVIDEOFORMAT_DATA 8 +#define XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA 0x018 +#define XV_CSC_CTRL_BITS_HWREG_OUTVIDEOFORMAT_DATA 8 +#define XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA 0x020 +#define XV_CSC_CTRL_BITS_HWREG_WIDTH_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA 0x028 +#define XV_CSC_CTRL_BITS_HWREG_HEIGHT_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA 0x030 +#define XV_CSC_CTRL_BITS_HWREG_COLSTART_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA 0x038 +#define XV_CSC_CTRL_BITS_HWREG_COLEND_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA 0x040 +#define XV_CSC_CTRL_BITS_HWREG_ROWSTART_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA 0x048 +#define XV_CSC_CTRL_BITS_HWREG_ROWEND_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K11_DATA 0x050 +#define XV_CSC_CTRL_BITS_HWREG_K11_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K12_DATA 0x058 +#define XV_CSC_CTRL_BITS_HWREG_K12_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K13_DATA 0x060 +#define XV_CSC_CTRL_BITS_HWREG_K13_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K21_DATA 0x068 +#define XV_CSC_CTRL_BITS_HWREG_K21_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K22_DATA 0x070 +#define XV_CSC_CTRL_BITS_HWREG_K22_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K23_DATA 0x078 +#define XV_CSC_CTRL_BITS_HWREG_K23_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K31_DATA 0x080 +#define XV_CSC_CTRL_BITS_HWREG_K31_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K32_DATA 0x088 +#define XV_CSC_CTRL_BITS_HWREG_K32_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K33_DATA 0x090 +#define XV_CSC_CTRL_BITS_HWREG_K33_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA 0x098 +#define XV_CSC_CTRL_BITS_HWREG_ROFFSET_V_DATA 12 +#define XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA 0x0a0 +#define XV_CSC_CTRL_BITS_HWREG_GOFFSET_V_DATA 12 +#define XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA 0x0a8 +#define XV_CSC_CTRL_BITS_HWREG_BOFFSET_V_DATA 12 +#define XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA 0x0b0 +#define XV_CSC_CTRL_BITS_HWREG_CLAMPMIN_V_DATA 10 +#define XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA 0x0b8 +#define XV_CSC_CTRL_BITS_HWREG_CLIPMAX_V_DATA 10 +#define XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA 0x0c0 +#define XV_CSC_CTRL_BITS_HWREG_K11_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA 0x0c8 +#define XV_CSC_CTRL_BITS_HWREG_K12_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA 0x0d0 +#define XV_CSC_CTRL_BITS_HWREG_K13_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA 0x0d8 +#define XV_CSC_CTRL_BITS_HWREG_K21_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA 0x0e0 +#define XV_CSC_CTRL_BITS_HWREG_K22_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA 0x0e8 +#define XV_CSC_CTRL_BITS_HWREG_K23_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA 0x0f0 +#define XV_CSC_CTRL_BITS_HWREG_K31_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA 0x0f8 +#define XV_CSC_CTRL_BITS_HWREG_K32_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA 0x100 +#define XV_CSC_CTRL_BITS_HWREG_K33_2_DATA 16 +#define XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA 0x108 +#define XV_CSC_CTRL_BITS_HWREG_ROFFSET_2_V_DATA 12 +#define XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA 0x110 +#define XV_CSC_CTRL_BITS_HWREG_GOFFSET_2_V_DATA 12 +#define XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA 0x118 +#define XV_CSC_CTRL_BITS_HWREG_BOFFSET_2_V_DATA 12 +#define XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA 0x120 +#define XV_CSC_CTRL_BITS_HWREG_CLAMPMIN_2_V_DATA 10 +#define XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA 0x128 +#define XV_CSC_CTRL_BITS_HWREG_CLIPMAX_2_V_DATA 10 diff --git a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.c b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.c new file mode 100644 index 00000000..44303c57 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.c @@ -0,0 +1,1297 @@ +/****************************************************************************** + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xv_csc_l2.c +* +* The CSC Layer-2 Driver. The functions in this file provides an abstraction +* from the register peek/poke methodology by implementing most common use-case +* provided by the sub-core. See xv_csc_l2.h for a detailed description of the +* layer-2 driver +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  rc   05/01/15   Initial Release
+
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xv_csc_l2.h" + +/************************** Constant Definitions *****************************/ +/* Maximum precision available for csc coefficients */ +#define XV_CSC_COEFF_FRACTIONAL_BITS (12) + +/**************************** Type Definitions *******************************/ +/** + * This typedef enumerates the window within which the csc core will have an + * impact. Coordinates outside the window will be passed as-is to output + */ +typedef enum +{ + UPDT_REG_FULL_FRAME = 0, + UPD_REG_DEMO_WIN +}XV_CSC_REG_UPDT_WIN; + + +/**************************** Local Global *******************************/ + +/************************** Function Prototypes ******************************/ +static void cscFwYCbCrtoRGB(s32 K[3][4], + XVidC_ColorStd cstdIn, + s32 pixPrec, + s32 *ClampMin, + s32 *ClipMax); + +static void cscFwRGBtoYCbCr(s32 K[3][4], + XVidC_ColorStd cstdOut, + s32 pixPrec, + s32 *ClampMin, + s32 *ClipMax); +#if 0 //currently not used +static void cscFwGetCoefficients(XV_csc_L2Reg *pCscFwReg, + s32 K[3][4], + s32 *ClampMin, + s32 *ClipMax); +#endif +static void cscFwSetCoefficients(XV_csc_L2Reg *pCscFwReg, + s32 K[3][4], + s32 ClampMin, + s32 ClipMax); +static void cscFwGetActiveCoefficients(XV_csc_L2Reg *pCscFwReg, s32 K[3][4]); +static void cscFwSetActiveCoefficients(XV_csc_L2Reg *pCscFwReg, s32 K[3][4]); +static void cscFwMatrixMult(s32 K1[3][4], s32 K2[3][4], s32 Kout[3][4]); +static void cscFwComputeCoeff(XV_csc_L2Reg *pCscFwReg, + s32 K2[3][4]); +static void cscUpdateIPReg(XV_csc *pCsc, + XV_csc_L2Reg *pCscFwReg, + XV_CSC_REG_UPDT_WIN win); +/*****************************************************************************/ +/** +* This function provides the write interface for FW register bank +* +* @param pCscFwReg is a pointer to fw register map of csc core instance +* @param offset is register offset +* @param val is data to write +* +* @return None +* +******************************************************************************/ +__inline void cscFw_RegW(XV_csc_L2Reg *pCscFwReg, u32 offset, s32 val) +{ + pCscFwReg->regMap[offset] = val; +} + +/*****************************************************************************/ +/** +* This function provides the read interface for FW register bank +* +* @param pCscFwReg is a pointer to fw register map of csc core instance +* @param offset is register offset +* +* @return Register value at requested offset +* +* +******************************************************************************/ +__inline s32 cscFw_RegR(XV_csc_L2Reg *pCscFwReg, u32 offset) +{ + return pCscFwReg->regMap[offset]; +} + +/*****************************************************************************/ +/** +* This function starts the Color space converter core +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XV_CscStart(XV_csc *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_csc_EnableAutoRestart(InstancePtr); + XV_csc_Start(InstancePtr); +} + +/*****************************************************************************/ +/** +* This function stops the Color space converter +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XV_CscStop(XV_csc *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_csc_DisableAutoRestart(InstancePtr); +} + +/*****************************************************************************/ +/** +* This function set the frame resolution for the Color space converter +* This also will reset the demo window to full frame +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* @param width is the input stream width +* @param height is the input stream height +* +* @return None +* +******************************************************************************/ +void XV_CscSetActiveSize(XV_csc *InstancePtr, + u32 width, + u32 height) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_csc_Set_HwReg_width(InstancePtr, width); + XV_csc_Set_HwReg_height(InstancePtr, height); + + //Reset demo window to full frame + XV_csc_Set_HwReg_ColStart(InstancePtr, 0); + XV_csc_Set_HwReg_ColEnd(InstancePtr, (width-1)); + XV_csc_Set_HwReg_RowStart(InstancePtr, 0); + XV_csc_Set_HwReg_RowEnd(InstancePtr, (height-1)); +} + +/*****************************************************************************/ +/** +* This function set the demo window for the Color space converter. Any pixel +* outside the demo window will not be impacted and will be passed to output +* as-is +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* @param ActiveWindow is structure that contains window coordinates and size +* +* @return None +* +******************************************************************************/ +void XV_CscSetDemoWindow(XV_csc *InstancePtr, XVidC_VideoWindow *ActiveWindow) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_csc_Set_HwReg_ColStart(InstancePtr, ActiveWindow->StartX); + XV_csc_Set_HwReg_ColEnd(InstancePtr, (ActiveWindow->StartX+ActiveWindow->Width-1)); + XV_csc_Set_HwReg_RowStart(InstancePtr, ActiveWindow->StartY); + XV_csc_Set_HwReg_RowEnd(InstancePtr, (ActiveWindow->StartY+ActiveWindow->Height-1)); +} + + +/*****************************************************************************/ +/** +* This function sets the CSC IP layer 2 fw registers to power on default state +* +* @param pCscFwReg is a pointer to the layer 2 fw register bank +* +* @return None +* +******************************************************************************/ +void XV_CscInitPowerOnDefault(XV_csc_L2Reg *pCscFwReg) +{ + Xil_AssertVoid(pCscFwReg != NULL); + + pCscFwReg->ColorFormatIn = XVIDC_CSF_RGB; + pCscFwReg->ColorFormatOut = XVIDC_CSF_RGB; + pCscFwReg->StandardIn = XVIDC_BT_601; + pCscFwReg->StandardOut = XVIDC_BT_601; + pCscFwReg->OutputRange = XVIDC_CR_0_255; + pCscFwReg->ColorDepth = XVIDC_BPC_8; + pCscFwReg->Brightness = 120; + pCscFwReg->Contrast = 0; + pCscFwReg->Saturation = 100; + pCscFwReg->RedGain = 120; + pCscFwReg->GreenGain = 120; + pCscFwReg->BlueGain = 120; + pCscFwReg->Brightness_active = 120; + pCscFwReg->Contrast_active = 0; + pCscFwReg->Saturation_active = 100; + pCscFwReg->RedGain_active = 120; + pCscFwReg->GreenGain_active = 120; + pCscFwReg->BlueGain_active = 120; + pCscFwReg->K_active[0][0] = (1<K_active[0][1] = 0; + pCscFwReg->K_active[0][2] = 0; + pCscFwReg->K_active[1][0] = 0; + pCscFwReg->K_active[1][1] = (1<K_active[1][2] = 0; + pCscFwReg->K_active[2][0] = 0; + pCscFwReg->K_active[2][1] = 0; + pCscFwReg->K_active[2][2] = (1<K_active[0][3] = 0; + pCscFwReg->K_active[1][3] = 0; + pCscFwReg->K_active[2][3] = 0; +} + + +/*****************************************************************************/ +/** + * This function configures the Color space converter to user specified + * settings. Before any feature specific calls in layer-2 driver is made + * csc core should have been configured via this call. + * + * @param InstancePtr is a pointer to the core instance to be worked on. + * @param pCscFwReg is pointer to layer 2 register bank + * @param cfmtIn is input color space + * @param cfmtOut is output color space + * @param cstdIn is input color standard + * @param cstdOut is output color standard + * @param cRangeOut is the selected output range + * + * @return None + * + *****************************************************************************/ +void XV_CscSetColorspace(XV_csc *InstancePtr, + XV_csc_L2Reg *pCscFwReg, + XVidC_ColorFormat cfmtIn, + XVidC_ColorFormat cfmtOut, + XVidC_ColorStd cstdIn, + XVidC_ColorStd cstdOut, + XVidC_ColorRange cRangeOut + ) +{ + s32 K[3][4], K1[3][4], K2[3][4]; + s32 ClampMin = 0; + s32 ClipMax; + s32 scale_factor; + XV_csc *pCsc = InstancePtr; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pCscFwReg != NULL); + + ClipMax = ((1<ColorDepth)-1); + scale_factor = (1<ColorDepth, &ClampMin, &ClipMax); + } + else if ((cfmtIn == XVIDC_CSF_YCRCB_444) && (cfmtOut == XVIDC_CSF_RGB)) + { + cscFwYCbCrtoRGB(K, cstdIn, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + } + else if ((cfmtIn == XVIDC_CSF_RGB) && (cfmtOut == XVIDC_CSF_RGB) ) + { + //nop + } + else //422->422 or 444->444 + { + if (cstdIn != cstdOut) + { + cscFwYCbCrtoRGB(K1, cstdIn, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwRGBtoYCbCr(K2, cstdOut, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(K1, K2, K); + } + } + //update fw registers + pCscFwReg->ColorFormatIn = cfmtIn; + pCscFwReg->ColorFormatOut = cfmtOut; + pCscFwReg->StandardIn = cstdIn; + pCscFwReg->StandardOut = cstdOut; + pCscFwReg->OutputRange = cRangeOut; + + cscFw_RegW(pCscFwReg, CSC_FW_REG_K11,K[0][0]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_K12,K[0][1]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_K13,K[0][2]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_K21,K[1][0]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_K22,K[1][1]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_K23,K[1][2]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_K13,K[2][0]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_K32,K[2][1]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_K33,K[2][2]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_ROffset,K[0][3]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_GOffset,K[1][3]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_BOffset,K[2][3]); + cscFw_RegW(pCscFwReg, CSC_FW_REG_ClampMin,ClampMin); + cscFw_RegW(pCscFwReg, CSC_FW_REG_ClipMax,ClipMax); + + //compute coeff for Demo window + cscFwComputeCoeff(pCscFwReg, pCscFwReg->K_active); + + //write IP Registers + cscUpdateIPReg(pCsc, pCscFwReg, UPDT_REG_FULL_FRAME); + cscUpdateIPReg(pCsc, pCscFwReg, UPD_REG_DEMO_WIN); +} + +/*****************************************************************************/ +/** +* This function sets coefficients for YCbCr to RGB conversion +* +* @param YCC2RGB is the array to hold coefficients +* @param cstdIn is input color standard +* @param pixPrec is the color depth +* @param ClampMin is min value to clamp computed by the function +* @param ClipMax is max value to saturate computed by the function +* +* @return Implicitly returns Clamp Min/Max values +* +******************************************************************************/ +static void cscFwYCbCrtoRGB(s32 YCC2RGB[3][4], + XVidC_ColorStd cstdIn, + s32 pixPrec, + s32 *ClampMin, + s32 *ClipMax) +{ + s32 scale_factor = (1<K_active[x][y]; + } + } +} + +/*****************************************************************************/ +/** +* This function sets the current RGB coefficients for demo window +* +* @param pCscFwReg is the pointer to layer 2 fw register bank +* @param K is the array to hold coefficients +* +* @return None +* +******************************************************************************/ +static void cscFwSetActiveCoefficients(XV_csc_L2Reg *pCscFwReg, s32 K[3][4]) +{ + u8 x,y; + + for(x=0; x<3; ++x) + { + for(y=0; y<4; ++y) + { + pCscFwReg->K_active[x][y] = K[x][y]; + } + } +} + +/*****************************************************************************/ +/** +* This function set brightness to specified value. It also translates user +* setting of 0-100 to hw register range +* +* @param InstancePtr is pointer to csc core instance +* @param pCscFwReg is a pointer to layer 2 fw register bank +* @param val is new brightness value +* +* @return None +* +******************************************************************************/ +void XV_CscSetBrightness(XV_csc *InstancePtr, XV_csc_L2Reg *pCscFwReg, s32 val) +{ + XV_csc *pCsc = InstancePtr; + s32 K1[3][4], K2[3][4]; + float brightness_f; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pCscFwReg != NULL); + + pCscFwReg->Brightness = (val*2+20); + brightness_f = (float)(pCscFwReg->Brightness)/(float)(pCscFwReg->Brightness_active); + + //get active coefficient set in RGB + cscFwGetActiveCoefficients(pCscFwReg, K1); + + K2[0][0] = (s32) ((float) K1[0][0] * brightness_f); + K2[0][1] = (s32) ((float) K1[0][1] * brightness_f); + K2[0][2] = (s32) ((float) K1[0][2] * brightness_f); + K2[1][0] = (s32) ((float) K1[1][0] * brightness_f); + K2[1][1] = (s32) ((float) K1[1][1] * brightness_f); + K2[1][2] = (s32) ((float) K1[1][2] * brightness_f); + K2[2][0] = (s32) ((float) K1[2][0] * brightness_f); + K2[2][1] = (s32) ((float) K1[2][1] * brightness_f); + K2[2][2] = (s32) ((float) K1[2][2] * brightness_f); + K2[0][3] = K1[0][3]; + K2[1][3] = K1[1][3]; + K2[2][3] = K1[2][3]; + + //write new active coefficient set in RGB + cscFwSetActiveCoefficients(pCscFwReg, K2); + //write new active brightness value + pCscFwReg->Brightness_active = pCscFwReg->Brightness; + + cscFwComputeCoeff(pCscFwReg, K2); + cscUpdateIPReg(pCsc, pCscFwReg, UPD_REG_DEMO_WIN); +} + +/*****************************************************************************/ +/** +* This function set contrast to specified value. It also translates user +* setting of 0-100 to hw register range +* +* @param InstancePtr is pointer to csc core instance +* @param pCscFwReg is a pointer to layer 2 fw register bank +* @param val is new contrast value +* +* @return None +* +******************************************************************************/ +void XV_CscSetContrast(XV_csc *InstancePtr, XV_csc_L2Reg *pCscFwReg, s32 val) +{ + XV_csc *pCsc = InstancePtr; + s32 contrast; + s32 K1[3][4], K2[3][4]; + s32 scale; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pCscFwReg != NULL); + + pCscFwReg->Contrast = val*4 - 200; + contrast = (pCscFwReg->Contrast) - (pCscFwReg->Contrast_active); + + scale = (1<<(pCscFwReg->ColorDepth-8)); + //get active coefficient set in RGB + cscFwGetActiveCoefficients(pCscFwReg, K1); + + K2[0][0] = K1[0][0]; + K2[0][1] = K1[0][1]; + K2[0][2] = K1[0][2]; + K2[1][0] = K1[1][0]; + K2[1][1] = K1[1][1]; + K2[1][2] = K1[1][2]; + K2[2][0] = K1[2][0]; + K2[2][1] = K1[2][1]; + K2[2][2] = K1[2][2]; + K2[0][3] = K1[0][3] + contrast*scale; + K2[1][3] = K1[1][3] + contrast*scale; + K2[2][3] = K1[2][3] + contrast*scale; + + //write new active coefficient set in RGB + cscFwSetActiveCoefficients(pCscFwReg, K2); + //write new active contrast value + pCscFwReg->Contrast_active = pCscFwReg->Contrast; + + cscFwComputeCoeff(pCscFwReg, K2); + cscUpdateIPReg(pCsc, pCscFwReg, UPD_REG_DEMO_WIN); +} + +/*****************************************************************************/ +/** +* This function set saturation to specified value. It also translates user +* setting of 0-100 to hw register range +* +* @param InstancePtr is pointer to csc core instance +* @param pCscFwReg is a pointer to layer 2 fw register bank +* @param val is new saturation value +* +* @return None +* +******************************************************************************/ +void XV_CscSetSaturation(XV_csc *InstancePtr, XV_csc_L2Reg *pCscFwReg, s32 val) +{ + XV_csc *pCsc = InstancePtr; + s32 x, y; + s32 K1[3][4], K2[3][4], K3[3][4], K4[3][4], M1[3][4], M2[3][4], Kout[3][4]; + s32 ClampMin = 0; + s32 ClipMax, scale_factor; + + float saturation_f; + float rwgt, gwgt, bwgt; + float a,b,c,d,e,f,g,h,i; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pCscFwReg != NULL); + + ClipMax = ((1<ColorDepth)-1); + scale_factor = (1<Saturation = ((val == 0) ? 1 : val*2); + saturation_f = (float)(pCscFwReg->Saturation)/(float)(pCscFwReg->Saturation_active); + + //get active coefficient set in RGB + cscFwGetActiveCoefficients(pCscFwReg, K1); + + rwgt = 0.3086f; + gwgt = 0.6094f; + bwgt = 0.0820f; + //rwgt = 0.299f; + //gwgt = 0.587f; + //bwgt = 0.114f; + + a = ((1.0f - saturation_f) * rwgt + saturation_f); + b = ((1.0f - saturation_f) * rwgt); + c = ((1.0f - saturation_f) * rwgt); + d = ((1.0f - saturation_f) * gwgt); + e = ((1.0f - saturation_f) * gwgt + saturation_f); + f = ((1.0f - saturation_f) * gwgt); + g = ((1.0f - saturation_f) * bwgt); + h = ((1.0f - saturation_f) * bwgt); + i = ((1.0f - saturation_f) * bwgt + saturation_f); + + K2[0][0]=(s32)(a*scale_factor); + K2[0][1]=(s32)(d*scale_factor); + K2[0][2]=(s32)(g*scale_factor); + K2[1][0]=(s32)(b*scale_factor); + K2[1][1]=(s32)(e*scale_factor); + K2[1][2]=(s32)(h*scale_factor); + K2[2][0]=(s32)(c*scale_factor); + K2[2][1]=(s32)(f*scale_factor); + K2[2][2]=(s32)(i*scale_factor); + K2[0][3] = 0; + K2[1][3] = 0; + K2[2][3] = 0; + + cscFwMatrixMult(K1, K2, K3); + + //write new active coefficient set in RGB + cscFwSetActiveCoefficients(pCscFwReg, K3); + //write new active saturation value + pCscFwReg->Saturation_active = pCscFwReg->Saturation; + + if ((pCscFwReg->ColorFormatIn == XVIDC_CSF_RGB) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_RGB) ) + { + for (x=0; x<3; x++) for (y=0; y<4; y++) + Kout[x][y] = K3[x][y]; + } + + if ((pCscFwReg->ColorFormatIn == XVIDC_CSF_RGB) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_YCRCB_444) ) + { + cscFwRGBtoYCbCr(M2, pCscFwReg->StandardOut, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(K3, M2, Kout); + } + + if ((pCscFwReg->ColorFormatIn == XVIDC_CSF_YCRCB_444) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_RGB) ) + { + cscFwYCbCrtoRGB(M1, pCscFwReg->StandardIn, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(M1, K3, Kout); + } + + if ((pCscFwReg->ColorFormatIn == XVIDC_CSF_YCRCB_444) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_YCRCB_444) ) + { + cscFwYCbCrtoRGB(M1, pCscFwReg->StandardIn, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(M1, K3, K4); + cscFwRGBtoYCbCr(M2, pCscFwReg->StandardOut, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(K4, M2, Kout); + } + + cscFwSetCoefficients(pCscFwReg, Kout, ClampMin, ClipMax); + cscUpdateIPReg(pCsc, pCscFwReg, UPD_REG_DEMO_WIN); +} + +/*****************************************************************************/ +/** +* This function set red gain to specified value. It also translates user +* setting of 0-100 to hw register range +* +* @param InstancePtr is pointer to csc core instance +* @param pCscFwReg is a pointer to layer 2 fw register bank +* @param val is new gain value +* +* @return None +* +******************************************************************************/ +void XV_CscSetRedGain(XV_csc *InstancePtr, XV_csc_L2Reg *pCscFwReg, s32 val) +{ + XV_csc *pCsc = InstancePtr; + s32 K1[3][4], K2[3][4]; + float red_f; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pCscFwReg != NULL); + + pCscFwReg->RedGain = (val*2+20); + red_f = (float)(pCscFwReg->RedGain)/(float)(pCscFwReg->RedGain_active); + + //get active coefficient set in RGB + cscFwGetActiveCoefficients(pCscFwReg, K1); + + K2[0][0] = (s32) ((float) K1[0][0] * red_f); + K2[0][1] = (s32) ((float) K1[0][1] * red_f); + K2[0][2] = (s32) ((float) K1[0][2] * red_f); + K2[1][0] = K1[1][0]; + K2[1][1] = K1[1][1]; + K2[1][2] = K1[1][2]; + K2[2][0] = K1[2][0]; + K2[2][1] = K1[2][1]; + K2[2][2] = K1[2][2]; + K2[0][3] = K1[0][3]; + K2[1][3] = K1[1][3]; + K2[2][3] = K1[2][3]; + + //write new active coefficient set in RGB + cscFwSetActiveCoefficients(pCscFwReg, K2); + //write new active red value + pCscFwReg->RedGain_active = pCscFwReg->RedGain; + + cscFwComputeCoeff(pCscFwReg, K2); + cscUpdateIPReg(pCsc, pCscFwReg, UPD_REG_DEMO_WIN); +} + +/*****************************************************************************/ +/** +* This function set green gain to specified value. It also translates user +* setting of 0-100 to hw register range +* +* @param InstancePtr is pointer to csc core instance +* @param pCscFwReg is a pointer to layer 2 fw register bank +* @param val is new gain value +* +* @return None +* +******************************************************************************/ +void XV_CscSetGreenGain(XV_csc *InstancePtr, XV_csc_L2Reg *pCscFwReg, s32 val) +{ + XV_csc *pCsc = InstancePtr; + s32 K1[3][4], K2[3][4]; + float green_f; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pCscFwReg != NULL); + + pCscFwReg->GreenGain = (val*2+20); + green_f = (float)(pCscFwReg->GreenGain)/(float)(pCscFwReg->GreenGain_active); + + //get active coefficient set in RGB + cscFwGetActiveCoefficients(pCscFwReg, K1); + + K2[0][0] = K1[0][0]; + K2[0][1] = K1[0][1]; + K2[0][2] = K1[0][2]; + K2[1][0] = (s32) ((float) K1[1][0] * green_f); + K2[1][1] = (s32) ((float) K1[1][1] * green_f); + K2[1][2] = (s32) ((float) K1[1][2] * green_f); + K2[2][0] = K1[2][0]; + K2[2][1] = K1[2][1]; + K2[2][2] = K1[2][2]; + K2[0][3] = K1[0][3]; + K2[1][3] = K1[1][3]; + K2[2][3] = K1[2][3]; + + //write new active coefficient set in RGB + cscFwSetActiveCoefficients(pCscFwReg, K2); + //write new active green value + pCscFwReg->GreenGain_active = pCscFwReg->GreenGain; + + cscFwComputeCoeff(pCscFwReg, K2); + cscUpdateIPReg(pCsc, pCscFwReg, UPD_REG_DEMO_WIN); +} + +/*****************************************************************************/ +/** +* This function set blue gain to specified value. It also translates user +* setting of 0-100 to hw register range +* +* @param InstancePtr is pointer to csc core instance +* @param pCscFwReg is a pointer to layer 2 fw register bank +* @param val is new gain value +* +* @return None +* +******************************************************************************/ +void XV_CscSetBlueGain(XV_csc *InstancePtr, XV_csc_L2Reg *pCscFwReg, s32 val) +{ + XV_csc *pCsc = InstancePtr; + s32 K1[3][4], K2[3][4]; + float blue_f; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pCscFwReg != NULL); + + pCscFwReg->BlueGain = (val*2+20); + blue_f = (float)(pCscFwReg->BlueGain)/(float)(pCscFwReg->BlueGain_active); + + //get active coefficient set in RGB + cscFwGetActiveCoefficients(pCscFwReg, K1); + + K2[0][0] = K1[0][0]; + K2[0][1] = K1[0][1]; + K2[0][2] = K1[0][2]; + K2[1][0] = K1[1][0]; + K2[1][1] = K1[1][1]; + K2[1][2] = K1[1][2]; + K2[2][0] = (s32) ((float) K1[2][0] * blue_f); + K2[2][1] = (s32) ((float) K1[2][1] * blue_f); + K2[2][2] = (s32) ((float) K1[2][2] * blue_f); + K2[0][3] = K1[0][3]; + K2[1][3] = K1[1][3]; + K2[2][3] = K1[2][3]; + + //write new active coefficient set in RGB + cscFwSetActiveCoefficients(pCscFwReg, K2); + //write new active blue value + pCscFwReg->BlueGain_active = pCscFwReg->BlueGain; + + cscFwComputeCoeff(pCscFwReg, K2); + cscUpdateIPReg(pCsc, pCscFwReg, UPD_REG_DEMO_WIN); +} + + +/*****************************************************************************/ +/** +* Compute the coefficients for the required color space and write to layer 2 +* fw register bank +* +* @param pCscFwReg is a pointer to layer 2 fw register bank +* @param K2 is the active coefficients +* +* @return None +* +******************************************************************************/ +static void cscFwComputeCoeff(XV_csc_L2Reg *pCscFwReg, + s32 K2[3][4]) +{ + u32 x,y; + s32 K3[3][4], M1[3][4], M2[3][4], Kout[3][4];; + s32 ClampMin = 0; + s32 ClipMax = ((1<ColorDepth)-1); + + if((pCscFwReg->ColorFormatIn == XVIDC_CSF_RGB) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_RGB) ) + { + for (x=0; x<3; x++) for (y=0; y<4; y++) + Kout[x][y] = K2[x][y]; + } + + if ((pCscFwReg->ColorFormatIn == XVIDC_CSF_RGB) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_YCRCB_444) ) + { + cscFwRGBtoYCbCr(M2, pCscFwReg->StandardOut, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(K2, M2, Kout); + } + + if ((pCscFwReg->ColorFormatIn == XVIDC_CSF_YCRCB_444) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_RGB) ) + { + cscFwYCbCrtoRGB(M1, pCscFwReg->StandardIn, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(M1, K2, Kout); + } + + if (((pCscFwReg->ColorFormatIn == XVIDC_CSF_YCRCB_444) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_YCRCB_444)) || + ((pCscFwReg->ColorFormatIn == XVIDC_CSF_YCRCB_422) && + (pCscFwReg->ColorFormatOut == XVIDC_CSF_YCRCB_422))) + { + cscFwYCbCrtoRGB(M1, pCscFwReg->StandardIn, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(M1, K2, K3); + cscFwRGBtoYCbCr(M2, pCscFwReg->StandardOut, pCscFwReg->ColorDepth, &ClampMin, &ClipMax); + cscFwMatrixMult(K3, M2, Kout); + } + cscFwSetCoefficients(pCscFwReg, Kout, ClampMin, ClipMax); +} + +/*****************************************************************************/ +/** +* This function multiplies Matrices. (Utility function) +* +* @param K1 input matrix +* @param K2 input matrix +* @param Kout is the output matrix (K1 * K2) +* +* @return Matrix multiplication via Kout +* +******************************************************************************/ +static void cscFwMatrixMult(s32 K1[3][4], s32 K2[3][4], s32 Kout[3][4]) +{ + + s32 A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T,U,V,W,X; + s32 scale_factor = (1<CSC IP STATUS<----\r\n"); + + done = XV_csc_IsDone(pCsc); + idle = XV_csc_IsIdle(pCsc); + ready = XV_csc_IsReady(pCsc); + ctrl = XV_csc_ReadReg(pCsc->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL); + + colstart = XV_csc_Get_HwReg_ColStart(pCsc); + colend = XV_csc_Get_HwReg_ColEnd(pCsc); + rowstart = XV_csc_Get_HwReg_RowStart(pCsc); + rowend = XV_csc_Get_HwReg_RowEnd(pCsc); + offset_r = XV_csc_Get_HwReg_ROffset_V(pCsc); + offset_g = XV_csc_Get_HwReg_GOffset_V(pCsc); + offset_b = XV_csc_Get_HwReg_BOffset_V(pCsc); + minclamp = XV_csc_Get_HwReg_ClampMin_V(pCsc); + maxclamp = XV_csc_Get_HwReg_ClipMax_V(pCsc); + height = XV_csc_Get_HwReg_height(pCsc); + width = XV_csc_Get_HwReg_width(pCsc); + + coeff[0][0] = XV_csc_Get_HwReg_K11_2(pCsc); + coeff[0][1] = XV_csc_Get_HwReg_K12_2(pCsc); + coeff[0][2] = XV_csc_Get_HwReg_K13_2(pCsc); + coeff[1][0] = XV_csc_Get_HwReg_K21_2(pCsc); + coeff[1][1] = XV_csc_Get_HwReg_K22_2(pCsc); + coeff[1][2] = XV_csc_Get_HwReg_K23_2(pCsc); + coeff[2][0] = XV_csc_Get_HwReg_K31_2(pCsc); + coeff[2][1] = XV_csc_Get_HwReg_K32_2(pCsc); + coeff[2][2] = XV_csc_Get_HwReg_K33_2(pCsc); + + xil_printf("IsDone: %d\r\n", done); + xil_printf("IsIdle: %d\r\n", idle); + xil_printf("IsReady: %d\r\n", ready); + xil_printf("Ctrl: 0x%x\r\n\r\n", ctrl); + + xil_printf("Color Format In: %s\r\n", + XVidC_GetColorFormatStr(XV_csc_Get_HwReg_InVideoFormat(pCsc))); + xil_printf("Color Format Out: %s\r\n", + XVidC_GetColorFormatStr(XV_csc_Get_HwReg_OutVideoFormat(pCsc))); + xil_printf("Column Start: %d\r\n",colstart); + xil_printf("Column End: %d\r\n",colend); + xil_printf("Row Start: %d\r\n",rowstart); + xil_printf("Row End: %d\r\n",rowend); + xil_printf("R Offset: %d\r\n",offset_r); + xil_printf("G Offset: %d\r\n",offset_g); + xil_printf("B Offset: %d\r\n",offset_b); + xil_printf("Min Clamp: %d\r\n",minclamp); + xil_printf("Max Clamp: %d\r\n",maxclamp); + xil_printf("Active Width: %d\r\n",width); + xil_printf("Active Height: %d\r\n",height); + + xil_printf("\r\nCoefficients:",height); + for(i=0; i<3; ++i) + { + xil_printf("\r\n r%d: ",i); + for(j=0; j<3; ++j) + { + xil_printf("%4d ",coeff[i][j]); + } + } +} diff --git a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.h b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.h new file mode 100644 index 00000000..fd9720a2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.h @@ -0,0 +1,397 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xv_csc_l2.h +* +* This header file contains layer 2 API's of the csc sub-core driver. +* The functions contained herein provides a high level implementation of features +* provided by the IP, abstracting away the register level details from +* the user +* +* Color Space Converter IP Features +* +* The CSC IP supports following features +* - Set a Demo Window (user can select a sub-frame where above features +* will have effect) +* - Supports resolution up to 4k2k 60Hz +* - up to 16 bits color depth +* - 1, 2 or 4 pixel per clock processing +* +* The Layer 2 driver of Color Space Conversion core offers following features +* - Set/Get Brightness, contrast, saturation +* - Set/Get Gain for R/G/B channel +* - Set/Get Input/Output Color Standard (BT601, BT709, BT2020) +* - Set/Get Input/Output Color Format (RGB, YUV444, YUV422) +* - All settings are translated between user range (0-100) and IP supported +* range +* +* Dependency +* +* This driver makes use of the video enumerations and data types defined in the +* Xilinx Video Common Driver (video_common_vX.x) and as such the common driver +* must be included as dependency to compile this driver +* +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CSC core. +* +* Before using the layer-2 API's user must initialize the core by calling +* Layer-1 API XV_csc_Initialize(). This function will look for a configuration +* structure for the device and initialize it to defined HW settings. After +* initialization Layer-2 API's can be used to configure the core. It is +* recommended user always make use of Layer-2 API to interact with the core +* Advanced users always have the capability to directly interact with the +* core using Layer-1 API's that perform low level register peek/poke. +* +* Interrupts +* +* This driver does not have any interrupts +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  rc   05/01/15   Initial Release
+
+*
+* +******************************************************************************/ +#ifndef XV_CSC_L2_H /* prevent circular inclusions */ +#define XV_CSC_L2_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xvidc.h" +#include "xv_csc.h" + + +/****************************** Type Definitions ******************************/ +/** + * CSC Layer 2 Register Map. Each instance of the csc core will have it's own + * register map + */ +typedef enum +{ + CSC_FW_REG_ColStart = 0, + CSC_FW_REG_ColEnd, + CSC_FW_REG_RowStart, + CSC_FW_REG_RowEnd, + CSC_FW_REG_K11, + CSC_FW_REG_K12, + CSC_FW_REG_K13, + CSC_FW_REG_K21, + CSC_FW_REG_K22, + CSC_FW_REG_K23, + CSC_FW_REG_K31, + CSC_FW_REG_K32, + CSC_FW_REG_K33, + CSC_FW_REG_ROffset, + CSC_FW_REG_GOffset, + CSC_FW_REG_BOffset, + CSC_FW_REG_ClampMin, + CSC_FW_REG_ClipMax, + CSC_FW_REG_K11_2, + CSC_FW_REG_K12_2, + CSC_FW_REG_K13_2, + CSC_FW_REG_K21_2, + CSC_FW_REG_K22_2, + CSC_FW_REG_K23_2, + CSC_FW_REG_K31_2, + CSC_FW_REG_K32_2, + CSC_FW_REG_K33_2, + CSC_FW_REG_ROffset_2, + CSC_FW_REG_GOffset_2, + CSC_FW_REG_BOffset_2, + CSC_FW_REG_ClampMin_2, + CSC_FW_REG_ClipMax_2, + CSC_FW_NUM_REGS +}XV_CSC_FW_REG_MMAP; + +/** + * This typedef contains the layer 2 register map for a given + * instance of the csc core. + */ +typedef struct +{ + XVidC_ColorFormat ColorFormatIn; + XVidC_ColorFormat ColorFormatOut; + XVidC_ColorStd StandardIn; + XVidC_ColorStd StandardOut; + XVidC_ColorRange OutputRange; + XVidC_ColorDepth ColorDepth; + s32 Brightness; + s32 Contrast; + s32 Saturation; + s32 RedGain; + s32 GreenGain; + s32 BlueGain; + s32 Brightness_active; + s32 Contrast_active; + s32 Saturation_active; + s32 RedGain_active; + s32 GreenGain_active; + s32 BlueGain_active; + s32 K_active[3][4]; + + s32 regMap[CSC_FW_NUM_REGS]; +}XV_csc_L2Reg; + +/************************** Macros Definitions *******************************/ +/*****************************************************************************/ +/** +* This macro sets color depth for CSC core +* +* @param pCscFwReg is a pointer to csc layer 2 fw register map +* @param val is the requested color depth +* +* @return None +* +******************************************************************************/ +#define XV_CscSetColorDepth(pCscFwReg, val) ((pCscFwReg)->ColorDepth = val) + +/*****************************************************************************/ +/** +* This macro returns current brightness setting by reading layer 2 fw register +* map. It also translates between hw register value and user view +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return current user view value (0-100) +* +******************************************************************************/ +#define XV_CscGetBrightness(pCscFwReg) (((pCscFwReg)->Brightness-20)/2) + +/*****************************************************************************/ +/** +* This macro returns current contrast setting by reading layer 2 fw register +* map. It also translates between hw register value and user view +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return current user view value (0-100) +* +******************************************************************************/ +#define XV_CscGetContrast(pCscFwReg) (((pCscFwReg)->Contrast+200)/4) + +/*****************************************************************************/ +/** +* This macro returns current saturation setting by reading layer 2 fw register +* map. It also translates between hw register value and user view +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return current user view value (0-100) +* +******************************************************************************/ +#define XV_CscGetSaturation(pCscFwReg) (((pCscFwReg)->Saturation/2)) + +/*****************************************************************************/ +/** +* This macro returns current red gain setting by reading layer 2 fw register +* map. It also translates between hw register value and user view +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return current user view value (0-100) +* +******************************************************************************/ +#define XV_CscGetRedGain(pCscFwReg) (((pCscFwReg)->RedGain-20)/2) + +/*****************************************************************************/ +/** +* This macro returns current green gain setting by reading layer 2 fw register +* map. It also translates between hw register value and user view +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return current user view value (0-100) +* +******************************************************************************/ +#define XV_CscGetGreenGain(pCscFwReg) (((pCscFwReg)->GreenGain-20)/2) + +/*****************************************************************************/ +/** +* This macro returns current blue gain setting by reading layer 2 fw register +* map. It also translates between hw register value and user view +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return current user view value (0-100) +* +******************************************************************************/ +#define XV_CscGetBlueGain(pCscFwReg) (((pCscFwReg)->BlueGain-20)/2) + +/*****************************************************************************/ +/** +* This macro returns current set input color format by reading layer 2 fw +* register map. +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return Current set input color format +* - XVIDC_CSF_RGB +* - XVIDC_CSF_YCRCB_444 +* - XVIDC_CSF_YCRCB_422 +* +******************************************************************************/ +#define XV_CscGetColorFormatIn(pCscFwReg) ((pCscFwReg)->ColorFormatIn) + +/*****************************************************************************/ +/** +* This macro returns current set output color format by reading layer 2 fw +* register map. +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return Current set output color format +* - XVIDC_CSF_RGB +* - XVIDC_CSF_YCRCB_444 +* - XVIDC_CSF_YCRCB_422 +* +******************************************************************************/ +#define XV_CscGetColorFormatOut(pCscFwReg) ((pCscFwReg)->ColorFormatOut) + +/*****************************************************************************/ +/** +* This macro returns current set input color standard by reading layer 2 fw +* register map. +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return Current set input color standard +* - XVIDC_BT_2020 +* - XVIDC_BT_709 +* - XVIDC_BT_601 +* +******************************************************************************/ +#define XV_CscGetColorStdIn(pCscFwReg) ((pCscFwReg)->StandardIn) + +/*****************************************************************************/ +/** +* This macro returns current set output color standard by reading layer 2 fw +* register map. +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return Current set output color standard +* - XVIDC_BT_2020 +* - XVIDC_BT_709 +* - XVIDC_BT_601 +* +*****************************************************************************/ +#define XV_CscGetColorStdOut(pCscFwReg) ((pCscFwReg)->StandardOut) + +/*****************************************************************************/ +/** +* This macro returns current set output range by reading layer 2 fw register +* map. +* +* @param pCscFwReg is pointer to csc fw register associated with csc core +* instance +* +* @return Current set output range +* - XVIDC_CR_16_235 +* - XVIDC_CR_16_240 +* - XVIDC_CR_0_255 +* +******************************************************************************/ +#define XV_CscGetOutputRange(pCscFwReg) ((pCscFwReg)->OutputRange) + +/************************** Function Prototypes ******************************/ +void XV_CscStart(XV_csc *InstancePtr); +void XV_CscStop(XV_csc *InstancePtr); +void XV_CscSetActiveSize(XV_csc *InstancePtr, + u32 width, + u32 height); +void XV_CscSetDemoWindow(XV_csc *InstancePtr, XVidC_VideoWindow *ActiveWindow); + +void XV_CscSetColorspace(XV_csc *InstancePtr, + XV_csc_L2Reg *pCscFwReg, + XVidC_ColorFormat cfmtIn, + XVidC_ColorFormat cfmtOut, + XVidC_ColorStd cstdIn, + XVidC_ColorStd cstdOut, + XVidC_ColorRange cRangeOut + ); + +void XV_CscInitPowerOnDefault(XV_csc_L2Reg *pCscFwReg); +void XV_CscSetBrightness(XV_csc *InstancePtr, + XV_csc_L2Reg *pCscFwReg, + s32 val); +void XV_CscSetContrast(XV_csc *InstancePtr, + XV_csc_L2Reg *pCscFwReg, + s32 val); +void XV_CscSetSaturation(XV_csc *InstancePtr, + XV_csc_L2Reg *pCscFwReg, + s32 val); +void XV_CscSetRedGain(XV_csc *InstancePtr, + XV_csc_L2Reg *pCscFwReg, + s32 val); +void XV_CscSetGreenGain(XV_csc *InstancePtr, + XV_csc_L2Reg *pCscFwReg, + s32 val); +void XV_CscSetBlueGain(XV_csc *InstancePtr, + XV_csc_L2Reg *pCscFwReg, + s32 val); +void XV_CscDbgReportStatus(XV_csc *InstancePtr); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_linux.c b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_linux.c new file mode 100644 index 00000000..992fd047 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_linux.c @@ -0,0 +1,150 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifdef __linux__ + +/***************************** Include Files *********************************/ +#include "xv_csc.h" + +/***************** Macros (Inline Functions) Definitions *********************/ +#define MAX_UIO_PATH_SIZE 256 +#define MAX_UIO_NAME_SIZE 64 +#define MAX_UIO_MAPS 5 +#define UIO_INVALID_ADDR 0 + +/**************************** Type Definitions ******************************/ +typedef struct { + u32 addr; + u32 size; +} XV_csc_uio_map; + +typedef struct { + int uio_fd; + int uio_num; + char name[ MAX_UIO_NAME_SIZE ]; + char version[ MAX_UIO_NAME_SIZE ]; + XV_csc_uio_map maps[ MAX_UIO_MAPS ]; +} XV_csc_uio_info; + +/***************** Variable Definitions **************************************/ +static XV_csc_uio_info uio_info; + +/************************** Function Implementation *************************/ +static int line_from_file(char* filename, char* linebuf) { + char* s; + int i; + FILE* fp = fopen(filename, "r"); + if (!fp) return -1; + s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp); + fclose(fp); + if (!s) return -2; + for (i=0; (*s)&&(iuio_num); + return line_from_file(file, info->name); +} + +static int uio_info_read_version(XV_csc_uio_info* info) { + char file[ MAX_UIO_PATH_SIZE ]; + sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num); + return line_from_file(file, info->version); +} + +static int uio_info_read_map_addr(XV_csc_uio_info* info, int n) { + int ret; + char file[ MAX_UIO_PATH_SIZE ]; + info->maps[n].addr = UIO_INVALID_ADDR; + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n); + FILE* fp = fopen(file, "r"); + if (!fp) return -1; + ret = fscanf(fp, "0x%x", &info->maps[n].addr); + fclose(fp); + if (ret < 0) return -2; + return 0; +} + +static int uio_info_read_map_size(XV_csc_uio_info* info, int n) { + int ret; + char file[ MAX_UIO_PATH_SIZE ]; + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n); + FILE* fp = fopen(file, "r"); + if (!fp) return -1; + ret = fscanf(fp, "0x%x", &info->maps[n].size); + fclose(fp); + if (ret < 0) return -2; + return 0; +} + +int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName) { + XV_csc_uio_info *InfoPtr = &uio_info; + struct dirent **namelist; + int i, n; + char* s; + char file[ MAX_UIO_PATH_SIZE ]; + char name[ MAX_UIO_NAME_SIZE ]; + int flag = 0; + + assert(InstancePtr != NULL); + + n = scandir("/sys/class/uio", &namelist, 0, alphasort); + if (n < 0) return XST_DEVICE_NOT_FOUND; + for (i = 0; i < n; i++) { + strcpy(file, "/sys/class/uio/"); + strcat(file, namelist[i]->d_name); + strcat(file, "/name"); + if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) { + flag = 1; + s = namelist[i]->d_name; + s += 3; // "uio" + InfoPtr->uio_num = atoi(s); + break; + } + } + if (flag == 0) return XST_DEVICE_NOT_FOUND; + + uio_info_read_name(InfoPtr); + uio_info_read_version(InfoPtr); + for (n = 0; n < MAX_UIO_MAPS; ++n) { + uio_info_read_map_addr(InfoPtr, n); + uio_info_read_map_size(InfoPtr, n); + } + + sprintf(file, "/dev/uio%d", InfoPtr->uio_num); + if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) { + return XST_OPEN_DEVICE_FAILED; + } + + // NOTE: slave interface 'Ctrl' should be mapped to uioX/map0 + InstancePtr->Ctrl_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize()); + assert(InstancePtr->Ctrl_BaseAddress); + + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} + +int XV_csc_Release(XV_csc *InstancePtr) { + XV_csc_uio_info *InfoPtr = &uio_info; + + assert(InstancePtr != NULL); + assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + munmap((void*)InstancePtr->Ctrl_BaseAddress, InfoPtr->maps[0].size); + + close(InfoPtr->uio_fd); + + return XST_SUCCESS; +} + +#endif diff --git a/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_sinit.c b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_sinit.c new file mode 100644 index 00000000..0af560e9 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_sinit.c @@ -0,0 +1,45 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifndef __linux__ + +#include "xstatus.h" +#include "xparameters.h" +#include "xv_csc.h" + +extern XV_csc_Config XV_csc_ConfigTable[]; + +XV_csc_Config *XV_csc_LookupConfig(u16 DeviceId) { + XV_csc_Config *ConfigPtr = NULL; + + int Index; + + for (Index = 0; Index < XPAR_XV_CSC_NUM_INSTANCES; Index++) { + if (XV_csc_ConfigTable[Index].DeviceId == DeviceId) { + ConfigPtr = &XV_csc_ConfigTable[Index]; + break; + } + } + + return ConfigPtr; +} + +int XV_csc_Initialize(XV_csc *InstancePtr, u16 DeviceId) { + XV_csc_Config *ConfigPtr; + + Xil_AssertNonvoid(InstancePtr != NULL); + + ConfigPtr = XV_csc_LookupConfig(DeviceId); + if (ConfigPtr == NULL) { + InstancePtr->IsReady = 0; + return (XST_DEVICE_NOT_FOUND); + } + + return XV_csc_CfgInitialize(InstancePtr, ConfigPtr); +} + +#endif