From cbbf0e86d7d855e784b65e664fbb1b5249107bd8 Mon Sep 17 00:00:00 2001 From: Anirudha Sarangi Date: Sun, 18 Oct 2015 02:48:24 +0530 Subject: [PATCH] standalone BSP: Disable TCM ECC checks in boot code It is observed that when the C stack in put in TCM, ECC errors get reported resulting in data abort. This patch disables TCM ECC check temporarily before we come to a proper conclusion regarding how to handle this use case. Since we expect users to run code in R5 TCM, this patch removed ECC check for TCMs to avoid data aborts. Signed-off-by: Anirudha Sarangi Acked by: Kinjal Pravinbhai Patel --- lib/bsp/standalone/src/cortexr5/gcc/boot.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/bsp/standalone/src/cortexr5/gcc/boot.S b/lib/bsp/standalone/src/cortexr5/gcc/boot.S index 944236f4..1c52614b 100644 --- a/lib/bsp/standalone/src/cortexr5/gcc/boot.S +++ b/lib/bsp/standalone/src/cortexr5/gcc/boot.S @@ -108,11 +108,14 @@ OKToRun: mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */ isb /* Ensure subsequent insts execute wrt new MPU settings */ -/* Disable Branch prediction */ +/* Disable Branch prediction, TCM ECC checks */ mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */ orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */ orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/ bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/ + bic r0, r0, #(0x1 << 27) /* Disable B1TCM ECC check */ + bic r0, r0, #(0x1 << 26) /* Disable B0TCM ECC check */ + bic r0, r0, #(0x1 << 25) /* Disable ATCM ECC check */ mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ dsb /* Complete all outstanding explicit memory operations*/