diff --git a/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c b/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
index d632832b..3861db64 100644
--- a/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
+++ b/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
@@ -51,6 +51,7 @@
 * 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
 *                    Disable extended mode. Perform all 64 bit changes under
 *                    check for arch64.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
 *
 * </pre>
 ******************************************************************************/
@@ -470,10 +471,17 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
 			(QPtr & ULONG64_LO_MASK));
 	}
 #ifdef __aarch64__
-	/* Set the MSB of Queue start address */
-	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
-			XEMACPS_MSBBUF_QBASE_OFFSET,
-			(u32)((QPtr & (u32)ULONG64_HI_MASK) >> 32U));
+	if (Direction == XEMACPS_SEND) {
+		/* Set the MSB of TX Queue start address */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_MSBBUF_TXQBASE_OFFSET,
+				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+	} else {
+		/* Set the MSB of RX Queue start address */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_MSBBUF_RXQBASE_OFFSET,
+				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+	}
 #endif
 }
 /** @} */
diff --git a/XilinxProcessorIPLib/drivers/emacps/src/xemacps.h b/XilinxProcessorIPLib/drivers/emacps/src/xemacps.h
index 7c158187..bf687b77 100644
--- a/XilinxProcessorIPLib/drivers/emacps/src/xemacps.h
+++ b/XilinxProcessorIPLib/drivers/emacps/src/xemacps.h
@@ -314,6 +314,7 @@
  *                     Remove "used bit set" from TX error interrupt masks.
  * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
  *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
  * </pre>
  *
  ****************************************************************************/
diff --git a/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h b/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
index fbcd2da4..a53527c7 100644
--- a/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
+++ b/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
@@ -59,6 +59,7 @@
 * 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.0  hk   03/18/15 Added support for jumbo frames.
 *                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
 * </pre>
 *
 ******************************************************************************/
@@ -300,7 +301,9 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 							reg */
 #define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
 							reg */
-#define XEMACPS_MSBBUF_QBASE_OFFSET  0x000004C8U /**< MSB Buffer Q Base
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
+							reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
 							reg */
 #define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
 							reg */