From d29d6bdcd053ef0df37c035ba2f96b6d3032939b Mon Sep 17 00:00:00 2001 From: RamyaSree Date: Tue, 13 Oct 2015 20:44:05 +0530 Subject: [PATCH] sw_apps:zynqmp_fsbl: Modified PMU Trigger logic This patch corrects the logic used to trigger PMU_0 IPI. Also added code to Enable PMU_0 IPI. Signed-off-by: RamyaSree Acked-by: Sarat Chand Savitala --- lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h | 5 ++++- lib/sw_apps/zynqmp_fsbl/src/xfsbl_partition_load.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h index 67d6e0a4..48bdb867 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h @@ -470,7 +470,10 @@ extern "C" { /* Register: IPI_PMU_0_TRIG */ #define IPI_PMU_0_TRIG ( ( IPI_BASEADDR ) + 0X00030000U ) -#define IPI_APU_TRIG_PMU_0_SHIFT 16U +#define IPI_PMU_0_TRIG_PMU_0_MASK 0X00010000U + +#define IPI_PMU_0_IER ( ( IPI_BASEADDR ) + 0X00030018U ) +#define IPI_PMU_0_IER_PMU_0_MASK 0X00010000U /**************************** Type Definitions *******************************/ diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_partition_load.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_partition_load.c index 922b56b8..6ce18ee5 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_partition_load.c +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_partition_load.c @@ -907,8 +907,11 @@ static u32 XFsbl_PartitionCopy(XFsblPs * FsblInstancePtr, u32 PartitionNum) if (DestinationDevice == XIH_PH_ATTRB_DEST_DEVICE_PMU) { + /* Enable PMU_0 IPI */ + XFsbl_Out32(IPI_PMU_0_IER, IPI_PMU_0_IER_PMU_0_MASK); + /* Trigger PMU0 IPI in PMU IPI TRIG Reg */ - XFsbl_Out32(IPI_PMU_0_TRIG, IPI_APU_TRIG_PMU_0_SHIFT); + XFsbl_Out32(IPI_PMU_0_TRIG, IPI_PMU_0_TRIG_PMU_0_MASK); /** * Wait until PMU Microblaze goes to sleep state,