From d7e056eb66d38968b87e2b81b1ba903df9a5efdd Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Tue, 24 Feb 2015 16:31:05 -0800 Subject: [PATCH] dptx: Handle new PHY_CONFIG bit for 8b10b encoding. Bit 21 of DPTX register PHY_CONFIG (0x200) enables 8b10b encoding. In v6.0 of the DPTX core, the default value is '1'. Current driver should keep this value untouched when writing to the PHY_CONFIG register. Signed-off-by: Andrei-Liviu Simion --- XilinxProcessorIPLib/drivers/dptx/src/xdptx.c | 29 ++++++++++++++----- .../drivers/dptx/src/xdptx_hw.h | 25 ++++++++++++++-- 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c index 81b832ab..951d37f4 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c @@ -162,6 +162,7 @@ static u32 XDptx_WaitPhyReady(XDptx *InstancePtr); u32 XDptx_InitializeTx(XDptx *InstancePtr) { u32 Status; + u32 PhyVal; u32 RegVal; XDptx_Config *Config = &InstancePtr->Config; @@ -169,9 +170,12 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + /* Preserve the current PHY settings. */ + PhyVal = XDptx_ReadReg(Config->BaseAddr, XDPTX_PHY_CONFIG); + /* Place the PHY (and GTTXRESET) into reset. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG, - XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK); + RegVal = PhyVal | XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK; + XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG, RegVal); /* Reset the video streams and AUX logic. */ XDptx_WriteReg(Config->BaseAddr, XDPTX_SOFT_RESET, @@ -206,8 +210,8 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr) } /* Bring the PHY (and GTTXRESET) out of reset. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG, - XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); + RegVal = PhyVal & ~XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK; + XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG, RegVal); /* Wait for the PHY to be ready. */ Status = XDptx_WaitPhyReady(InstancePtr); @@ -1306,15 +1310,26 @@ void XDptx_DisableMainLink(XDptx *InstancePtr) *******************************************************************************/ void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset) { + u32 PhyVal; + u32 RegVal; + /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x0); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, Reset); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, - XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); + /* Preserve the current PHY settings. */ + PhyVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG); + + /* Apply reset. */ + RegVal = PhyVal | Reset; + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, RegVal); + + /* Remove the reset. */ + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, PhyVal); + + /* Wait for the PHY to be ready. */ XDptx_WaitPhyReady(InstancePtr); XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x1); diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h index c48f9e09..bca47d73 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h @@ -627,15 +627,34 @@ #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK \ 0x0000100 /**< Hold TX_PHY_PMA reset. */ #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \ - 0x0000200 /**< HOLD TX_PHY_PCS reset. */ + 0x0000200 /**< Hold TX_PHY_PCS reset. */ #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK \ - 0x0000400 /**< Set TX_PHY_POLARITY. */ + 0x0000800 /**< Set TX_PHY_POLARITY. */ #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \ 0x0001000 /**< Set TX_PHY_PRBSFORCEERR. */ #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK \ 0x000E000 /**< Set TX_PHY_LOOPBACK. */ +#define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 /**< Shift bits for + TX_PHY_LOOPBACK. */ +#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK \ + 0x0010000 /**< Set to enable individual + lane polarity. */ +#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK \ + 0x0020000 /**< Set TX_PHY_POLARITY for + lane 0. */ +#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK \ + 0x0040000 /**< Set TX_PHY_POLARITY for + lane 1. */ +#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK \ + 0x0080000 /**< Set TX_PHY_POLARITY for + lane 2. */ +#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK \ + 0x0100000 /**< Set TX_PHY_POLARITY for + lane 3. */ +#define XDPTX_PHY_CONFIG_TX_PHY_8B10BEN_MASK \ + 0x0200000 /**< 8B10B encoding enable. */ #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK \ - 0x0000003 /**< Rest GT and PHY. */ + 0x0000003 /**< Reset GT and PHY. */ /* 0x234: PHY_CLOCK_SELECT */ #define XDPTX_PHY_CLOCK_SELECT_162GBPS 0x1 /**< 1.62 Gbps link. */ #define XDPTX_PHY_CLOCK_SELECT_270GBPS 0x3 /**< 2.70 Gbps link. */