From d94ec8f60e307b40168de3eb5508de255cb44e15 Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Wed, 7 Jan 2015 16:06:32 -0800 Subject: [PATCH] dptx: Updated Doxygen documentation. Signed-off-by: Andrei-Liviu Simion --- .../drivers/dptx/doc/html/api/annotated.html | 1 - .../drivers/dptx/doc/html/api/files.html | 1 - .../drivers/dptx/doc/html/api/functions.html | 236 +- .../dptx/doc/html/api/functions_vars.html | 236 +- .../drivers/dptx/doc/html/api/globals.html | 2 +- .../dptx/doc/html/api/globals_0x72.html | 4 +- .../dptx/doc/html/api/globals_0x78.html | 1505 ++++---- .../dptx/doc/html/api/globals_defs.html | 1237 +++---- .../dptx/doc/html/api/globals_enum.html | 3 +- .../dptx/doc/html/api/globals_eval.html | 109 +- .../dptx/doc/html/api/globals_func.html | 156 +- .../dptx/doc/html/api/globals_type.html | 6 +- .../dptx/doc/html/api/globals_vars.html | 9 +- .../drivers/dptx/doc/html/api/index.html | 52 +- .../doc/html/api/struct_x_dptx-members.html | 36 +- .../dptx/doc/html/api/struct_x_dptx.html | 142 +- ...ruct_x_dptx___aux_transaction-members.html | 8 +- .../api/struct_x_dptx___aux_transaction.html | 30 +- .../struct_x_dptx___board_char-members.html | 8 +- .../html/api/struct_x_dptx___board_char.html | 30 +- .../api/struct_x_dptx___config-members.html | 32 +- .../doc/html/api/struct_x_dptx___config.html | 126 +- .../struct_x_dptx___link_config-members.html | 24 +- .../html/api/struct_x_dptx___link_config.html | 94 +- ...dptx___main_stream_attributes-members.html | 38 +- ...truct_x_dptx___main_stream_attributes.html | 150 +- .../struct_x_dptx___mst_stream-members.html | 8 +- .../html/api/struct_x_dptx___mst_stream.html | 28 +- ...ink_address_reply_device_info-members.html | 10 +- ...sb_msg_link_address_reply_device_info.html | 38 +- ...ink_address_reply_port_detail-members.html | 20 +- ...sb_msg_link_address_reply_port_detail.html | 78 +- .../struct_x_dptx___sideband_msg-members.html | 4 +- .../api/struct_x_dptx___sideband_msg.html | 14 +- ...ct_x_dptx___sideband_msg_body-members.html | 6 +- .../struct_x_dptx___sideband_msg_body.html | 22 +- ..._x_dptx___sideband_msg_header-members.html | 22 +- .../struct_x_dptx___sideband_msg_header.html | 86 +- ...truct_x_dptx___sideband_reply-members.html | 4 +- .../api/struct_x_dptx___sideband_reply.html | 14 +- .../struct_x_dptx___sink_config-members.html | 4 +- .../html/api/struct_x_dptx___sink_config.html | 14 +- .../api/struct_x_dptx___topology-members.html | 8 +- .../html/api/struct_x_dptx___topology.html | 30 +- ...struct_x_dptx___topology_node-members.html | 12 +- .../api/struct_x_dptx___topology_node.html | 46 +- .../drivers/dptx/doc/html/api/xdptx_8c.html | 162 +- .../drivers/dptx/doc/html/api/xdptx_8h.html | 740 ++-- .../dptx/doc/html/api/xdptx__edid_8c.html | 28 +- .../dptx/doc/html/api/xdptx__hw_8h.html | 3100 +++++++++-------- .../dptx/doc/html/api/xdptx__intr_8c.html | 20 +- .../dptx/doc/html/api/xdptx__mst_8c.html | 148 +- .../dptx/doc/html/api/xdptx__selftest_8c.html | 63 +- .../dptx/doc/html/api/xdptx__sinit_8c.html | 10 +- .../dptx/doc/html/api/xdptx__spm_8c.html | 42 +- 55 files changed, 4282 insertions(+), 4774 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/annotated.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/annotated.html index 65f55e42..2a371ea9 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/annotated.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/annotated.html @@ -26,7 +26,6 @@ XDptx_AuxTransaction XDptx_BoardChar XDptx_Config - XDptx_DmtMode XDptx_LinkConfig XDptx_MainStreamAttributes XDptx_MstStream diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/files.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/files.html index 727ff05a..fef3c07c 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/files.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/files.html @@ -31,6 +31,5 @@ xdptx_selftest.c xdptx_sinit.c xdptx_spm.c - xdptx_vidmodetable.c Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html index 15431379..58437d3f 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html @@ -57,166 +57,152 @@ Here is a list of all class members with links to the classes they belong to:

- a -

+: XDptx_AuxTransaction
  • AuxDelayUs +: XDptx
  • AvgBytesPerTU +: XDptx_MainStreamAttributes

    - b -

    +: XDptx_Config
  • BitsPerColor +: XDptx_MainStreamAttributes
  • BoardChar +: XDptx
  • Body +: XDptx_SidebandMsg
  • BroadcastMsg +: XDptx_SidebandMsgHeader

    - c -

    +: XDptx_AuxTransaction
  • ComponentFormat +: XDptx_MainStreamAttributes
  • Config +: XDptx
  • Crc +: XDptx_SidebandMsgBody, XDptx_SidebandMsgHeader

    - d -

    +: XDptx_SidebandReply, XDptx_AuxTransaction
  • DataPerLane +: XDptx_MainStreamAttributes
  • DeviceId +: XDptx_Config
  • DeviceType +: XDptx_TopologyNode
  • DownspreadControl +: XDptx_LinkConfig
  • DpcdRev +: XDptx_SbMsgLinkAddressReplyPortDetail, XDptx_TopologyNode
  • DpcdRxCapsField +: XDptx_SinkConfig
  • DpDevPlugStatus +: XDptx_SbMsgLinkAddressReplyPortDetail
  • DpProtocol +: XDptx_Config
  • DualPixelEn +: XDptx_Config
  • DynamicRange +: XDptx_MainStreamAttributes

    - e -

    +: XDptx_SidebandMsgHeader
  • EnhancedFramingMode +: XDptx_LinkConfig

    - g -

    +: XDptx_SbMsgLinkAddressReplyDeviceInfo, XDptx_SbMsgLinkAddressReplyPortDetail, XDptx_TopologyNode

    - h -

    +: XDptx_BoardChar
  • HClkTotal +: XDptx_MainStreamAttributes
  • Header +: XDptx_SidebandMsg
  • HpdEventCallbackRef +: XDptx
  • HpdEventHandler +: XDptx
  • HpdPulseCallbackRef +: XDptx
  • HpdPulseHandler +: XDptx
  • HStart +: XDptx_MainStreamAttributes

    - i -

    +: XDptx_MainStreamAttributes
  • InputPort +: XDptx_SbMsgLinkAddressReplyPortDetail
  • IsReady +: XDptx

    - l -

    +: XDptx_LinkConfig
  • LaneStatusAdjReqs +: XDptx_SinkConfig
  • LegacyDevPlugStatus +: XDptx_SbMsgLinkAddressReplyPortDetail
  • Length +: XDptx_SidebandReply
  • LinkConfig +: XDptx
  • LinkCountRemaining +: XDptx_SidebandMsgHeader
  • LinkCountTotal +: XDptx_SidebandMsgHeader, XDptx_TopologyNode, XDptx_MstStream
  • LinkRate +: XDptx_LinkConfig

    - m -

    +: XDptx_Config
  • MaxLaneCount +: XDptx_LinkConfig, XDptx_Config
  • MaxLinkRate +: XDptx_LinkConfig, XDptx_Config
  • Misc0 +: XDptx_MainStreamAttributes
  • Misc1 +: XDptx_MainStreamAttributes
  • MsaConfig +: XDptx
  • MsgBodyLength +: XDptx_SidebandMsgHeader
  • MsgCapStatus +: XDptx_SbMsgLinkAddressReplyPortDetail, XDptx_TopologyNode
  • MsgData +: XDptx_SidebandMsgBody
  • MsgDataLength +: XDptx_SidebandMsgBody
  • MsgHeaderLength +: XDptx_SidebandMsgHeader
  • MsgSequenceNum +: XDptx_SidebandMsgHeader
  • MstEnable +: XDptx
  • MstPbn +: XDptx_MstStream
  • MstStreamConfig +: XDptx
  • MstStreamEnable +: XDptx_MstStream
  • MstSupport +: XDptx_Config

    - n -

    +: XDptx_Topology
  • NodeTotal +: XDptx_Topology
  • NumAudioChs +: XDptx_Config
  • NumBytes +: XDptx_AuxTransaction
  • NumMstStreams +: XDptx_Config
  • NumPorts +: XDptx_SbMsgLinkAddressReplyDeviceInfo
  • NumSdpStreams +: XDptx_SbMsgLinkAddressReplyPortDetail
  • NumSdpStreamSinks +: XDptx_SbMsgLinkAddressReplyPortDetail
  • NVid +: XDptx_MainStreamAttributes

    - o -

    +: XDptx_MainStreamAttributes

    - p -

    +: XDptx_SidebandMsgHeader
  • Pattern +: XDptx_LinkConfig
  • PayloadDataWidth +: XDptx_Config
  • PeerDeviceType +: XDptx_SbMsgLinkAddressReplyPortDetail
  • PeLevel +: XDptx_LinkConfig
  • PortDetails +: XDptx_SbMsgLinkAddressReplyDeviceInfo
  • PortNum +: XDptx_SbMsgLinkAddressReplyPortDetail

    - q -

    +: XDptx_Config

    - r -

    +: XDptx_SidebandMsgHeader, XDptx_TopologyNode, XDptx_MstStream
  • ReplyType +: XDptx_SbMsgLinkAddressReplyDeviceInfo
  • RequestId +: XDptx_SbMsgLinkAddressReplyDeviceInfo
  • RxConfig +: XDptx

    - s -

    +: XDptx_Config
  • SbMsgDelayUs +: XDptx
  • ScramblerEn +: XDptx_LinkConfig
  • SecondaryChEn +: XDptx_Config
  • SinkList +: XDptx_Topology
  • SinkTotal +: XDptx_Topology
  • StartOfMsgTransaction +: XDptx_SidebandMsgHeader
  • SupportDownspreadControl +: XDptx_LinkConfig
  • SupportEnhancedFramingMode +: XDptx_LinkConfig
  • SynchronousClockMode +: XDptx_MainStreamAttributes

    - t -

    +: XDptx
  • TrainAdaptive +: XDptx
  • TransferUnitSize +: XDptx_MainStreamAttributes
  • TxPeLevels +: XDptx_BoardChar
  • TxVsLevels +: XDptx_BoardChar
  • TxVsOffset +: XDptx_BoardChar

    - u -

    +: XDptx_MainStreamAttributes
  • UserTimerPtr +: XDptx
  • UserTimerWaitUs +: XDptx

    - v -

    +
  • VClkTotal +: XDptx_MainStreamAttributes
  • VsLevel +: XDptx_LinkConfig
  • VStart +: XDptx_MainStreamAttributes
  • Vtm +: XDptx_MainStreamAttributes

    - y -

    +: XDptx_MainStreamAttributes
  • YCrCbEn +: XDptx_Config
  • YOnlyEn +: XDptx_Config Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions_vars.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions_vars.html index 7901fd7e..5c157539 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions_vars.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions_vars.html @@ -57,166 +57,152 @@

    - a -

    +: XDptx_AuxTransaction
  • AuxDelayUs +: XDptx
  • AvgBytesPerTU +: XDptx_MainStreamAttributes

    - b -

    +: XDptx_Config
  • BitsPerColor +: XDptx_MainStreamAttributes
  • BoardChar +: XDptx
  • Body +: XDptx_SidebandMsg
  • BroadcastMsg +: XDptx_SidebandMsgHeader

    - c -

    +: XDptx_AuxTransaction
  • ComponentFormat +: XDptx_MainStreamAttributes
  • Config +: XDptx
  • Crc +: XDptx_SidebandMsgBody, XDptx_SidebandMsgHeader

    - d -

    +: XDptx_SidebandReply, XDptx_AuxTransaction
  • DataPerLane +: XDptx_MainStreamAttributes
  • DeviceId +: XDptx_Config
  • DeviceType +: XDptx_TopologyNode
  • DownspreadControl +: XDptx_LinkConfig
  • DpcdRev +: XDptx_SbMsgLinkAddressReplyPortDetail, XDptx_TopologyNode
  • DpcdRxCapsField +: XDptx_SinkConfig
  • DpDevPlugStatus +: XDptx_SbMsgLinkAddressReplyPortDetail
  • DpProtocol +: XDptx_Config
  • DualPixelEn +: XDptx_Config
  • DynamicRange +: XDptx_MainStreamAttributes

    - e -

    +: XDptx_SidebandMsgHeader
  • EnhancedFramingMode +: XDptx_LinkConfig

    - g -

    +: XDptx_SbMsgLinkAddressReplyDeviceInfo, XDptx_SbMsgLinkAddressReplyPortDetail, XDptx_TopologyNode

    - h -

    +: XDptx_BoardChar
  • HClkTotal +: XDptx_MainStreamAttributes
  • Header +: XDptx_SidebandMsg
  • HpdEventCallbackRef +: XDptx
  • HpdEventHandler +: XDptx
  • HpdPulseCallbackRef +: XDptx
  • HpdPulseHandler +: XDptx
  • HStart +: XDptx_MainStreamAttributes

    - i -

    +: XDptx_MainStreamAttributes
  • InputPort +: XDptx_SbMsgLinkAddressReplyPortDetail
  • IsReady +: XDptx

    - l -

    +: XDptx_LinkConfig
  • LaneStatusAdjReqs +: XDptx_SinkConfig
  • LegacyDevPlugStatus +: XDptx_SbMsgLinkAddressReplyPortDetail
  • Length +: XDptx_SidebandReply
  • LinkConfig +: XDptx
  • LinkCountRemaining +: XDptx_SidebandMsgHeader
  • LinkCountTotal +: XDptx_SidebandMsgHeader, XDptx_TopologyNode, XDptx_MstStream
  • LinkRate +: XDptx_LinkConfig

    - m -

    +: XDptx_Config
  • MaxLaneCount +: XDptx_LinkConfig, XDptx_Config
  • MaxLinkRate +: XDptx_LinkConfig, XDptx_Config
  • Misc0 +: XDptx_MainStreamAttributes
  • Misc1 +: XDptx_MainStreamAttributes
  • MsaConfig +: XDptx
  • MsgBodyLength +: XDptx_SidebandMsgHeader
  • MsgCapStatus +: XDptx_SbMsgLinkAddressReplyPortDetail, XDptx_TopologyNode
  • MsgData +: XDptx_SidebandMsgBody
  • MsgDataLength +: XDptx_SidebandMsgBody
  • MsgHeaderLength +: XDptx_SidebandMsgHeader
  • MsgSequenceNum +: XDptx_SidebandMsgHeader
  • MstEnable +: XDptx
  • MstPbn +: XDptx_MstStream
  • MstStreamConfig +: XDptx
  • MstStreamEnable +: XDptx_MstStream
  • MstSupport +: XDptx_Config

    - n -

    +: XDptx_Topology
  • NodeTotal +: XDptx_Topology
  • NumAudioChs +: XDptx_Config
  • NumBytes +: XDptx_AuxTransaction
  • NumMstStreams +: XDptx_Config
  • NumPorts +: XDptx_SbMsgLinkAddressReplyDeviceInfo
  • NumSdpStreams +: XDptx_SbMsgLinkAddressReplyPortDetail
  • NumSdpStreamSinks +: XDptx_SbMsgLinkAddressReplyPortDetail
  • NVid +: XDptx_MainStreamAttributes

    - o -

    +: XDptx_MainStreamAttributes

    - p -

    +: XDptx_SidebandMsgHeader
  • Pattern +: XDptx_LinkConfig
  • PayloadDataWidth +: XDptx_Config
  • PeerDeviceType +: XDptx_SbMsgLinkAddressReplyPortDetail
  • PeLevel +: XDptx_LinkConfig
  • PortDetails +: XDptx_SbMsgLinkAddressReplyDeviceInfo
  • PortNum +: XDptx_SbMsgLinkAddressReplyPortDetail

    - q -

    +: XDptx_Config

    - r -

    +: XDptx_SidebandMsgHeader, XDptx_TopologyNode, XDptx_MstStream
  • ReplyType +: XDptx_SbMsgLinkAddressReplyDeviceInfo
  • RequestId +: XDptx_SbMsgLinkAddressReplyDeviceInfo
  • RxConfig +: XDptx

    - s -

    +: XDptx_Config
  • SbMsgDelayUs +: XDptx
  • ScramblerEn +: XDptx_LinkConfig
  • SecondaryChEn +: XDptx_Config
  • SinkList +: XDptx_Topology
  • SinkTotal +: XDptx_Topology
  • StartOfMsgTransaction +: XDptx_SidebandMsgHeader
  • SupportDownspreadControl +: XDptx_LinkConfig
  • SupportEnhancedFramingMode +: XDptx_LinkConfig
  • SynchronousClockMode +: XDptx_MainStreamAttributes

    - t -

    +: XDptx
  • TrainAdaptive +: XDptx
  • TransferUnitSize +: XDptx_MainStreamAttributes
  • TxPeLevels +: XDptx_BoardChar
  • TxVsLevels +: XDptx_BoardChar
  • TxVsOffset +: XDptx_BoardChar

    - u -

    +: XDptx_MainStreamAttributes
  • UserTimerPtr +: XDptx
  • UserTimerWaitUs +: XDptx

    - v -

    +
  • VClkTotal +: XDptx_MainStreamAttributes
  • VsLevel +: XDptx_LinkConfig
  • VStart +: XDptx_MainStreamAttributes
  • Vtm +: XDptx_MainStreamAttributes

    - y -

    +: XDptx_MainStreamAttributes
  • YCrCbEn +: XDptx_Config
  • YOnlyEn +: XDptx_Config Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals.html index b2369b2e..d830a898 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals.html @@ -45,5 +45,5 @@ Here is a list of all file members with links to the files they belong to:

    - g -

    +: xdptx_mst.c Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x72.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x72.html index 0aa9c757..1602258a 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x72.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x72.html @@ -45,6 +45,6 @@ Here is a list of all file members with links to the files they belong to:

    - r -

    +: xdptx_selftest.c
  • ResetValuesMsa +: xdptx_selftest.c Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x78.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x78.html index b7d234b5..18539fab 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x78.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x78.html @@ -45,801 +45,712 @@ Here is a list of all file members with links to the files they belong to:

    - x -

    +: xdptx_mst.c, xdptx.h
  • XDptx_AllocatePayloadVcIdTable() +: xdptx_mst.c, xdptx.h
  • XDPTX_AUX_ADDRESS +: xdptx_hw.h
  • XDPTX_AUX_CLK_DIVIDER +: xdptx_hw.h
  • XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK +: xdptx_hw.h
  • XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT +: xdptx_hw.h
  • XDPTX_AUX_CLK_DIVIDER_VAL_MASK +: xdptx_hw.h
  • XDPTX_AUX_CMD +: xdptx_hw.h
  • XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_READ +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_READ_MOT +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_WRITE +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_WRITE_MOT +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_WRITE_STATUS +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT +: xdptx_hw.h
  • XDPTX_AUX_CMD_MASK +: xdptx_hw.h
  • XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK +: xdptx_hw.h
  • XDPTX_AUX_CMD_READ +: xdptx_hw.h
  • XDPTX_AUX_CMD_SHIFT +: xdptx_hw.h
  • XDPTX_AUX_CMD_WRITE +: xdptx_hw.h
  • XDPTX_AUX_MAX_DEFER_COUNT +: xdptx.c
  • XDPTX_AUX_MAX_TIMEOUT_COUNT +: xdptx.c
  • XDPTX_AUX_REPLY_CODE +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_ACK +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_DEFER +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_I2C_ACK +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_I2C_DEFER +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_I2C_NACK +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_NACK +: xdptx_hw.h
  • XDPTX_AUX_REPLY_COUNT +: xdptx_hw.h
  • XDPTX_AUX_REPLY_DATA +: xdptx_hw.h
  • XDPTX_AUX_WRITE_FIFO +: xdptx_hw.h
  • XDptx_AuxRead() +: xdptx.h, xdptx.c
  • XDptx_AuxWrite() +: xdptx.h, xdptx.c
  • XDptx_CfgInitialize() +: xdptx.h, xdptx.c
  • XDptx_CfgMainLinkMax() +: xdptx.h, xdptx.c
  • XDptx_CfgMsaEnSynchClkMode() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaRecalculate() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaSetBpc() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaUseCustom() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaUseEdidPreferredTiming() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaUseStandardVideoMode() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgTxPeLevel() +: xdptx.h, xdptx.c
  • XDptx_CfgTxVsLevel() +: xdptx.h, xdptx.c
  • XDptx_CfgTxVsOffset() +: xdptx.h, xdptx.c
  • XDptx_CheckLinkStatus() +: xdptx.h, xdptx.c
  • XDptx_ClearMsaValues() +: xdptx_spm.c, xdptx.h
  • XDptx_ClearPayloadVcIdTable() +: xdptx_mst.c, xdptx.h
  • XDptx_ConfigTable +: xdptx_sinit.c
  • XDPTX_CORE_ID +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_MJR_VER_MASK +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_MJR_VER_SHIFT +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_MNR_VER_MASK +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_MNR_VER_SHIFT +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_REV_MASK +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_REV_SHIFT +: xdptx_hw.h
  • XDPTX_CORE_ID_TYPE_MASK +: xdptx_hw.h
  • XDPTX_CORE_ID_TYPE_RX +: xdptx_hw.h
  • XDPTX_CORE_ID_TYPE_TX +: xdptx_hw.h
  • XDptx_DisableMainLink() +: xdptx.h, xdptx.c
  • XDptx_DiscoverTopology() +: xdptx_mst.c, xdptx.h
  • XDPTX_DISPID_DB_SEC_REV +: xdptx_hw.h
  • XDPTX_DISPID_DB_SEC_SIZE +: xdptx_hw.h
  • XDPTX_DISPID_DB_SEC_TAG +: xdptx_hw.h
  • XDPTX_DISPID_EXT_COUNT +: xdptx_hw.h
  • XDPTX_DISPID_PAYLOAD_START +: xdptx_hw.h
  • XDPTX_DISPID_SIZE +: xdptx_hw.h
  • XDPTX_DISPID_TDT_HSIZE0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_HSIZE1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_PCODE0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_PCODE1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_SN0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_SN1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_SN2 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_SN3 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TAG +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP0_HTOT_L_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP0_HTOT_L_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP0_VTOT_L_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP1_HLOC_L_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP1_HLOC_L_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP1_VLOC_L_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_HLOC_H_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_HLOC_H_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_HTOT_H_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_HTOT_H_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_VLOC_H_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_VTOT_H_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_VTOT_H_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VENID0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VENID1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VENID2 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VSIZE0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VSIZE1 +: xdptx_hw.h
  • XDPTX_DISPID_TYPE +: xdptx_hw.h
  • XDPTX_DISPID_VER_REV +: xdptx_hw.h
  • XDPTX_DOWNSPREAD_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_ADAPTER_CAP +: xdptx_hw.h
  • XDPTX_DPCD_ADAPTER_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_0_1 +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_2_3 +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2 +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEC_LAT_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEC_LAT_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEL_INS_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEL_INS_23_16 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEL_INS_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_PP_LAT_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_PP_LAT_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_AUDIO_DELAY_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_AUDIO_DELAY_23_6 +: xdptx_hw.h
  • XDPTX_DPCD_AUDIO_DELAY_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_AV_GRANULARITY +: xdptx_hw.h
  • XDPTX_DPCD_BACK_CH_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_BRANCH_DEVICE_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_DEVICE_SERVICE_IRQ +: xdptx_hw.h
  • XDPTX_DPCD_DOWN_REP +: xdptx_hw.h
  • XDPTX_DPCD_DOWN_REQ +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_0_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_0_DET_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_1_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_1_DET_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_2_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_2_DET_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_3_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_3_DET_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_COUNT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_PRESENT +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_PRESENT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_DP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_OTHERS +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSPREAD_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_EDP_CFG_CAP +: xdptx_hw.h
  • XDPTX_DPCD_EDP_CFG_SET +: xdptx_hw.h
  • XDPTX_DPCD_ENHANCED_FRAME_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_CAP +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_CAP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_FORWARD_CH_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_MODE_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_GUID +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_CAP +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_NONE +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_SET +: xdptx_hw.h
  • XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED +: xdptx_hw.h
  • XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK +: xdptx_hw.h
  • XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET_1 +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET_2 +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET_4 +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET_MASK +: xdptx_hw.h
  • XDPTX_DPCD_LINK_BW_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_BW_SET_162GBPS +: xdptx_hw.h
  • XDPTX_DPCD_LINK_BW_SET_270GBPS +: xdptx_hw.h
  • XDPTX_DPCD_LINK_BW_SET_540GBPS +: xdptx_hw.h
  • XDPTX_DPCD_LINK_CFG_FIELD_SIZE +: xdptx_hw.h
  • XDPTX_DPCD_LINK_CFG_FIELD_START +: xdptx_hw.h
  • XDPTX_DPCD_LINK_QUAL_LANE0_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_QUAL_LANE1_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_QUAL_LANE2_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_QUAL_LANE3_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE +: xdptx_hw.h
  • XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START +: xdptx_hw.h
  • XDPTX_DPCD_MAX_DOWNSPREAD +: xdptx_hw.h
  • XDPTX_DPCD_MAX_DOWNSPREAD_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT_1 +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT_2 +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT_4 +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LINK_RATE +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LINK_RATE_162GBPS +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LINK_RATE_270GBPS +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LINK_RATE_540GBPS +: xdptx_hw.h
  • XDPTX_DPCD_ML_CH_CODING_CAP +: xdptx_hw.h
  • XDPTX_DPCD_ML_CH_CODING_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ML_CH_CODING_SET +: xdptx_hw.h
  • XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MST_CAP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MST_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MSTM_CAP +: xdptx_hw.h
  • XDPTX_DPCD_MSTM_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_NORP_PWR_V_CAP +: xdptx_hw.h
  • XDPTX_DPCD_NUM_AUDIO_EPS +: xdptx_hw.h
  • XDPTX_DPCD_OUI_SUPPORT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_PAYLOAD_ALLOCATE_SET +: xdptx_hw.h
  • XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT +: xdptx_hw.h
  • XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE +: xdptx_hw.h
  • XDPTX_DPCD_RECEIVER_CAP_FIELD_START +: xdptx_hw.h
  • XDPTX_DPCD_REP_LAT +: xdptx_hw.h
  • XDPTX_DPCD_REV +: xdptx_hw.h
  • XDPTX_DPCD_REV_MJR_MASK +: xdptx_hw.h
  • XDPTX_DPCD_REV_MJR_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_REV_MNR_MASK +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_MSTR_REQ +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_23_16 +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_31_24 +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORT0_CAP_0 +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORT0_CAP_1 +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORT1_CAP_0 +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORT1_CAP_1 +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE +: xdptx_hw.h
  • XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI +: xdptx_hw.h
  • XDPTX_DPCD_SINK_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_SINK_COUNT_ESI +: xdptx_hw.h
  • XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 +: xdptx_hw.h
  • XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 +: xdptx_hw.h
  • XDPTX_DPCD_SINK_LANE0_1_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_SINK_LANE2_3_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 +: xdptx_hw.h
  • XDPTX_DPCD_SINK_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_SINK_STATUS_ESI +: xdptx_hw.h
  • XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_SPREAD_AMP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_0_1 +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_2_3 +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0 +: xdptx_hw.h
  • XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1 +: xdptx_hw.h
  • XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2 +: xdptx_hw.h
  • XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_OFF +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_TP1 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_TP2 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_TP3 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_D102_TEST +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_OFF +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_PRBS7 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_SER_MES +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_TPS3_SUPPORT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE0_1_SET2 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE0_SET +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE1_SET +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE2_3_SET2 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE2_SET +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE3_SET +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_SCORE_LANE_0 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_SCORE_LANE_1 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_SCORE_LANE_2 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_SCORE_LANE_3 +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_VALUE_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_VALUE_23_16 +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_VALUE_31_24 +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_VALUE_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_UP_IS_SRC_MASK +: xdptx_hw.h
  • XDPTX_DPCD_UP_REP +: xdptx_hw.h
  • XDPTX_DPCD_UP_REQ +: xdptx_hw.h
  • XDPTX_DPCD_UP_REQ_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED +: xdptx_hw.h
  • XDPTX_DPCD_VC_PAYLOAD_ID_SLOT +: xdptx_hw.h
  • XDPTX_DPCD_VID_INTER_LAT +: xdptx_hw.h
  • XDPTX_DPCD_VID_PROG_LAT +: xdptx_hw.h
  • XDPTX_EDID_ADDR +: xdptx_hw.h
  • XDPTX_EDID_BLOCK_SIZE +: xdptx_hw.h
  • XDPTX_EDID_DTD_DD +: xdptx_hw.h
  • XDPTX_EDID_DTD_HBLANK_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_HBORDER +: xdptx_hw.h
  • XDPTX_EDID_DTD_HFPORCH_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_HIMGSIZE_MM_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_HRES_HBLANK_U4 +: xdptx_hw.h
  • XDPTX_EDID_DTD_HRES_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_HSPW_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_VBLANK_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_VBORDER +: xdptx_hw.h
  • XDPTX_EDID_DTD_VFPORCH_VSPW_L4 +: xdptx_hw.h
  • XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_VIMGSIZE_MM_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_VRES_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_VRES_VBLANK_U4 +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2 +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XIMGSIZE_MM_U4 +: xdptx_hw.h
  • XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_EXT_BLOCK_COUNT +: xdptx_hw.h
  • XDPTX_EDID_EXT_BLOCK_TAG +: xdptx_hw.h
  • XDPTX_EDID_EXT_BLOCK_TAG_DISPID +: xdptx_hw.h
  • XDPTX_EDID_PTM +: xdptx_hw.h
  • XDPTX_ENABLE +: xdptx_hw.h
  • XDPTX_ENABLE_MAIN_STREAM +: xdptx_hw.h
  • XDPTX_ENABLE_SEC_STREAM +: xdptx_hw.h
  • XDptx_EnableMainLink() +: xdptx.h, xdptx.c
  • XDptx_EnableTrainAdaptive() +: xdptx.h, xdptx.c
  • XDPTX_ENHANCED_FRAME_EN +: xdptx_hw.h
  • XDptx_EstablishLink() +: xdptx.h, xdptx.c
  • XDptx_FindAccessibleDpDevices() +: xdptx_mst.c, xdptx.h
  • XDPTX_FORCE_SCRAMBLER_RESET +: xdptx_hw.h
  • XDPTX_FRAC_BYTES_PER_TU +: xdptx_hw.h
  • XDptx_GetDispIdDataBlock() +: xdptx_edid.c, xdptx.h
  • XDptx_GetDispIdTdtHLoc +: xdptx_hw.h
  • XDptx_GetDispIdTdtHTotal +: xdptx_hw.h
  • XDptx_GetDispIdTdtNumTiles +: xdptx_hw.h
  • XDptx_GetDispIdTdtTileOrder +: xdptx_hw.h
  • XDptx_GetDispIdTdtVLoc +: xdptx_hw.h
  • XDptx_GetDispIdTdtVTotal +: xdptx_hw.h
  • XDptx_GetEdid() +: xdptx_edid.c, xdptx.h
  • XDptx_GetEdidBlock() +: xdptx_edid.c, xdptx.h
  • XDptx_GetGuid() +: xdptx_mst.c, xdptx.h
  • XDptx_GetRemoteEdid() +: xdptx_edid.c, xdptx.h
  • XDptx_GetRemoteEdidBlock() +: xdptx_edid.c, xdptx.h
  • XDptx_GetRemoteEdidDispIdExt() +: xdptx_edid.c, xdptx.h
  • XDptx_GetRemoteTiledDisplayDb() +: xdptx_edid.c, xdptx.h
  • XDptx_GetRxCapabilities() +: xdptx.h, xdptx.c
  • XDPTX_GT_DRP_CHANNEL_STATUS +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT +: xdptx_hw.h
  • XDPTX_GT_DRP_READ_DATA +: xdptx_hw.h
  • XDPTX_HPD_DURATION +: xdptx_hw.h
  • XDptx_HpdEventHandler +: xdptx.h
  • XDptx_HpdInterruptHandler() +: xdptx_intr.c, xdptx.h
  • XDptx_HpdPulseHandler +: xdptx.h
  • XDptx_IicRead() +: xdptx.h, xdptx.c
  • XDptx_IicWrite() +: xdptx.h, xdptx.c
  • XDptx_In32 +: xdptx_hw.h
  • XDPTX_INIT_WAIT +: xdptx_hw.h
  • XDptx_InitializeTx() +: xdptx.h, xdptx.c
  • XDPTX_INTERRUPT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK +: xdptx_hw.h
  • XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT +: xdptx.c
  • XDptx_IsConnected() +: xdptx.h, xdptx.c
  • XDptx_IsEdidExtBlockDispId +: xdptx_hw.h
  • XDPTX_LANE_COUNT_SET +: xdptx_hw.h
  • XDPTX_LANE_COUNT_SET_1 +: xdptx_hw.h
  • XDPTX_LANE_COUNT_SET_2 +: xdptx_hw.h
  • XDPTX_LANE_COUNT_SET_4 +: xdptx_hw.h
  • XDPTX_LINK_BW_SET +: xdptx_hw.h
  • XDPTX_LINK_BW_SET_162GBPS +: xdptx_hw.h
  • XDPTX_LINK_BW_SET_270GBPS +: xdptx_hw.h
  • XDPTX_LINK_BW_SET_540GBPS +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET_OFF +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET_PRBS7 +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET_SER_MES +: xdptx_hw.h
  • XDptx_LookupConfig() +: xdptx_sinit.c, xdptx.h
  • XDPTX_M_VID +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_HRES +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_HSTART +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_HSWIDTH +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_HTOTAL +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_INTERLACED +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_MISC0 +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_MISC1 +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_POLARITY +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_VRES +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_VSTART +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_VSWIDTH +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_VTOTAL +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT +: xdptx_hw.h
  • XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT +: xdptx_mst.c
  • XDPTX_MAXIMUM_PE_LEVEL +: xdptx.c
  • XDPTX_MAXIMUM_VS_LEVEL +: xdptx.c
  • XDPTX_MIN_BYTES_PER_TU +: xdptx_hw.h
  • XDptx_MstCapable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstCfgModeDisable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstCfgModeEnable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstCfgStreamDisable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstCfgStreamEnable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstDisable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstEnable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstStreamIsEnabled() +: xdptx_mst.c, xdptx.h
  • XDPTX_N_VID +: xdptx_hw.h
  • XDptx_Out32 +: xdptx_hw.h
  • XDPTX_PE_LEVEL_0 +: xdptx_hw.h
  • XDPTX_PE_LEVEL_1 +: xdptx_hw.h
  • XDPTX_PE_LEVEL_2 +: xdptx_hw.h
  • XDPTX_PE_LEVEL_3 +: xdptx_hw.h
  • XDPTX_PHY_CLOCK_SELECT +: xdptx_hw.h
  • XDPTX_PHY_CLOCK_SELECT_162GBPS +: xdptx_hw.h
  • XDPTX_PHY_CLOCK_SELECT_270GBPS +: xdptx_hw.h
  • XDPTX_PHY_CLOCK_SELECT_540GBPS +: xdptx_hw.h
  • XDPTX_PHY_CONFIG +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_GTTX_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_PHY_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK +: xdptx_hw.h
  • XDPTX_PHY_POSTCURSOR_LANE_0 +: xdptx_hw.h
  • XDPTX_PHY_POSTCURSOR_LANE_1 +: xdptx_hw.h
  • XDPTX_PHY_POSTCURSOR_LANE_2 +: xdptx_hw.h
  • XDPTX_PHY_POSTCURSOR_LANE_3 +: xdptx_hw.h
  • XDPTX_PHY_PRECURSOR_LANE_0 +: xdptx_hw.h
  • XDPTX_PHY_PRECURSOR_LANE_1 +: xdptx_hw.h
  • XDPTX_PHY_PRECURSOR_LANE_2 +: xdptx_hw.h
  • XDPTX_PHY_PRECURSOR_LANE_3 +: xdptx_hw.h
  • XDPTX_PHY_STATUS +: xdptx_hw.h
  • XDPTX_PHY_STATUS_ALL_LANES_READY_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_LANES_0_1_READY_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_TRANSMIT_PRBS7 +: xdptx_hw.h
  • XDPTX_PHY_VOLTAGE_DIFF_LANE_0 +: xdptx_hw.h
  • XDPTX_PHY_VOLTAGE_DIFF_LANE_1 +: xdptx_hw.h
  • XDPTX_PHY_VOLTAGE_DIFF_LANE_2 +: xdptx_hw.h
  • XDPTX_PHY_VOLTAGE_DIFF_LANE_3 +: xdptx_hw.h
  • XDptx_ReadReg +: xdptx_hw.h
  • XDptx_RemoteDpcdRead() +: xdptx_mst.c, xdptx.h
  • XDptx_RemoteDpcdWrite() +: xdptx_mst.c, xdptx.h
  • XDptx_RemoteIicRead() +: xdptx_mst.c, xdptx.h
  • XDptx_RemoteIicWrite() +: xdptx_mst.c, xdptx.h
  • XDPTX_REPLY_DATA_COUNT +: xdptx_hw.h
  • XDPTX_REPLY_STATUS +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_ERROR_MASK +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK +: xdptx_hw.h
  • XDptx_ResetPhy() +: xdptx.h, xdptx.c
  • XDPTX_SBMSG_ALLOCATE_PAYLOAD +: xdptx_hw.h
  • XDPTX_SBMSG_CLEAR_PAYLOAD_ID_TABLE +: xdptx_hw.h
  • XDPTX_SBMSG_ENUM_PATH_RESOURCES +: xdptx_hw.h
  • XDPTX_SBMSG_LINK_ADDRESS +: xdptx_hw.h
  • XDPTX_SBMSG_REMOTE_DPCD_READ +: xdptx_hw.h
  • XDPTX_SBMSG_REMOTE_DPCD_WRITE +: xdptx_hw.h
  • XDPTX_SBMSG_REMOTE_I2C_READ +: xdptx_hw.h
  • XDPTX_SBMSG_REMOTE_I2C_WRITE +: xdptx_hw.h
  • XDPTX_SCRAMBLING_DISABLE +: xdptx_hw.h
  • XDPTX_SEGPTR_ADDR +: xdptx_hw.h
  • XDptx_SelfTest() +: xdptx_selftest.c, xdptx.h
  • XDptx_SendSbMsgAllocatePayload() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgClearPayloadIdTable() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgEnumPathResources() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgLinkAddress() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgRemoteDpcdRead() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgRemoteDpcdWrite() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgRemoteIicRead() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgRemoteIicWrite() +: xdptx_mst.c, xdptx.h
  • XDptx_SetDownspread() +: xdptx.h, xdptx.c
  • XDptx_SetEnhancedFrameMode() +: xdptx.h, xdptx.c
  • XDptx_SetHasRedriverInPath() +: xdptx.h, xdptx.c
  • XDptx_SetHpdEventHandler() +: xdptx_intr.c, xdptx.h
  • XDptx_SetHpdPulseHandler() +: xdptx_intr.c, xdptx.h
  • XDptx_SetLaneCount() +: xdptx.h, xdptx.c
  • XDptx_SetLinkRate() +: xdptx.h, xdptx.c
  • XDptx_SetMsaValues() +: xdptx_spm.c, xdptx.h
  • XDptx_SetScrambler() +: xdptx.h, xdptx.c
  • XDptx_SetStreamSelectFromSinkList() +: xdptx_mst.c, xdptx.h
  • XDptx_SetStreamSinkRad() +: xdptx_mst.c, xdptx.h
  • XDptx_SetUserTimerHandler() +: xdptx.h, xdptx.c
  • XDptx_SetVideoMode() +: xdptx_spm.c, xdptx.h
  • XDPTX_SOFT_RESET +: xdptx_hw.h
  • XDPTX_SOFT_RESET_AUX_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK +: xdptx_hw.h
  • XDPTX_STREAM1 +: xdptx_hw.h
  • XDPTX_STREAM1_MSA_START +: xdptx_hw.h
  • XDPTX_STREAM2 +: xdptx_hw.h
  • XDPTX_STREAM2_MSA_START +: xdptx_hw.h
  • XDPTX_STREAM2_MSA_START_OFFSET +: xdptx_hw.h
  • XDPTX_STREAM3 +: xdptx_hw.h
  • XDPTX_STREAM3_MSA_START +: xdptx_hw.h
  • XDPTX_STREAM3_MSA_START_OFFSET +: xdptx_hw.h
  • XDPTX_STREAM4 +: xdptx_hw.h
  • XDPTX_STREAM4_MSA_START +: xdptx_hw.h
  • XDPTX_STREAM4_MSA_START_OFFSET +: xdptx_hw.h
  • XDPTX_STREAM_ID1 +: xdptx_hw.h
  • XDPTX_STREAM_ID2 +: xdptx_hw.h
  • XDPTX_STREAM_ID3 +: xdptx_hw.h
  • XDPTX_STREAM_ID4 +: xdptx_hw.h
  • XDptx_TimerHandler +: xdptx.h
  • XDptx_TopologySortSinksByTiling() +: xdptx_mst.c, xdptx.h
  • XDptx_TopologySwapSinks() +: xdptx_mst.c, xdptx.h
  • XDPTX_TRAINING_PATTERN_SET +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET_OFF +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET_TP1 +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET_TP2 +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET_TP3 +: xdptx_hw.h
  • XDptx_TrainingState +: xdptx.c
  • XDPTX_TS_ADJUST_LANE_COUNT +: xdptx.c
  • XDPTX_TS_ADJUST_LINK_RATE +: xdptx.c
  • XDPTX_TS_CHANNEL_EQUALIZATION +: xdptx.c
  • XDPTX_TS_CLOCK_RECOVERY +: xdptx.c
  • XDPTX_TS_FAILURE +: xdptx.c
  • XDPTX_TS_SUCCESS +: xdptx.c
  • XDPTX_TU_SIZE +: xdptx_hw.h
  • XDPTX_TX_AUDIO_CHANNELS +: xdptx_hw.h
  • XDPTX_TX_AUDIO_CONTROL +: xdptx_hw.h
  • XDPTX_TX_AUDIO_EXT_DATA +: xdptx_hw.h
  • XDPTX_TX_AUDIO_INFO_DATA +: xdptx_hw.h
  • XDPTX_TX_AUDIO_MAUD +: xdptx_hw.h
  • XDPTX_TX_AUDIO_NAUD +: xdptx_hw.h
  • XDPTX_TX_MST_CONFIG +: xdptx_hw.h
  • XDPTX_TX_MST_CONFIG_MST_EN_MASK +: xdptx_hw.h
  • XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK +: xdptx_hw.h
  • XDPTX_TX_PHY_POWER_DOWN +: xdptx_hw.h
  • XDPTX_TX_USER_FIFO_OVERFLOW +: xdptx_hw.h
  • XDPTX_USER_DATA_COUNT_PER_LANE +: xdptx_hw.h
  • XDPTX_USER_PIXEL_WIDTH +: xdptx_hw.h
  • XDPTX_VC_PAYLOAD_BUFFER_ADDR +: xdptx_hw.h
  • XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT +: xdptx_mst.c
  • XDPTX_VERSION +: xdptx_hw.h
  • XDPTX_VERSION_CORE_PATCH_MASK +: xdptx_hw.h
  • XDPTX_VERSION_CORE_PATCH_SHIFT +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_MJR_MASK +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_MJR_SHIFT +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_MNR_MASK +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_MNR_SHIFT +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_REV_MASK +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_REV_SHIFT +: xdptx_hw.h
  • XDPTX_VERSION_INTER_REV_MASK +: xdptx_hw.h
  • XDPTX_VS_LEVEL_0 +: xdptx_hw.h
  • XDPTX_VS_LEVEL_1 +: xdptx_hw.h
  • XDPTX_VS_LEVEL_2 +: xdptx_hw.h
  • XDPTX_VS_LEVEL_3 +: xdptx_hw.h
  • XDPTX_VS_LEVEL_OFFSET +: xdptx_hw.h
  • XDptx_WaitUs() +: xdptx.h, xdptx.c
  • XDptx_WriteGuid() +: xdptx_mst.c, xdptx.h
  • XDptx_WriteReg +: xdptx_hw.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_defs.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_defs.html index beeb32fb..763d1a79 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_defs.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_defs.html @@ -43,622 +43,623 @@

    - x -

    +: xdptx_hw.h
  • XDPTX_AUX_CLK_DIVIDER +: xdptx_hw.h
  • XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK +: xdptx_hw.h
  • XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT +: xdptx_hw.h
  • XDPTX_AUX_CLK_DIVIDER_VAL_MASK +: xdptx_hw.h
  • XDPTX_AUX_CMD +: xdptx_hw.h
  • XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_READ +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_READ_MOT +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_WRITE +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_WRITE_MOT +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_WRITE_STATUS +: xdptx_hw.h
  • XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT +: xdptx_hw.h
  • XDPTX_AUX_CMD_MASK +: xdptx_hw.h
  • XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK +: xdptx_hw.h
  • XDPTX_AUX_CMD_READ +: xdptx_hw.h
  • XDPTX_AUX_CMD_SHIFT +: xdptx_hw.h
  • XDPTX_AUX_CMD_WRITE +: xdptx_hw.h
  • XDPTX_AUX_MAX_DEFER_COUNT +: xdptx.c
  • XDPTX_AUX_MAX_TIMEOUT_COUNT +: xdptx.c
  • XDPTX_AUX_REPLY_CODE +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_ACK +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_DEFER +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_I2C_ACK +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_I2C_DEFER +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_I2C_NACK +: xdptx_hw.h
  • XDPTX_AUX_REPLY_CODE_NACK +: xdptx_hw.h
  • XDPTX_AUX_REPLY_COUNT +: xdptx_hw.h
  • XDPTX_AUX_REPLY_DATA +: xdptx_hw.h
  • XDPTX_AUX_WRITE_FIFO +: xdptx_hw.h
  • XDPTX_CORE_ID +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_MJR_VER_MASK +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_MJR_VER_SHIFT +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_MNR_VER_MASK +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_MNR_VER_SHIFT +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_REV_MASK +: xdptx_hw.h
  • XDPTX_CORE_ID_DP_REV_SHIFT +: xdptx_hw.h
  • XDPTX_CORE_ID_TYPE_MASK +: xdptx_hw.h
  • XDPTX_CORE_ID_TYPE_RX +: xdptx_hw.h
  • XDPTX_CORE_ID_TYPE_TX +: xdptx_hw.h
  • XDPTX_DISPID_DB_SEC_REV +: xdptx_hw.h
  • XDPTX_DISPID_DB_SEC_SIZE +: xdptx_hw.h
  • XDPTX_DISPID_DB_SEC_TAG +: xdptx_hw.h
  • XDPTX_DISPID_EXT_COUNT +: xdptx_hw.h
  • XDPTX_DISPID_PAYLOAD_START +: xdptx_hw.h
  • XDPTX_DISPID_SIZE +: xdptx_hw.h
  • XDPTX_DISPID_TDT_HSIZE0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_HSIZE1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_PCODE0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_PCODE1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_SN0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_SN1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_SN2 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_SN3 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TAG +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP0_HTOT_L_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP0_HTOT_L_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP0_VTOT_L_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP1_HLOC_L_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP1_HLOC_L_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP1_VLOC_L_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_HLOC_H_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_HLOC_H_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_HTOT_H_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_HTOT_H_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_VLOC_H_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_VTOT_H_MASK +: xdptx_hw.h
  • XDPTX_DISPID_TDT_TOP2_VTOT_H_SHIFT +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VENID0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VENID1 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VENID2 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VSIZE0 +: xdptx_hw.h
  • XDPTX_DISPID_TDT_VSIZE1 +: xdptx_hw.h
  • XDPTX_DISPID_TYPE +: xdptx_hw.h
  • XDPTX_DISPID_VER_REV +: xdptx_hw.h
  • XDPTX_DOWNSPREAD_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_ADAPTER_CAP +: xdptx_hw.h
  • XDPTX_DPCD_ADAPTER_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_0_1 +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_LANE_2_3 +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2 +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEC_LAT_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEC_LAT_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEL_INS_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEL_INS_23_16 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_DEL_INS_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_PP_LAT_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_AUD_PP_LAT_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_AUDIO_DELAY_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_AUDIO_DELAY_23_6 +: xdptx_hw.h
  • XDPTX_DPCD_AUDIO_DELAY_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_AV_GRANULARITY +: xdptx_hw.h
  • XDPTX_DPCD_BACK_CH_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_BRANCH_DEVICE_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_DEVICE_SERVICE_IRQ +: xdptx_hw.h
  • XDPTX_DPCD_DOWN_REP +: xdptx_hw.h
  • XDPTX_DPCD_DOWN_REQ +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_0_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_0_DET_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_1_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_1_DET_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_2_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_2_DET_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_3_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_3_DET_CAP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_COUNT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_PRESENT +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_PRESENT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_DP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_OTHERS +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_TYPE_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK +: xdptx_hw.h
  • XDPTX_DPCD_DOWNSPREAD_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_EDP_CFG_CAP +: xdptx_hw.h
  • XDPTX_DPCD_EDP_CFG_SET +: xdptx_hw.h
  • XDPTX_DPCD_ENHANCED_FRAME_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_CAP +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_CAP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_FORWARD_CH_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_FAUX_MODE_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_GUID +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_CAP +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_NONE +: xdptx_hw.h
  • XDPTX_DPCD_I2C_SPEED_CTL_SET +: xdptx_hw.h
  • XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED +: xdptx_hw.h
  • XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK +: xdptx_hw.h
  • XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET_1 +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET_2 +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET_4 +: xdptx_hw.h
  • XDPTX_DPCD_LANE_COUNT_SET_MASK +: xdptx_hw.h
  • XDPTX_DPCD_LINK_BW_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_BW_SET_162GBPS +: xdptx_hw.h
  • XDPTX_DPCD_LINK_BW_SET_270GBPS +: xdptx_hw.h
  • XDPTX_DPCD_LINK_BW_SET_540GBPS +: xdptx_hw.h
  • XDPTX_DPCD_LINK_CFG_FIELD_SIZE +: xdptx_hw.h
  • XDPTX_DPCD_LINK_CFG_FIELD_START +: xdptx_hw.h
  • XDPTX_DPCD_LINK_QUAL_LANE0_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_QUAL_LANE1_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_QUAL_LANE2_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_QUAL_LANE3_SET +: xdptx_hw.h
  • XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE +: xdptx_hw.h
  • XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START +: xdptx_hw.h
  • XDPTX_DPCD_MAX_DOWNSPREAD +: xdptx_hw.h
  • XDPTX_DPCD_MAX_DOWNSPREAD_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT_1 +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT_2 +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT_4 +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LANE_COUNT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LINK_RATE +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LINK_RATE_162GBPS +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LINK_RATE_270GBPS +: xdptx_hw.h
  • XDPTX_DPCD_MAX_LINK_RATE_540GBPS +: xdptx_hw.h
  • XDPTX_DPCD_ML_CH_CODING_CAP +: xdptx_hw.h
  • XDPTX_DPCD_ML_CH_CODING_MASK +: xdptx_hw.h
  • XDPTX_DPCD_ML_CH_CODING_SET +: xdptx_hw.h
  • XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MST_CAP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MST_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_MSTM_CAP +: xdptx_hw.h
  • XDPTX_DPCD_MSTM_CTRL +: xdptx_hw.h
  • XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_NORP_PWR_V_CAP +: xdptx_hw.h
  • XDPTX_DPCD_NUM_AUDIO_EPS +: xdptx_hw.h
  • XDPTX_DPCD_OUI_SUPPORT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_PAYLOAD_ALLOCATE_SET +: xdptx_hw.h
  • XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT +: xdptx_hw.h
  • XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE +: xdptx_hw.h
  • XDPTX_DPCD_RECEIVER_CAP_FIELD_START +: xdptx_hw.h
  • XDPTX_DPCD_REP_LAT +: xdptx_hw.h
  • XDPTX_DPCD_REV +: xdptx_hw.h
  • XDPTX_DPCD_REV_MJR_MASK +: xdptx_hw.h
  • XDPTX_DPCD_REV_MJR_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_REV_MNR_MASK +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_MSTR_REQ +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_23_16 +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_31_24 +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORT0_CAP_0 +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORT0_CAP_1 +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORT1_CAP_0 +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORT1_CAP_1 +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE +: xdptx_hw.h
  • XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI +: xdptx_hw.h
  • XDPTX_DPCD_SINK_COUNT +: xdptx_hw.h
  • XDPTX_DPCD_SINK_COUNT_ESI +: xdptx_hw.h
  • XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 +: xdptx_hw.h
  • XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 +: xdptx_hw.h
  • XDPTX_DPCD_SINK_LANE0_1_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_SINK_LANE2_3_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 +: xdptx_hw.h
  • XDPTX_DPCD_SINK_STATUS +: xdptx_hw.h
  • XDPTX_DPCD_SINK_STATUS_ESI +: xdptx_hw.h
  • XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_SPREAD_AMP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_0_1 +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_2_3 +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0 +: xdptx_hw.h
  • XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1 +: xdptx_hw.h
  • XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2 +: xdptx_hw.h
  • XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_OFF +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_TP1 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_TP2 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SEL_TP3 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_D102_TEST +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_OFF +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_PRBS7 +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_SER_MES +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_LQP_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_TPS3_SUPPORT_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS +: xdptx_hw.h
  • XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE0_1_SET2 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE0_SET +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE1_SET +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE2_3_SET2 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE2_SET +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE3_SET +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_SCORE_LANE_0 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_SCORE_LANE_1 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_SCORE_LANE_2 +: xdptx_hw.h
  • XDPTX_DPCD_TRAINING_SCORE_LANE_3 +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_VALUE_15_8 +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_VALUE_23_16 +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_VALUE_31_24 +: xdptx_hw.h
  • XDPTX_DPCD_TX_GTC_VALUE_7_0 +: xdptx_hw.h
  • XDPTX_DPCD_UP_IS_SRC_MASK +: xdptx_hw.h
  • XDPTX_DPCD_UP_REP +: xdptx_hw.h
  • XDPTX_DPCD_UP_REQ +: xdptx_hw.h
  • XDPTX_DPCD_UP_REQ_EN_MASK +: xdptx_hw.h
  • XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED +: xdptx_hw.h
  • XDPTX_DPCD_VC_PAYLOAD_ID_SLOT +: xdptx_hw.h
  • XDPTX_DPCD_VID_INTER_LAT +: xdptx_hw.h
  • XDPTX_DPCD_VID_PROG_LAT +: xdptx_hw.h
  • XDPTX_EDID_ADDR +: xdptx_hw.h
  • XDPTX_EDID_BLOCK_SIZE +: xdptx_hw.h
  • XDPTX_EDID_DTD_DD +: xdptx_hw.h
  • XDPTX_EDID_DTD_HBLANK_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_HBORDER +: xdptx_hw.h
  • XDPTX_EDID_DTD_HFPORCH_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_HIMGSIZE_MM_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_HRES_HBLANK_U4 +: xdptx_hw.h
  • XDPTX_EDID_DTD_HRES_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_HSPW_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_VBLANK_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_VBORDER +: xdptx_hw.h
  • XDPTX_EDID_DTD_VFPORCH_VSPW_L4 +: xdptx_hw.h
  • XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_VIMGSIZE_MM_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_VRES_LSB +: xdptx_hw.h
  • XDPTX_EDID_DTD_VRES_VBLANK_U4 +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2 +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XIMGSIZE_MM_U4 +: xdptx_hw.h
  • XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK +: xdptx_hw.h
  • XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT +: xdptx_hw.h
  • XDPTX_EDID_EXT_BLOCK_COUNT +: xdptx_hw.h
  • XDPTX_EDID_EXT_BLOCK_TAG +: xdptx_hw.h
  • XDPTX_EDID_EXT_BLOCK_TAG_DISPID +: xdptx_hw.h
  • XDPTX_EDID_PTM +: xdptx_hw.h
  • XDPTX_ENABLE +: xdptx_hw.h
  • XDPTX_ENABLE_MAIN_STREAM +: xdptx_hw.h
  • XDPTX_ENABLE_SEC_STREAM +: xdptx_hw.h
  • XDPTX_ENHANCED_FRAME_EN +: xdptx_hw.h
  • XDPTX_FORCE_SCRAMBLER_RESET +: xdptx_hw.h
  • XDPTX_FRAC_BYTES_PER_TU +: xdptx_hw.h
  • XDptx_GetDispIdTdtHLoc +: xdptx_hw.h
  • XDptx_GetDispIdTdtHTotal +: xdptx_hw.h
  • XDptx_GetDispIdTdtNumTiles +: xdptx_hw.h
  • XDptx_GetDispIdTdtTileOrder +: xdptx_hw.h
  • XDptx_GetDispIdTdtVLoc +: xdptx_hw.h
  • XDptx_GetDispIdTdtVTotal +: xdptx_hw.h
  • XDPTX_GT_DRP_CHANNEL_STATUS +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK +: xdptx_hw.h
  • XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT +: xdptx_hw.h
  • XDPTX_GT_DRP_READ_DATA +: xdptx_hw.h
  • XDPTX_HPD_DURATION +: xdptx_hw.h
  • XDptx_In32 +: xdptx_hw.h
  • XDPTX_INIT_WAIT +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK +: xdptx_hw.h
  • XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK +: xdptx_hw.h
  • XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT +: xdptx.c
  • XDptx_IsEdidExtBlockDispId +: xdptx_hw.h
  • XDPTX_LANE_COUNT_SET +: xdptx_hw.h
  • XDPTX_LANE_COUNT_SET_1 +: xdptx_hw.h
  • XDPTX_LANE_COUNT_SET_2 +: xdptx_hw.h
  • XDPTX_LANE_COUNT_SET_4 +: xdptx_hw.h
  • XDPTX_LINK_BW_SET +: xdptx_hw.h
  • XDPTX_LINK_BW_SET_162GBPS +: xdptx_hw.h
  • XDPTX_LINK_BW_SET_270GBPS +: xdptx_hw.h
  • XDPTX_LINK_BW_SET_540GBPS +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET_OFF +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET_PRBS7 +: xdptx_hw.h
  • XDPTX_LINK_QUAL_PATTERN_SET_SER_MES +: xdptx_hw.h
  • XDPTX_M_VID +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_HRES +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_HSTART +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_HSWIDTH +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_HTOTAL +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_INTERLACED +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_MISC0 +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_MISC1 +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_POLARITY +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_VRES +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_VSTART +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_VSWIDTH +: xdptx_hw.h
  • XDPTX_MAIN_STREAM_VTOTAL +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK +: xdptx_hw.h
  • XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT +: xdptx_hw.h
  • XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT +: xdptx_mst.c
  • XDPTX_MAXIMUM_PE_LEVEL +: xdptx.c
  • XDPTX_MAXIMUM_VS_LEVEL +: xdptx.c
  • XDPTX_MIN_BYTES_PER_TU +: xdptx_hw.h
  • XDPTX_N_VID +: xdptx_hw.h
  • XDptx_Out32 +: xdptx_hw.h
  • XDPTX_PE_LEVEL_0 +: xdptx_hw.h
  • XDPTX_PE_LEVEL_1 +: xdptx_hw.h
  • XDPTX_PE_LEVEL_2 +: xdptx_hw.h
  • XDPTX_PE_LEVEL_3 +: xdptx_hw.h
  • XDPTX_PHY_CLOCK_SELECT +: xdptx_hw.h
  • XDPTX_PHY_CLOCK_SELECT_162GBPS +: xdptx_hw.h
  • XDPTX_PHY_CLOCK_SELECT_270GBPS +: xdptx_hw.h
  • XDPTX_PHY_CLOCK_SELECT_540GBPS +: xdptx_hw.h
  • XDPTX_PHY_CONFIG +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_GTTX_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_PHY_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK +: xdptx_hw.h
  • XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK +: xdptx_hw.h
  • XDPTX_PHY_POSTCURSOR_LANE_0 +: xdptx_hw.h
  • XDPTX_PHY_POSTCURSOR_LANE_1 +: xdptx_hw.h
  • XDPTX_PHY_POSTCURSOR_LANE_2 +: xdptx_hw.h
  • XDPTX_PHY_POSTCURSOR_LANE_3 +: xdptx_hw.h
  • XDPTX_PHY_PRECURSOR_LANE_0 +: xdptx_hw.h
  • XDPTX_PHY_PRECURSOR_LANE_1 +: xdptx_hw.h
  • XDPTX_PHY_PRECURSOR_LANE_2 +: xdptx_hw.h
  • XDPTX_PHY_PRECURSOR_LANE_3 +: xdptx_hw.h
  • XDPTX_PHY_STATUS +: xdptx_hw.h
  • XDPTX_PHY_STATUS_ALL_LANES_READY_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_LANES_0_1_READY_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK +: xdptx_hw.h
  • XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT +: xdptx_hw.h
  • XDPTX_PHY_TRANSMIT_PRBS7 +: xdptx_hw.h
  • XDPTX_PHY_VOLTAGE_DIFF_LANE_0 +: xdptx_hw.h
  • XDPTX_PHY_VOLTAGE_DIFF_LANE_1 +: xdptx_hw.h
  • XDPTX_PHY_VOLTAGE_DIFF_LANE_2 +: xdptx_hw.h
  • XDPTX_PHY_VOLTAGE_DIFF_LANE_3 +: xdptx_hw.h
  • XDptx_ReadReg +: xdptx_hw.h
  • XDPTX_REPLY_DATA_COUNT +: xdptx_hw.h
  • XDPTX_REPLY_STATUS +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_ERROR_MASK +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT +: xdptx_hw.h
  • XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK +: xdptx_hw.h
  • XDPTX_SBMSG_ALLOCATE_PAYLOAD +: xdptx_hw.h
  • XDPTX_SBMSG_CLEAR_PAYLOAD_ID_TABLE +: xdptx_hw.h
  • XDPTX_SBMSG_ENUM_PATH_RESOURCES +: xdptx_hw.h
  • XDPTX_SBMSG_LINK_ADDRESS +: xdptx_hw.h
  • XDPTX_SBMSG_REMOTE_DPCD_READ +: xdptx_hw.h
  • XDPTX_SBMSG_REMOTE_DPCD_WRITE +: xdptx_hw.h
  • XDPTX_SBMSG_REMOTE_I2C_READ +: xdptx_hw.h
  • XDPTX_SBMSG_REMOTE_I2C_WRITE +: xdptx_hw.h
  • XDPTX_SCRAMBLING_DISABLE +: xdptx_hw.h
  • XDPTX_SEGPTR_ADDR +: xdptx_hw.h
  • XDPTX_SOFT_RESET +: xdptx_hw.h
  • XDPTX_SOFT_RESET_AUX_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK +: xdptx_hw.h
  • XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK +: xdptx_hw.h
  • XDPTX_STREAM1 +: xdptx_hw.h
  • XDPTX_STREAM1_MSA_START +: xdptx_hw.h
  • XDPTX_STREAM2 +: xdptx_hw.h
  • XDPTX_STREAM2_MSA_START +: xdptx_hw.h
  • XDPTX_STREAM2_MSA_START_OFFSET +: xdptx_hw.h
  • XDPTX_STREAM3 +: xdptx_hw.h
  • XDPTX_STREAM3_MSA_START +: xdptx_hw.h
  • XDPTX_STREAM3_MSA_START_OFFSET +: xdptx_hw.h
  • XDPTX_STREAM4 +: xdptx_hw.h
  • XDPTX_STREAM4_MSA_START +: xdptx_hw.h
  • XDPTX_STREAM4_MSA_START_OFFSET +: xdptx_hw.h
  • XDPTX_STREAM_ID1 +: xdptx_hw.h
  • XDPTX_STREAM_ID2 +: xdptx_hw.h
  • XDPTX_STREAM_ID3 +: xdptx_hw.h
  • XDPTX_STREAM_ID4 +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET_OFF +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET_TP1 +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET_TP2 +: xdptx_hw.h
  • XDPTX_TRAINING_PATTERN_SET_TP3 +: xdptx_hw.h
  • XDPTX_TU_SIZE +: xdptx_hw.h
  • XDPTX_TX_AUDIO_CHANNELS +: xdptx_hw.h
  • XDPTX_TX_AUDIO_CONTROL +: xdptx_hw.h
  • XDPTX_TX_AUDIO_EXT_DATA +: xdptx_hw.h
  • XDPTX_TX_AUDIO_INFO_DATA +: xdptx_hw.h
  • XDPTX_TX_AUDIO_MAUD +: xdptx_hw.h
  • XDPTX_TX_AUDIO_NAUD +: xdptx_hw.h
  • XDPTX_TX_MST_CONFIG +: xdptx_hw.h
  • XDPTX_TX_MST_CONFIG_MST_EN_MASK +: xdptx_hw.h
  • XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK +: xdptx_hw.h
  • XDPTX_TX_PHY_POWER_DOWN +: xdptx_hw.h
  • XDPTX_TX_USER_FIFO_OVERFLOW +: xdptx_hw.h
  • XDPTX_USER_DATA_COUNT_PER_LANE +: xdptx_hw.h
  • XDPTX_USER_PIXEL_WIDTH +: xdptx_hw.h
  • XDPTX_VC_PAYLOAD_BUFFER_ADDR +: xdptx_hw.h
  • XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT +: xdptx_mst.c
  • XDPTX_VERSION +: xdptx_hw.h
  • XDPTX_VERSION_CORE_PATCH_MASK +: xdptx_hw.h
  • XDPTX_VERSION_CORE_PATCH_SHIFT +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_MJR_MASK +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_MJR_SHIFT +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_MNR_MASK +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_MNR_SHIFT +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_REV_MASK +: xdptx_hw.h
  • XDPTX_VERSION_CORE_VER_REV_SHIFT +: xdptx_hw.h
  • XDPTX_VERSION_INTER_REV_MASK +: xdptx_hw.h
  • XDPTX_VS_LEVEL_0 +: xdptx_hw.h
  • XDPTX_VS_LEVEL_1 +: xdptx_hw.h
  • XDPTX_VS_LEVEL_2 +: xdptx_hw.h
  • XDPTX_VS_LEVEL_3 +: xdptx_hw.h
  • XDPTX_VS_LEVEL_OFFSET +: xdptx_hw.h
  • XDptx_WriteReg +: xdptx_hw.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_enum.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_enum.html index 586ce7c1..867aa2c1 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_enum.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_enum.html @@ -36,6 +36,5 @@

    +: xdptx.c Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_eval.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_eval.html index 905c867e..846cb328 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_eval.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_eval.html @@ -32,109 +32,14 @@
  • Defines
  • -
    -
      -
    • x
    • -
    -
    - -

     

    -

    - x -

    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html index e83958c6..532f571f 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html @@ -43,82 +43,82 @@

    - x -

    +: xdptx_mst.c, xdptx.h
  • XDptx_AllocatePayloadVcIdTable() +: xdptx_mst.c, xdptx.h
  • XDptx_AuxRead() +: xdptx.h, xdptx.c
  • XDptx_AuxWrite() +: xdptx.h, xdptx.c
  • XDptx_CfgInitialize() +: xdptx.h, xdptx.c
  • XDptx_CfgMainLinkMax() +: xdptx.h, xdptx.c
  • XDptx_CfgMsaEnSynchClkMode() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaRecalculate() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaSetBpc() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaUseCustom() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaUseEdidPreferredTiming() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgMsaUseStandardVideoMode() +: xdptx_spm.c, xdptx.h
  • XDptx_CfgTxPeLevel() +: xdptx.h, xdptx.c
  • XDptx_CfgTxVsLevel() +: xdptx.h, xdptx.c
  • XDptx_CfgTxVsOffset() +: xdptx.h, xdptx.c
  • XDptx_CheckLinkStatus() +: xdptx.h, xdptx.c
  • XDptx_ClearMsaValues() +: xdptx_spm.c, xdptx.h
  • XDptx_ClearPayloadVcIdTable() +: xdptx_mst.c, xdptx.h
  • XDptx_DisableMainLink() +: xdptx.h, xdptx.c
  • XDptx_DiscoverTopology() +: xdptx_mst.c, xdptx.h
  • XDptx_EnableMainLink() +: xdptx.h, xdptx.c
  • XDptx_EnableTrainAdaptive() +: xdptx.h, xdptx.c
  • XDptx_EstablishLink() +: xdptx.h, xdptx.c
  • XDptx_FindAccessibleDpDevices() +: xdptx_mst.c, xdptx.h
  • XDptx_GetDispIdDataBlock() +: xdptx_edid.c, xdptx.h
  • XDptx_GetEdid() +: xdptx_edid.c, xdptx.h
  • XDptx_GetEdidBlock() +: xdptx_edid.c, xdptx.h
  • XDptx_GetGuid() +: xdptx_mst.c, xdptx.h
  • XDptx_GetRemoteEdid() +: xdptx_edid.c, xdptx.h
  • XDptx_GetRemoteEdidBlock() +: xdptx_edid.c, xdptx.h
  • XDptx_GetRemoteEdidDispIdExt() +: xdptx_edid.c, xdptx.h
  • XDptx_GetRemoteTiledDisplayDb() +: xdptx_edid.c, xdptx.h
  • XDptx_GetRxCapabilities() +: xdptx.h, xdptx.c
  • XDptx_HpdInterruptHandler() +: xdptx_intr.c, xdptx.h
  • XDptx_IicRead() +: xdptx.h, xdptx.c
  • XDptx_IicWrite() +: xdptx.h, xdptx.c
  • XDptx_InitializeTx() +: xdptx.h, xdptx.c
  • XDptx_IsConnected() +: xdptx.h, xdptx.c
  • XDptx_LookupConfig() +: xdptx_sinit.c, xdptx.h
  • XDptx_MstCapable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstCfgModeDisable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstCfgModeEnable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstCfgStreamDisable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstCfgStreamEnable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstDisable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstEnable() +: xdptx_mst.c, xdptx.h
  • XDptx_MstStreamIsEnabled() +: xdptx_mst.c, xdptx.h
  • XDptx_RemoteDpcdRead() +: xdptx_mst.c, xdptx.h
  • XDptx_RemoteDpcdWrite() +: xdptx_mst.c, xdptx.h
  • XDptx_RemoteIicRead() +: xdptx_mst.c, xdptx.h
  • XDptx_RemoteIicWrite() +: xdptx_mst.c, xdptx.h
  • XDptx_ResetPhy() +: xdptx.h, xdptx.c
  • XDptx_SelfTest() +: xdptx_selftest.c, xdptx.h
  • XDptx_SendSbMsgAllocatePayload() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgClearPayloadIdTable() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgEnumPathResources() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgLinkAddress() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgRemoteDpcdRead() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgRemoteDpcdWrite() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgRemoteIicRead() +: xdptx_mst.c, xdptx.h
  • XDptx_SendSbMsgRemoteIicWrite() +: xdptx_mst.c, xdptx.h
  • XDptx_SetDownspread() +: xdptx.h, xdptx.c
  • XDptx_SetEnhancedFrameMode() +: xdptx.h, xdptx.c
  • XDptx_SetHasRedriverInPath() +: xdptx.h, xdptx.c
  • XDptx_SetHpdEventHandler() +: xdptx_intr.c, xdptx.h
  • XDptx_SetHpdPulseHandler() +: xdptx_intr.c, xdptx.h
  • XDptx_SetLaneCount() +: xdptx.h, xdptx.c
  • XDptx_SetLinkRate() +: xdptx.h, xdptx.c
  • XDptx_SetMsaValues() +: xdptx_spm.c, xdptx.h
  • XDptx_SetScrambler() +: xdptx.h, xdptx.c
  • XDptx_SetStreamSelectFromSinkList() +: xdptx_mst.c, xdptx.h
  • XDptx_SetStreamSinkRad() +: xdptx_mst.c, xdptx.h
  • XDptx_SetUserTimerHandler() +: xdptx.h, xdptx.c
  • XDptx_SetVideoMode() +: xdptx_spm.c, xdptx.h
  • XDptx_TopologySortSinksByTiling() +: xdptx_mst.c, xdptx.h
  • XDptx_TopologySwapSinks() +: xdptx_mst.c, xdptx.h
  • XDptx_WaitUs() +: xdptx.h, xdptx.c
  • XDptx_WriteGuid() +: xdptx_mst.c, xdptx.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_type.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_type.html index 8aac67dc..0d148352 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_type.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_type.html @@ -36,7 +36,7 @@

    +: xdptx.h
  • XDptx_HpdPulseHandler +: xdptx.h
  • XDptx_TimerHandler +: xdptx.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_vars.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_vars.html index 6aff945f..b7176e25 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_vars.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_vars.html @@ -36,9 +36,8 @@

    +: xdptx_mst.c
  • ResetValues +: xdptx_selftest.c
  • ResetValuesMsa +: xdptx_selftest.c
  • XDptx_ConfigTable +: xdptx_sinit.c Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html index f7764e5f..852f375a 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html @@ -2,7 +2,7 @@ - dptx v3_0 + Main Page @@ -16,52 +16,6 @@
  • Classes
  • Files
  • -

    dptx v3_0

    +

    -The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the DisplayPort 1.2a specification.

    -The Xilinx DisplayPort soft IP supports the following features:

    -

    -The Xilinx DisplayPort soft IP does not support the following features:

    -

    -DisplayPort overview

    -A DisplayPort link consists of:

    -

    -Driver description

    -The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort TX soft IP, communicate and control an RX device/sink monitor over the AUX channel, and to initialize and transmit data streams over the main link.

    -This driver implements link layer functionality: a Link Policy Maker (LPM) and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.

    -

    -Using AUX transactions to read/write from/to the sink's DisplayPort Configuration Data (DPCD) address space, the LPM obtains the link capabilities, obtains link configuration and link and sink status, and configures and controls the link and sink. The main link is trained this way.

    -I2C-over-AUX transactions are used to obtain the sink's Extended Display Identification Data (EDID) which give information on the display capabilities of the monitor. The SPM may use this information to determine what available screen resolutions and video timing are possible.

    -Device configuration

    -The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the xdptx_g.c file which is generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the DisplayPort instances present in the system. This information includes parameters that are defined in the driver's data/dptx.tcl file such as the base address of the memory-mapped device and the maximum number of lanes, maximum link rate, and video interface that the DisplayPort instance supports, among others.

    -Interrupt processing

    -DisplayPort interrupts occur on the HPD signal line when the DisplayPort cable is connected/disconnected or when the RX device sends a pulse. The user hardware design must contain an interrupt controller which the DisplayPort TX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts. When the XDptx_HpdInterruptHandler function is invoked, the handler will identify what type of DisplayPort interrupt has occurred, and will call either the HPD event handler function or the HPD pulse handler function, depending on whether a an HPD event on an HPD pulse event occurred.

    -The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of interrupt that has occured, and the XDptx_HpdInterruptHandler will use this information to decide which handler to call. An HPD event is identified if bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.

    -The HPD event handler may be set up by using the XDptx_SetHpdEventHandler function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler function.

    -Multi-stream transport (MST) mode

    -The driver handles MST mode functionality, including sideband messaging, topology discovery, virtual channel payload ID table management, and directing streams to different sinks.

    -MST testing has been done at 5.40Gbps per 4 lanes, with 4 sinks in a daisy- chain configuration, with each stream having the same resolution. Testing has been done at the following resolutions: 640x480, 720x480, 800x600, 848x480, 1024x768, 1280x720, 1280x1024, 1080p, and UHD (UHD/2 on 2 streams). Each resolutions was tested at 24 bits per pixel using 1, 2, 3, and 4 streams. Color depths of 18, 30, 36, and 48 bits per pixel were also tested.

    -Audio

    -The driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.

    -Asserts

    -Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.

    -Limitations and known issues

    -

    -

    -

    Note:
    For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.
    -
    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
    - ----- ---- -------- -----------------------------------------------
    - 1.0   als  05/17/14 Initial release.
    -       als  08/03/14 Initial MST addition.
    - 2.0   als  09/21/14 Added XDptx_DiscoverTopology function and changed
    -                     XDptx_IsConnected from macro to function.
    - 
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html index bbab7dff..afead409 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html @@ -22,22 +22,22 @@
  • Class Members
  • XDptx Member List

    This is the complete list of members for XDptx, including all inherited members.

    - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + +
    AuxDelayUsXDptx
    BoardCharXDptx
    ConfigXDptx
    HpdEventCallbackRefXDptx
    HpdEventHandlerXDptx
    HpdPulseCallbackRefXDptx
    HpdPulseHandlerXDptx
    IsReadyXDptx
    LinkConfigXDptx
    MsaConfigXDptx
    MstEnableXDptx
    MstStreamConfigXDptx
    RxConfigXDptx
    SbMsgDelayUsXDptx
    TopologyXDptx
    TrainAdaptiveXDptx
    UserTimerPtrXDptx
    UserTimerWaitUsXDptx
    AuxDelayUsXDptx
    BoardCharXDptx
    ConfigXDptx
    HpdEventCallbackRefXDptx
    HpdEventHandlerXDptx
    HpdPulseCallbackRefXDptx
    HpdPulseHandlerXDptx
    IsReadyXDptx
    LinkConfigXDptx
    MsaConfigXDptx
    MstEnableXDptx
    MstStreamConfigXDptx
    RxConfigXDptx
    SbMsgDelayUsXDptx
    TopologyXDptx
    TrainAdaptiveXDptx
    UserTimerPtrXDptx
    UserTimerWaitUsXDptx
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html index 1d77c2ae..420b50aa 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html @@ -29,305 +29,305 @@ The XDptx driver instance data. The - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +

    Public Attributes

    u32 MstEnable
    u32 MstEnable
    u32 IsReady
    u32 IsReady
    u8 TrainAdaptive
    u8 TrainAdaptive
    XDptx_Config Config
    XDptx_Config Config
    XDptx_SinkConfig RxConfig
    XDptx_SinkConfig RxConfig
    XDptx_LinkConfig LinkConfig
    XDptx_LinkConfig LinkConfig
    XDptx_BoardChar BoardChar
    XDptx_BoardChar BoardChar
    XDptx_MainStreamAttributes MsaConfig [4]
    XDptx_MainStreamAttributes MsaConfig [4]
    XDptx_MstStream MstStreamConfig [4]
    XDptx_MstStream MstStreamConfig [4]
    XDptx_Topology Topology
    XDptx_Topology Topology
    u32 AuxDelayUs
    u32 AuxDelayUs
    u32 SbMsgDelayUs
    u32 SbMsgDelayUs
    XDptx_TimerHandler UserTimerWaitUs
    XDptx_TimerHandler UserTimerWaitUs
    void * UserTimerPtr
    void * UserTimerPtr
    XDptx_HpdEventHandler HpdEventHandler
    XDptx_HpdEventHandler HpdEventHandler
    void * HpdEventCallbackRef
    void * HpdEventCallbackRef
    XDptx_HpdPulseHandler HpdPulseHandler
    XDptx_HpdPulseHandler HpdPulseHandler
    void * HpdPulseCallbackRef
    void * HpdPulseCallbackRef


    Member Data Documentation

    - +

    -Amount of latency in micro- seconds to use between AUX transactions. +Amount of latency in micro- seconds to use between AUX transactions.

    - +

    -Some board characteristics information that affects link training. +Some board characteristics information that affects link training.

    - +

    -Configuration structure for the DisplayPort TX core. +Configuration structure for the DisplayPort TX core.

    - +

    -A pointer to the user data passed to the HPD event callback function. +A pointer to the user data passed to the HPD event callback function.

    - +

    -Callback function for Hot- Plug-Detect (HPD) event interrupts. +Callback function for Hot- Plug-Detect (HPD) event interrupts.

    - +

    -A pointer to the user data passed to the HPD pulse callback function. +A pointer to the user data passed to the HPD pulse callback function.

    - +

    -Callback function for Hot- Plug-Detect (HPD) pulse interrupts. +Callback function for Hot- Plug-Detect (HPD) pulse interrupts.

    - +

    -Device is initialized and ready. +Device is initialized and ready.

    - +

    -Configuration structure for the main link. +Configuration structure for the main link.

    - +

    -Configuration structure for the main stream attributes (MSA). Each stream has its own set of attributes. When MST mode is disabled, only MsaConfig[0] is used. +Configuration structure for the main stream attributes (MSA). Each stream has its own set of attributes. When MST mode is disabled, only MsaConfig[0] is used.

    - +

    -Multi-stream transport (MST) mode. Enables functionality, allowing multiple streams to be sent over the main link. +Multi-stream transport (MST) mode. Enables functionality, allowing multiple streams to be sent over the main link.

    - +

    -Configuration structure for a multi-stream transport (MST) stream. +Configuration structure for a multi-stream transport (MST) stream.

    - +

    -Configuration structure for the RX device. +Configuration structure for the RX device.

    - +

    -Amount of latency in micro- seconds to use between sideband messages for multi-stream transport (MST) mode. +Amount of latency in micro- seconds to use between sideband messages for multi-stream transport (MST) mode.

    - +

    -The topology of connected downstream DisplayPort devices when the driver is running in MST mode. +The topology of connected downstream DisplayPort devices when the driver is running in MST mode.

    - +

    -Downshift lane count and link rate if necessary during training. +Downshift lane count and link rate if necessary during training.

    - +

    -Pointer to a timer instance used by the custom user delay/sleep function. +Pointer to a timer instance used by the custom user delay/sleep function.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction-members.html index 61dc43f5..de3434c8 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction-members.html @@ -22,8 +22,8 @@
  • Class Members
  • XDptx_AuxTransaction Member List

    This is the complete list of members for XDptx_AuxTransaction, including all inherited members.

    - - - - + + + +
    AddressXDptx_AuxTransaction
    CmdCodeXDptx_AuxTransaction
    DataXDptx_AuxTransaction
    NumBytesXDptx_AuxTransaction
    AddressXDptx_AuxTransaction
    CmdCodeXDptx_AuxTransaction
    DataXDptx_AuxTransaction
    NumBytesXDptx_AuxTransaction
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction.html index 1ad6a77a..a04721bb 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction.html @@ -27,67 +27,67 @@ This typedef describes an AUX transaction. - + - + - + - +

    Public Attributes

    u16 CmdCode
    u16 CmdCode
    u8 NumBytes
    u8 NumBytes
    u32 Address
    u32 Address
    u8 * Data
    u8 * Data


    Member Data Documentation

    - +

    -The AUX or I2C start address that the AUX transaction will perform work on. +The AUX or I2C start address that the AUX transaction will perform work on.

    - +

    -The AUX command code that specifies what type of AUX transaction is taking place. +The AUX command code that specifies what type of AUX transaction is taking place.

    - +

    -The data buffer that will store the data read from AUX read transactions or the data to write for AUX write transactions. +The data buffer that will store the data read from AUX read transactions or the data to write for AUX write transactions.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___board_char-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___board_char-members.html index c62bae4b..78962a54 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___board_char-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___board_char-members.html @@ -22,8 +22,8 @@
  • Class Members
  • XDptx_BoardChar Member List

    This is the complete list of members for XDptx_BoardChar, including all inherited members.

    - - - - + + + +
    HasRedriverInPathXDptx_BoardChar
    TxPeLevelsXDptx_BoardChar
    TxVsLevelsXDptx_BoardChar
    TxVsOffsetXDptx_BoardChar
    HasRedriverInPathXDptx_BoardChar
    TxPeLevelsXDptx_BoardChar
    TxVsLevelsXDptx_BoardChar
    TxVsOffsetXDptx_BoardChar
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___board_char.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___board_char.html index eb839bd6..2ab2050e 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___board_char.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___board_char.html @@ -29,67 +29,67 @@ This typedef describes some board characteristics information that affects link - + - + - + - +

    Public Attributes

    u8 HasRedriverInPath
    u8 HasRedriverInPath
    u8 TxVsLevels [4]
    u8 TxVsLevels [4]
    u8 TxPeLevels [4]
    u8 TxPeLevels [4]
    u8 TxVsOffset
    u8 TxVsOffset


    Member Data Documentation

    - +

    -Redriver in path requires different voltage swing and pre-emphasis. +Redriver in path requires different voltage swing and pre-emphasis.

    - +

    -The pre-emphasis/cursor level to be used by the DisplayPort TX. +The pre-emphasis/cursor level to be used by the DisplayPort TX.

    - +

    -The voltage swing levels to be used by the DisplayPort TX. +The voltage swing levels to be used by the DisplayPort TX.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html index 83d8c501..3bee8ad5 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html @@ -22,20 +22,20 @@
  • Class Members
  • XDptx_Config Member List

    This is the complete list of members for XDptx_Config, including all inherited members.

    - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + +
    BaseAddrXDptx_Config
    DeviceIdXDptx_Config
    DpProtocolXDptx_Config
    DualPixelEnXDptx_Config
    MaxBitsPerColorXDptx_Config
    MaxLaneCountXDptx_Config
    MaxLinkRateXDptx_Config
    MstSupportXDptx_Config
    NumAudioChsXDptx_Config
    NumMstStreamsXDptx_Config
    PayloadDataWidthXDptx_Config
    QuadPixelEnXDptx_Config
    SAxiClkHzXDptx_Config
    SecondaryChEnXDptx_Config
    YCrCbEnXDptx_Config
    YOnlyEnXDptx_Config
    BaseAddrXDptx_Config
    DeviceIdXDptx_Config
    DpProtocolXDptx_Config
    DualPixelEnXDptx_Config
    MaxBitsPerColorXDptx_Config
    MaxLaneCountXDptx_Config
    MaxLinkRateXDptx_Config
    MstSupportXDptx_Config
    NumAudioChsXDptx_Config
    NumMstStreamsXDptx_Config
    PayloadDataWidthXDptx_Config
    QuadPixelEnXDptx_Config
    SAxiClkHzXDptx_Config
    SecondaryChEnXDptx_Config
    YCrCbEnXDptx_Config
    YOnlyEnXDptx_Config
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html index 3fb0284c..32569d1e 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html @@ -29,271 +29,271 @@ This typedef contains configuration information for the DisplayPort TX core. - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +

    Public Attributes

    u16 DeviceId
    u16 DeviceId
    u32 BaseAddr
    u32 BaseAddr
    u32 SAxiClkHz
    u32 SAxiClkHz
    u8 MaxLaneCount
    u8 MaxLaneCount
    u8 MaxLinkRate
    u8 MaxLinkRate
    u8 MaxBitsPerColor
    u8 MaxBitsPerColor
    u8 QuadPixelEn
    u8 QuadPixelEn
    u8 DualPixelEn
    u8 DualPixelEn
    u8 YCrCbEn
    u8 YCrCbEn
    u8 YOnlyEn
    u8 YOnlyEn
    u8 PayloadDataWidth
    u8 PayloadDataWidth
    u8 SecondaryChEn
    u8 SecondaryChEn
    u8 NumAudioChs
    u8 NumAudioChs
    u8 MstSupport
    u8 MstSupport
    u8 NumMstStreams
    u8 NumMstStreams
    u8 DpProtocol
    u8 DpProtocol


    Member Data Documentation

    - +

    -The base address of the core instance. +The base address of the core instance.

    - +

    -Device instance ID. +Device instance ID.

    - +

    -The DisplayPort protocol version that this core instance is configured for. 0 = v1.1a, 1 = v1.2. +The DisplayPort protocol version that this core instance is configured for. 0 = v1.1a, 1 = v1.2.

    - +

    -Dual pixel support by this core instance. +Dual pixel support by this core instance.

    - +

    -The maximum bits/color supported by this core instance +The maximum bits/color supported by this core instance

    - +

    -The maximum lane count supported by this core instance. +The maximum lane count supported by this core instance.

    - +

    -The maximum link rate supported by this core instance. +The maximum link rate supported by this core instance.

    - +

    -Multi-stream transport (MST) mode is enabled by this core instance. +Multi-stream transport (MST) mode is enabled by this core instance.

    - +

    -The number of audio channels supported by this core instance. +The number of audio channels supported by this core instance.

    - +

    -The total number of MST streams supported by this core instance. +The total number of MST streams supported by this core instance.

    - +

    -The payload data width used by this core instance. +The payload data width used by this core instance.

    - +

    -Quad pixel support by this core instance. +Quad pixel support by this core instance.

    - +

    -The clock frequency of the core instance's S_AXI_ACLK port. +The clock frequency of the core instance's S_AXI_ACLK port.

    - +

    -This core instance supports audio packets being sent by the secondary channel. +This core instance supports audio packets being sent by the secondary channel.

    - +

    -YCrCb format support by this core instance. +YCrCb format support by this core instance.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config-members.html index 77af296e..94bbdb7a 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config-members.html @@ -22,16 +22,16 @@
  • Class Members
  • XDptx_LinkConfig Member List

    This is the complete list of members for XDptx_LinkConfig, including all inherited members.

    - - - - - - - - - - - - + + + + + + + + + + + +
    DownspreadControlXDptx_LinkConfig
    EnhancedFramingModeXDptx_LinkConfig
    LaneCountXDptx_LinkConfig
    LinkRateXDptx_LinkConfig
    MaxLaneCountXDptx_LinkConfig
    MaxLinkRateXDptx_LinkConfig
    PatternXDptx_LinkConfig
    PeLevelXDptx_LinkConfig
    ScramblerEnXDptx_LinkConfig
    SupportDownspreadControlXDptx_LinkConfig
    SupportEnhancedFramingModeXDptx_LinkConfig
    VsLevelXDptx_LinkConfig
    DownspreadControlXDptx_LinkConfig
    EnhancedFramingModeXDptx_LinkConfig
    LaneCountXDptx_LinkConfig
    LinkRateXDptx_LinkConfig
    MaxLaneCountXDptx_LinkConfig
    MaxLinkRateXDptx_LinkConfig
    PatternXDptx_LinkConfig
    PeLevelXDptx_LinkConfig
    ScramblerEnXDptx_LinkConfig
    SupportDownspreadControlXDptx_LinkConfig
    SupportEnhancedFramingModeXDptx_LinkConfig
    VsLevelXDptx_LinkConfig
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config.html index e8f77ab9..d7f3fd63 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config.html @@ -29,203 +29,203 @@ This typedef contains configuration information about the main link settings. - + - + - + - + - + - + - + - + - + - + - + - +

    Public Attributes

    u8 LaneCount
    u8 LaneCount
    u8 LinkRate
    u8 LinkRate
    u8 ScramblerEn
    u8 ScramblerEn
    u8 EnhancedFramingMode
    u8 EnhancedFramingMode
    u8 DownspreadControl
    u8 DownspreadControl
    u8 MaxLaneCount
    u8 MaxLaneCount
    u8 MaxLinkRate
    u8 MaxLinkRate
    u8 SupportEnhancedFramingMode
    u8 SupportEnhancedFramingMode
    u8 SupportDownspreadControl
    u8 SupportDownspreadControl
    u8 VsLevel
    u8 VsLevel
    u8 PeLevel
    u8 PeLevel
    u8 Pattern
    u8 Pattern


    Member Data Documentation

    - +

    -Downspread control is currently in use over the main link. +Downspread control is currently in use over the main link.

    - +

    -Enhanced frame mode is currently in use over the main link. +Enhanced frame mode is currently in use over the main link.

    - +

    -The current lane count of the main link. +The current lane count of the main link.

    - +

    -The current link rate of the main link. +The current link rate of the main link.

    - +

    -The maximum lane count of the main link. +The maximum lane count of the main link.

    - +

    -The maximum link rate of the main link. +The maximum link rate of the main link.

    - +

    -The current pattern currently in use over the main link. +The current pattern currently in use over the main link.

    - +

    -The current pre-emphasis/cursor level for each lane. +The current pre-emphasis/cursor level for each lane.

    - +

    -Symbol scrambling is currently in use over the main link. +Symbol scrambling is currently in use over the main link.

    - +

    -Downspread control is supported by the RX device. +Downspread control is supported by the RX device.

    - +

    -Enhanced frame mode is supported by the RX device. +Enhanced frame mode is supported by the RX device.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html index 87d4a876..4ecff287 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html @@ -22,23 +22,23 @@
  • Class Members
  • XDptx_MainStreamAttributes Member List

    This is the complete list of members for XDptx_MainStreamAttributes, including all inherited members.

    - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + +
    AvgBytesPerTUXDptx_MainStreamAttributes
    BitsPerColorXDptx_MainStreamAttributes
    ComponentFormatXDptx_MainStreamAttributes
    DataPerLaneXDptx_MainStreamAttributes
    DmtXDptx_MainStreamAttributes
    DynamicRangeXDptx_MainStreamAttributes
    HClkTotalXDptx_MainStreamAttributes
    HStartXDptx_MainStreamAttributes
    InitWaitXDptx_MainStreamAttributes
    Misc0XDptx_MainStreamAttributes
    Misc1XDptx_MainStreamAttributes
    NVidXDptx_MainStreamAttributes
    OverrideUserPixelWidthXDptx_MainStreamAttributes
    SynchronousClockModeXDptx_MainStreamAttributes
    TransferUnitSizeXDptx_MainStreamAttributes
    UserPixelWidthXDptx_MainStreamAttributes
    VClkTotalXDptx_MainStreamAttributes
    VStartXDptx_MainStreamAttributes
    YCbCrColorimetryXDptx_MainStreamAttributes
    AvgBytesPerTUXDptx_MainStreamAttributes
    BitsPerColorXDptx_MainStreamAttributes
    ComponentFormatXDptx_MainStreamAttributes
    DataPerLaneXDptx_MainStreamAttributes
    DynamicRangeXDptx_MainStreamAttributes
    HClkTotalXDptx_MainStreamAttributes
    HStartXDptx_MainStreamAttributes
    InitWaitXDptx_MainStreamAttributes
    Misc0XDptx_MainStreamAttributes
    Misc1XDptx_MainStreamAttributes
    NVidXDptx_MainStreamAttributes
    OverrideUserPixelWidthXDptx_MainStreamAttributes
    SynchronousClockModeXDptx_MainStreamAttributes
    TransferUnitSizeXDptx_MainStreamAttributes
    UserPixelWidthXDptx_MainStreamAttributes
    VClkTotalXDptx_MainStreamAttributes
    VStartXDptx_MainStreamAttributes
    VtmXDptx_MainStreamAttributes
    YCbCrColorimetryXDptx_MainStreamAttributes
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html index 60d02dc2..e54f0cc4 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html @@ -29,322 +29,322 @@ This typedef contains the main stream attributes which determine how the video w - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +

    Public Attributes

    XDptx_DmtMode Dmt
    XVid_VideoTimingMode Vtm
    u32 HClkTotal
    u32 HClkTotal
    u32 VClkTotal
    u32 VClkTotal
    u32 HStart
    u32 HStart
    u32 VStart
    u32 VStart
    u32 Misc0
    u32 Misc0
    u32 Misc1
    u32 Misc1
    u32 NVid
    u32 NVid
    u32 UserPixelWidth
    u32 UserPixelWidth
    u32 DataPerLane
    u32 DataPerLane
    u32 AvgBytesPerTU
    u32 AvgBytesPerTU
    u32 TransferUnitSize
    u32 TransferUnitSize
    u32 InitWait
    u32 InitWait
    u32 BitsPerColor
    u32 BitsPerColor
    u8 ComponentFormat
    u8 ComponentFormat
    u8 DynamicRange
    u8 DynamicRange
    u8 YCbCrColorimetry
    u8 YCbCrColorimetry
    u8 SynchronousClockMode
    u8 SynchronousClockMode
    u8 OverrideUserPixelWidth
    u8 OverrideUserPixelWidth


    Member Data Documentation

    - +

    -Average number of bytes per transfer unit, scaled up by a factor of 1000. +Average number of bytes per transfer unit, scaled up by a factor of 1000.

    - +

    -Number of bits per color component. +Number of bits per color component.

    - +

    -The component format currently in use by the video stream. +The component format currently in use by the video stream.

    - +

    -Used to translate the number of pixels per line to the native internal 16-bit datapath. +Used to translate the number of pixels per line to the native internal 16-bit datapath.

    - +

    -Holds the set of Display Mode Timing (DMT) attributes that correspond to the information stored in the XDptx_DmtModes table. +The dynamic range currently in use by the video stream.

    - +

    -The dynamic range currently in use by the video stream. +Horizontal total time (in pixels).

    - +

    -Horizontal total time (in pixels). +Horizontal blank start (in pixels).

    - +

    -Horizontal blank start (in pixels). +Number of initial wait cycles at the start of a new line by the framing logic.

    - +

    -Number of initial wait cycles at the start of a new line by the framing logic. +Miscellaneous stream attributes 0 as specified by the DisplayPort 1.2 specification.

    - +

    -Miscellaneous stream attributes 0 as specified by the DisplayPort 1.2 specification. +Miscellaneous stream attributes 1 as specified by the DisplayPort 1.2 specification.

    - +

    -Miscellaneous stream attributes 1 as specified by the DisplayPort 1.2 specification. +N value for the video stream.

    - +

    -N value for the video stream. +If set to 1, the value stored for UserPixelWidth will be used as the pixel width.

    - +

    -If set to 1, the value stored for UserPixelWidth will be used as the pixel width. +Synchronous clock mode is currently in use by the video stream.

    - +

    -Synchronous clock mode is currently in use by the video stream. +Size of the transfer unit in the framing logic. In MST mode, this is also the number of time slots that are alloted in the payload ID table.

    - +

    -Size of the transfer unit in the framing logic. In MST mode, this is also the number of time slots that are alloted in the payload ID table. +The width of the user data input port.

    - +

    -The width of the user data input port. +Vertical total time (in pixels).

    - +

    -Vertical total time (in pixels). +Vertical blank start (in lines).

    - +

    -Vertical blank start (in lines). +The video timing.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___mst_stream-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___mst_stream-members.html index c546bab3..7a94481f 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___mst_stream-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___mst_stream-members.html @@ -22,8 +22,8 @@
  • Class Members
  • XDptx_MstStream Member List

    This is the complete list of members for XDptx_MstStream, including all inherited members.

    - - - - + + + +
    LinkCountTotalXDptx_MstStream
    MstPbnXDptx_MstStream
    MstStreamEnableXDptx_MstStream
    RelativeAddressXDptx_MstStream
    LinkCountTotalXDptx_MstStream
    MstPbnXDptx_MstStream
    MstStreamEnableXDptx_MstStream
    RelativeAddressXDptx_MstStream
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___mst_stream.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___mst_stream.html index e4b8283a..1e3c9bff 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___mst_stream.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___mst_stream.html @@ -29,22 +29,22 @@ This typedef describes a stream when the driver is running in multi-stream trans - + - + - + - +

    Public Attributes

    u8 LinkCountTotal
    u8 LinkCountTotal
    u8 RelativeAddress [15]
    u8 RelativeAddress [15]
    u16 MstPbn
    u16 MstPbn
    u8 MstStreamEnable
    u8 MstStreamEnable


    Member Data Documentation

    - +
    @@ -54,42 +54,42 @@ This typedef describes a stream when the driver is running in multi-stream trans

    - +

    -The relative address from the DisplayPort TX to the sink device that this MST stream is targeting. Payload bandwidth number used to allocate bandwidth for the MST stream. +The relative address from the DisplayPort TX to the sink device that this MST stream is targeting. Payload bandwidth number used to allocate bandwidth for the MST stream.

    - +

    -In MST mode, enables the corresponding stream for this MSA configuration. +In MST mode, enables the corresponding stream for this MSA configuration.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info-members.html index 14f0e01e..05f093d4 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info-members.html @@ -22,9 +22,9 @@
  • Class Members
  • XDptx_SbMsgLinkAddressReplyDeviceInfo Member List

    This is the complete list of members for XDptx_SbMsgLinkAddressReplyDeviceInfo, including all inherited members.

    - - - - - + + + + +
    GuidXDptx_SbMsgLinkAddressReplyDeviceInfo
    NumPortsXDptx_SbMsgLinkAddressReplyDeviceInfo
    PortDetailsXDptx_SbMsgLinkAddressReplyDeviceInfo
    ReplyTypeXDptx_SbMsgLinkAddressReplyDeviceInfo
    RequestIdXDptx_SbMsgLinkAddressReplyDeviceInfo
    GuidXDptx_SbMsgLinkAddressReplyDeviceInfo
    NumPortsXDptx_SbMsgLinkAddressReplyDeviceInfo
    PortDetailsXDptx_SbMsgLinkAddressReplyDeviceInfo
    ReplyTypeXDptx_SbMsgLinkAddressReplyDeviceInfo
    RequestIdXDptx_SbMsgLinkAddressReplyDeviceInfo
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info.html index 82376650..fb575bcb 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_device_info.html @@ -29,84 +29,84 @@ This typedef describes a DisplayPort branch device. This structure is used when - + - + - + - + - +

    Public Attributes

    u8 ReplyType
    u8 ReplyType
    u8 RequestId
    u8 RequestId
    u32 Guid [4]
    u32 Guid [4]
    u8 NumPorts
    u8 NumPorts
    XDptx_SbMsgLinkAddressReplyPortDetail PortDetails [16]
    XDptx_SbMsgLinkAddressReplyPortDetail PortDetails [16]


    Member Data Documentation

    - +

    -The global unique identifier (GUID) of the branch device. +The global unique identifier (GUID) of the branch device.

    - +

    -The number of ports associated with this branch device. +The number of ports associated with this branch device.

    - +

    -An array describing all ports attached to this branch device. +An array describing all ports attached to this branch device.

    - +

    -The reply type of the sideband message. A value of 1 indicates that the request wasn't successful and the return data will give the reason for a negative-acknowledge (NACK). +The reply type of the sideband message. A value of 1 indicates that the request wasn't successful and the return data will give the reason for a negative-acknowledge (NACK).

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail-members.html index f18b3102..4b2a0b51 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail-members.html @@ -22,14 +22,14 @@
  • Class Members
  • XDptx_SbMsgLinkAddressReplyPortDetail Member List

    This is the complete list of members for XDptx_SbMsgLinkAddressReplyPortDetail, including all inherited members.

    - - - - - - - - - - + + + + + + + + + +
    DpcdRevXDptx_SbMsgLinkAddressReplyPortDetail
    DpDevPlugStatusXDptx_SbMsgLinkAddressReplyPortDetail
    GuidXDptx_SbMsgLinkAddressReplyPortDetail
    InputPortXDptx_SbMsgLinkAddressReplyPortDetail
    LegacyDevPlugStatusXDptx_SbMsgLinkAddressReplyPortDetail
    MsgCapStatusXDptx_SbMsgLinkAddressReplyPortDetail
    NumSdpStreamsXDptx_SbMsgLinkAddressReplyPortDetail
    NumSdpStreamSinksXDptx_SbMsgLinkAddressReplyPortDetail
    PeerDeviceTypeXDptx_SbMsgLinkAddressReplyPortDetail
    PortNumXDptx_SbMsgLinkAddressReplyPortDetail
    DpcdRevXDptx_SbMsgLinkAddressReplyPortDetail
    DpDevPlugStatusXDptx_SbMsgLinkAddressReplyPortDetail
    GuidXDptx_SbMsgLinkAddressReplyPortDetail
    InputPortXDptx_SbMsgLinkAddressReplyPortDetail
    LegacyDevPlugStatusXDptx_SbMsgLinkAddressReplyPortDetail
    MsgCapStatusXDptx_SbMsgLinkAddressReplyPortDetail
    NumSdpStreamsXDptx_SbMsgLinkAddressReplyPortDetail
    NumSdpStreamSinksXDptx_SbMsgLinkAddressReplyPortDetail
    PeerDeviceTypeXDptx_SbMsgLinkAddressReplyPortDetail
    PortNumXDptx_SbMsgLinkAddressReplyPortDetail
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail.html index 971a96b1..442f4232 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sb_msg_link_address_reply_port_detail.html @@ -29,169 +29,169 @@ This typedef describes a port that is connected to a DisplayPort branch device. - + - + - + - + - + - + - + - + - + - +

    Public Attributes

    u8 InputPort
    u8 InputPort
    u8 PeerDeviceType
    u8 PeerDeviceType
    u8 PortNum
    u8 PortNum
    u8 MsgCapStatus
    u8 MsgCapStatus
    u8 DpDevPlugStatus
    u8 DpDevPlugStatus
    u8 LegacyDevPlugStatus
    u8 LegacyDevPlugStatus
    u8 DpcdRev
    u8 DpcdRev
    u32 Guid [4]
    u32 Guid [4]
    u8 NumSdpStreams
    u8 NumSdpStreams
    u8 NumSdpStreamSinks
    u8 NumSdpStreamSinks


    Member Data Documentation

    - +

    -The DisplayPort Configuration Data (DPCD) revision of the device connected to this port. +The DisplayPort Configuration Data (DPCD) revision of the device connected to this port.

    - +

    -There is a device connected to this port. +There is a device connected to this port.

    - +

    -The global unique identifier (GUID) of the device connected to this port. +The global unique identifier (GUID) of the device connected to this port.

    - +

    -Specifies that this port is an input port. +Specifies that this port is an input port.

    - +

    -This port is connected to a legacy device. +This port is connected to a legacy device.

    - +

    -This port or the device at this port can send and receive MST messages. +This port or the device at this port can send and receive MST messages.

    - +

    -The total number of Secondary-Data Packet (SDP) streams that this port can handle. +The total number of Secondary-Data Packet (SDP) streams that this port can handle.

    - +

    -The number of SDP streams associated with this port. +The number of SDP streams associated with this port.

    - +

    -Specifies the device type connected to this port. +Specifies the device type connected to this port.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg-members.html index b2108945..d259ab46 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg-members.html @@ -22,6 +22,6 @@
  • Class Members
  • XDptx_SidebandMsg Member List

    This is the complete list of members for XDptx_SidebandMsg, including all inherited members.

    - - + +
    BodyXDptx_SidebandMsg
    HeaderXDptx_SidebandMsg
    BodyXDptx_SidebandMsg
    HeaderXDptx_SidebandMsg
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg.html index a6642549..7c744e5c 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg.html @@ -27,33 +27,33 @@ This typedef stores the entire sideband message. - + - +

    Public Attributes

    XDptx_SidebandMsgHeader Header
    XDptx_SidebandMsgHeader Header
    XDptx_SidebandMsgBody Body
    XDptx_SidebandMsgBody Body


    Member Data Documentation

    - +

    -The body segment of the sideband message. +The body segment of the sideband message.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_body-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_body-members.html index 55706a36..34692097 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_body-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_body-members.html @@ -22,7 +22,7 @@
  • Class Members
  • XDptx_SidebandMsgBody Member List

    This is the complete list of members for XDptx_SidebandMsgBody, including all inherited members.

    - - - + + +
    CrcXDptx_SidebandMsgBody
    MsgDataXDptx_SidebandMsgBody
    MsgDataLengthXDptx_SidebandMsgBody
    CrcXDptx_SidebandMsgBody
    MsgDataXDptx_SidebandMsgBody
    MsgDataLengthXDptx_SidebandMsgBody
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_body.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_body.html index d1ae9a45..fcc5750b 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_body.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_body.html @@ -27,50 +27,50 @@ This typedef stores the sideband message body. - + - + - +

    Public Attributes

    u8 MsgData [62]
    u8 MsgData [62]
    u8 MsgDataLength
    u8 MsgDataLength
    u8 Crc
    u8 Crc


    Member Data Documentation

    - +

    -The cyclic-redundancy check (CRC) value of the body data. +The cyclic-redundancy check (CRC) value of the body data.

    - +

    -The raw body data of the sideband message. +The raw body data of the sideband message.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_header-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_header-members.html index 2f4cf629..7e1d48b3 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_header-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_header-members.html @@ -22,15 +22,15 @@
  • Class Members
  • XDptx_SidebandMsgHeader Member List

    This is the complete list of members for XDptx_SidebandMsgHeader, including all inherited members.

    - - - - - - - - - - - + + + + + + + + + + +
    BroadcastMsgXDptx_SidebandMsgHeader
    CrcXDptx_SidebandMsgHeader
    EndOfMsgTransactionXDptx_SidebandMsgHeader
    LinkCountRemainingXDptx_SidebandMsgHeader
    LinkCountTotalXDptx_SidebandMsgHeader
    MsgBodyLengthXDptx_SidebandMsgHeader
    MsgHeaderLengthXDptx_SidebandMsgHeader
    MsgSequenceNumXDptx_SidebandMsgHeader
    PathMsgXDptx_SidebandMsgHeader
    RelativeAddressXDptx_SidebandMsgHeader
    StartOfMsgTransactionXDptx_SidebandMsgHeader
    BroadcastMsgXDptx_SidebandMsgHeader
    CrcXDptx_SidebandMsgHeader
    EndOfMsgTransactionXDptx_SidebandMsgHeader
    LinkCountRemainingXDptx_SidebandMsgHeader
    LinkCountTotalXDptx_SidebandMsgHeader
    MsgBodyLengthXDptx_SidebandMsgHeader
    MsgHeaderLengthXDptx_SidebandMsgHeader
    MsgSequenceNumXDptx_SidebandMsgHeader
    PathMsgXDptx_SidebandMsgHeader
    RelativeAddressXDptx_SidebandMsgHeader
    StartOfMsgTransactionXDptx_SidebandMsgHeader
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_header.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_header.html index af809f2d..4af75e8c 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_header.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_msg_header.html @@ -27,186 +27,186 @@ This typedef stores the sideband message header. - + - + - + - + - + - + - + - + - + - + - +

    Public Attributes

    u8 LinkCountTotal
    u8 LinkCountTotal
    u8 LinkCountRemaining
    u8 LinkCountRemaining
    u8 RelativeAddress [15]
    u8 RelativeAddress [15]
    u8 BroadcastMsg
    u8 BroadcastMsg
    u8 PathMsg
    u8 PathMsg
    u8 MsgBodyLength
    u8 MsgBodyLength
    u8 StartOfMsgTransaction
    u8 StartOfMsgTransaction
    u8 EndOfMsgTransaction
    u8 EndOfMsgTransaction
    u8 MsgSequenceNum
    u8 MsgSequenceNum
    u8 Crc
    u8 Crc
    u8 MsgHeaderLength
    u8 MsgHeaderLength


    Member Data Documentation

    - +

    -Specifies that this message is a broadcast message, to be handled by all downstream devices. +Specifies that this message is a broadcast message, to be handled by all downstream devices.

    - +

    -The cyclic-redundancy check (CRC) value of the header data. +The cyclic-redundancy check (CRC) value of the header data.

    - +

    -This message is the last sideband message in the transaction. +This message is the last sideband message in the transaction.

    - +

    -The remaining link count until the sideband message reaches the target device. +The remaining link count until the sideband message reaches the target device.

    - +

    -The total number of DisplayPort links connecting the device device that this sideband message is targeted from the DisplayPort TX. +The total number of DisplayPort links connecting the device device that this sideband message is targeted from the DisplayPort TX.

    - +

    -The total number of data bytes that are stored in the sideband message body. +The total number of data bytes that are stored in the sideband message body.

    - +

    -The number of data bytes stored as part of the sideband message header. +The number of data bytes stored as part of the sideband message header.

    - +

    -Identifies invidiual message transactions to a given DisplayPort device. +Identifies invidiual message transactions to a given DisplayPort device.

    - +

    -Specifies that this message is a path message, to be handled by all the devices between the origin and the target device. +Specifies that this message is a path message, to be handled by all the devices between the origin and the target device.

    - +

    -The relative address from the DisplayPort TX to the target device. +The relative address from the DisplayPort TX to the target device.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply-members.html index b0c07712..c6a47ce2 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply-members.html @@ -22,6 +22,6 @@
  • Class Members
  • XDptx_SidebandReply Member List

    This is the complete list of members for XDptx_SidebandReply, including all inherited members.

    - - + +
    DataXDptx_SidebandReply
    LengthXDptx_SidebandReply
    DataXDptx_SidebandReply
    LengthXDptx_SidebandReply
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply.html index f73e5a50..ffa04478 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sideband_reply.html @@ -27,33 +27,33 @@ This typedef describes a sideband message reply. - + - +

    Public Attributes

    u8 Length
    u8 Length
    u8 Data [256]
    u8 Data [256]


    Member Data Documentation

    - +

    -The raw reply data. +The raw reply data.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config-members.html index b0f7a448..56beeede 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config-members.html @@ -22,6 +22,6 @@
  • Class Members
  • XDptx_SinkConfig Member List

    This is the complete list of members for XDptx_SinkConfig, including all inherited members.

    - - + +
    DpcdRxCapsFieldXDptx_SinkConfig
    LaneStatusAdjReqsXDptx_SinkConfig
    DpcdRxCapsFieldXDptx_SinkConfig
    LaneStatusAdjReqsXDptx_SinkConfig
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config.html index ce0426ed..4c6ecfbd 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config.html @@ -29,33 +29,33 @@ This typedef contains configuration information about the RX device. - + - +

    Public Attributes

    u8 DpcdRxCapsField [XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE]
    u8 DpcdRxCapsField [16]
    u8 LaneStatusAdjReqs [6]
    u8 LaneStatusAdjReqs [6]


    Member Data Documentation

    - +
    - +
    u8 XDptx_SinkConfig::DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE] u8 XDptx_SinkConfig::DpcdRxCapsField[16]

    -The raw capabilities field of the RX device's DisplayPort Configuration Data (DPCD). +The first 16 bytes of the raw capabilities field of the RX device's DisplayPort Configuration Data (DPCD).

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology-members.html index 3dd8262a..5810aa93 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology-members.html @@ -22,8 +22,8 @@
  • Class Members
  • XDptx_Topology Member List

    This is the complete list of members for XDptx_Topology, including all inherited members.

    - - - - + + + +
    NodeTableXDptx_Topology
    NodeTotalXDptx_Topology
    SinkListXDptx_Topology
    SinkTotalXDptx_Topology
    NodeTableXDptx_Topology
    NodeTotalXDptx_Topology
    SinkListXDptx_Topology
    SinkTotalXDptx_Topology
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology.html index c9210db4..a10a1a45 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology.html @@ -29,67 +29,67 @@ This typedef describes a the entire topology of connected downstream DisplayPort - + - + - + - +

    Public Attributes

    u8 NodeTotal
    u8 NodeTotal
    XDptx_TopologyNode NodeTable [63]
    XDptx_TopologyNode NodeTable [63]
    u8 SinkTotal
    u8 SinkTotal
    XDptx_TopologyNodeSinkList [63]
    XDptx_TopologyNodeSinkList [63]


    Member Data Documentation

    - +

    -A table listing all the nodes in the MST topology. +A table listing all the nodes in the MST topology.

    - +

    -The total number of nodes that were found in the MST topology. +The total number of nodes that were found in the MST topology.

    - +

    -A pointer list of sinks in the MST topology. The entries will point to the sinks in the NodeTable. +A pointer list of sinks in the MST topology. The entries will point to the sinks in the NodeTable.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology_node-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology_node-members.html index fbb81ef5..dc89cb4e 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology_node-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology_node-members.html @@ -22,10 +22,10 @@
  • Class Members
  • XDptx_TopologyNode Member List

    This is the complete list of members for XDptx_TopologyNode, including all inherited members.

    - - - - - - + + + + + +
    DeviceTypeXDptx_TopologyNode
    DpcdRevXDptx_TopologyNode
    GuidXDptx_TopologyNode
    LinkCountTotalXDptx_TopologyNode
    MsgCapStatusXDptx_TopologyNode
    RelativeAddressXDptx_TopologyNode
    DeviceTypeXDptx_TopologyNode
    DpcdRevXDptx_TopologyNode
    GuidXDptx_TopologyNode
    LinkCountTotalXDptx_TopologyNode
    MsgCapStatusXDptx_TopologyNode
    RelativeAddressXDptx_TopologyNode
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology_node.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology_node.html index 56ec9293..0fab00a1 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology_node.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___topology_node.html @@ -29,101 +29,101 @@ This typedef describes a downstream DisplayPort device when the driver is runnin - + - + - + - + - + - +

    Public Attributes

    u32 Guid [4]
    u32 Guid [4]
    u8 RelativeAddress [15]
    u8 RelativeAddress [15]
    u8 DeviceType
    u8 DeviceType
    u8 LinkCountTotal
    u8 LinkCountTotal
    u8 DpcdRev
    u8 DpcdRev
    u8 MsgCapStatus
    u8 MsgCapStatus


    Member Data Documentation

    - +

    -The type of DisplayPort device. Either a branch or sink. +The type of DisplayPort device. Either a branch or sink.

    - +

    -The revision of the device's DisplayPort Configuration Data (DPCD). For this device to support MST features, this value must represent a protocl version greater or equal to 1.2. +The revision of the device's DisplayPort Configuration Data (DPCD). For this device to support MST features, this value must represent a protocl version greater or equal to 1.2.

    - +

    -The global unique identifier (GUID) of the device. +The global unique identifier (GUID) of the device.

    - +

    -The total number of DisplayPort links connecting this device to the DisplayPort TX. +The total number of DisplayPort links connecting this device to the DisplayPort TX.

    - +

    -This device is capable of sending and receiving sideband messages. +This device is capable of sending and receiving sideband messages.

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8c.html index d8fdf628..fdda4745 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8c.html @@ -30,7 +30,11 @@ Contains a minimal set of functions for the xdptx.h"
    #include "xstatus.h"
    @@ -41,84 +45,84 @@ Contains a minimal set of functions for the struct  XDptx_AuxTransaction

    Defines

    -#define XDPTX_MAXIMUM_VS_LEVEL   3 +#define XDPTX_MAXIMUM_VS_LEVEL   3 -#define XDPTX_MAXIMUM_PE_LEVEL   3 +#define XDPTX_MAXIMUM_PE_LEVEL   3 -#define XDPTX_AUX_MAX_DEFER_COUNT   50 +#define XDPTX_AUX_MAX_DEFER_COUNT   50 -#define XDPTX_AUX_MAX_TIMEOUT_COUNT   50 +#define XDPTX_AUX_MAX_TIMEOUT_COUNT   50 -#define XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT   50 +#define XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT   50

    Enumerations

    -enum  XDptx_TrainingState {
    -  XDPTX_TS_CLOCK_RECOVERY, -XDPTX_TS_CHANNEL_EQUALIZATION, -XDPTX_TS_ADJUST_LINK_RATE, -XDPTX_TS_ADJUST_LANE_COUNT, +enum  XDptx_TrainingState {
    +  XDPTX_TS_CLOCK_RECOVERY, +XDPTX_TS_CHANNEL_EQUALIZATION, +XDPTX_TS_ADJUST_LINK_RATE, +XDPTX_TS_ADJUST_LANE_COUNT,
    -  XDPTX_TS_FAILURE, -XDPTX_TS_SUCCESS +  XDPTX_TS_FAILURE, +XDPTX_TS_SUCCESS
    }

    Functions

    -u32 XDptx_InitializeTx (XDptx *InstancePtr) +u32 XDptx_InitializeTx (XDptx *InstancePtr) -void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr) +void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr) -u32 XDptx_GetRxCapabilities (XDptx *InstancePtr) +u32 XDptx_GetRxCapabilities (XDptx *InstancePtr) -u32 XDptx_CfgMainLinkMax (XDptx *InstancePtr) +u32 XDptx_CfgMainLinkMax (XDptx *InstancePtr) -u32 XDptx_EstablishLink (XDptx *InstancePtr) +u32 XDptx_EstablishLink (XDptx *InstancePtr) -u32 XDptx_CheckLinkStatus (XDptx *InstancePtr, u8 LaneCount) +u32 XDptx_CheckLinkStatus (XDptx *InstancePtr, u8 LaneCount) -void XDptx_EnableTrainAdaptive (XDptx *InstancePtr, u8 Enable) +void XDptx_EnableTrainAdaptive (XDptx *InstancePtr, u8 Enable) -void XDptx_SetHasRedriverInPath (XDptx *InstancePtr, u8 Set) +void XDptx_SetHasRedriverInPath (XDptx *InstancePtr, u8 Set) -void XDptx_CfgTxVsOffset (XDptx *InstancePtr, u8 Offset) +void XDptx_CfgTxVsOffset (XDptx *InstancePtr, u8 Offset) -void XDptx_CfgTxVsLevel (XDptx *InstancePtr, u8 Level, u8 TxLevel) +void XDptx_CfgTxVsLevel (XDptx *InstancePtr, u8 Level, u8 TxLevel) -void XDptx_CfgTxPeLevel (XDptx *InstancePtr, u8 Level, u8 TxLevel) +void XDptx_CfgTxPeLevel (XDptx *InstancePtr, u8 Level, u8 TxLevel) -u32 XDptx_IsConnected (XDptx *InstancePtr) +u32 XDptx_IsConnected (XDptx *InstancePtr) -u32 XDptx_AuxRead (XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToRead, void *ReadData) +u32 XDptx_AuxRead (XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToRead, void *ReadData) -u32 XDptx_AuxWrite (XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, void *WriteData) +u32 XDptx_AuxWrite (XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, void *WriteData) -u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData) +u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData) -u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData) +u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData) -u32 XDptx_SetDownspread (XDptx *InstancePtr, u8 Enable) +u32 XDptx_SetDownspread (XDptx *InstancePtr, u8 Enable) -u32 XDptx_SetEnhancedFrameMode (XDptx *InstancePtr, u8 Enable) +u32 XDptx_SetEnhancedFrameMode (XDptx *InstancePtr, u8 Enable) -u32 XDptx_SetLaneCount (XDptx *InstancePtr, u8 LaneCount) +u32 XDptx_SetLaneCount (XDptx *InstancePtr, u8 LaneCount) -u32 XDptx_SetLinkRate (XDptx *InstancePtr, u8 LinkRate) +u32 XDptx_SetLinkRate (XDptx *InstancePtr, u8 LinkRate) -u32 XDptx_SetScrambler (XDptx *InstancePtr, u8 Enable) +u32 XDptx_SetScrambler (XDptx *InstancePtr, u8 Enable) -void XDptx_EnableMainLink (XDptx *InstancePtr) +void XDptx_EnableMainLink (XDptx *InstancePtr) -void XDptx_DisableMainLink (XDptx *InstancePtr) +void XDptx_DisableMainLink (XDptx *InstancePtr) -void XDptx_ResetPhy (XDptx *InstancePtr, u32 Reset) +void XDptx_ResetPhy (XDptx *InstancePtr, u32 Reset) -void XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef) +void XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef) -void XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds) +void XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds)

    Define Documentation

    - +
    @@ -133,7 +137,7 @@ Contains a minimal set of functions for the +
    @@ -148,7 +152,7 @@ Contains a minimal set of functions for the +
    @@ -163,7 +167,7 @@ Contains a minimal set of functions for the +
    @@ -178,7 +182,7 @@ Contains a minimal set of functions for the +
    @@ -194,12 +198,12 @@ Contains a minimal set of functions for the +
    - +
    enum XDptx_TrainingState enum XDptx_TrainingState
    @@ -208,17 +212,17 @@ Contains a minimal set of functions for the -XDPTX_TS_CLOCK_RECOVERY  +XDPTX_TS_CLOCK_RECOVERY  -XDPTX_TS_CHANNEL_EQUALIZATION  +XDPTX_TS_CHANNEL_EQUALIZATION  -XDPTX_TS_ADJUST_LINK_RATE  +XDPTX_TS_ADJUST_LINK_RATE  -XDPTX_TS_ADJUST_LANE_COUNT  +XDPTX_TS_ADJUST_LANE_COUNT  -XDPTX_TS_FAILURE  +XDPTX_TS_FAILURE  -XDPTX_TS_SUCCESS  +XDPTX_TS_SUCCESS  @@ -226,7 +230,7 @@ This typedef enumerates the list of training states used in the state machine du


    Function Documentation

    - +
    @@ -280,7 +284,7 @@ This function issues a read request over the AUX channel that will read from the

    - +

    @@ -334,7 +338,7 @@ This function issues a write request over the AUX channel that will write to the

    - +

    @@ -379,7 +383,7 @@ This function retrieves the configuration for this DisplayPort TX instance and f

    - +

    @@ -409,7 +413,7 @@ This function determines the common capabilities between the DisplayPort TX core

    - +

    @@ -454,7 +458,7 @@ This function sets the pre-emphasis level value in the DisplayPort TX that will

    - +

    @@ -499,7 +503,7 @@ This function sets the voltage swing level value in the DisplayPort TX that will

    - +

    @@ -537,7 +541,7 @@ This function sets the voltage swing offset to use during training when no redri

    - +

    @@ -577,7 +581,7 @@ This function checks if the reciever's DisplayPort Configuration Data (DPCD) ind

    - +

    @@ -605,7 +609,7 @@ This function disables the main link.

    - +

    @@ -633,7 +637,7 @@ This function enables the main link.

    - +

    @@ -671,7 +675,7 @@ This function enables or disables downshifting during the training process.

    - +

    @@ -701,7 +705,7 @@ This function checks if the link needs training and runs the training sequence i

    - +

    @@ -731,7 +735,7 @@ This function retrieves the RX device's capabilities from the RX device's Displa

    - +

    @@ -794,7 +798,7 @@ This function performs an I2C read over the AUX channel. The read message will b

    - +

    @@ -848,7 +852,7 @@ This function performs an I2C write over the AUX channel.

    - +

    @@ -878,7 +882,7 @@ This function prepares the DisplayPort TX core for use.

    - +

    @@ -907,7 +911,7 @@ This function checks if there is a connected RX device.

    - +

    @@ -945,7 +949,7 @@ This function does a PHY reset.

    - +

    @@ -985,7 +989,7 @@ This function enables or disables 0.5% spreading of the clock for both the Displ

    - +

    @@ -1025,7 +1029,7 @@ This function enables or disables the enhanced framing symbol sequence for both

    - +

    @@ -1063,7 +1067,7 @@ This function sets a software switch that signifies whether or not a redriver ex

    - +

    @@ -1103,7 +1107,7 @@ This function sets the number of lanes to be used by the main link for both the

    - +

    @@ -1145,7 +1149,7 @@ This function sets the data rate to be used by the main link for both the Displa

    - +

    @@ -1185,7 +1189,7 @@ This function enables or disables scrambling of symbols for both the DisplayPort

    - +

    @@ -1198,7 +1202,7 @@ This function enables or disables scrambling of symbols for both the DisplayPort - + @@ -1230,7 +1234,7 @@ This function installs a custom delay/sleep function to be used by the XDdptx dr

    - +

    XDptx_TimerHandler XDptx_TimerHandler  CallbackFunc,
    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html index 3effbab0..aac7b4ab 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html @@ -21,11 +21,78 @@
  • File List
  • File Members
  • -

    xdptx.h File Reference

    +

    xdptx.h File Reference


    Detailed Description

    +The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the DisplayPort 1.2a specification.

    +The Xilinx DisplayPort soft IP supports the following features:

      +
    • 1, 2, or 4 lanes.
    • A link rate of 1.62, 2.70, or 5.40Gbps per lane.
    • 1, 2, or 4 pixel-wide video interfaces.
    • RGB and YCbCr color space.
    • Up to 16 bits per component.
    • Up to 4Kx2K monitor resolution.
    • Auto lane rate and width negotiation.
    • I2C over a 1Mb/s AUX channel.
    • Secondary channel audio support (2 channels).
    • 4 independent video multi-streams.
    +

    +The Xilinx DisplayPort soft IP does not support the following features:

      +
    • The automated test feature.
    • Audio (3-8 channel).
    • FAUX.
    • Bridging function.
    • MST audio.
    • eDP optional features.
    • iDP.
    • GTC.
    +

    +DisplayPort overview

    +A DisplayPort link consists of:

      +
    • A unidirectional main link which is used to transport isochronous data streams such as video and audio. The main link may use 1, 2, or 4 lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link needs to be trained prior to sending streams.
    • An auxiliary (AUX) channel is a 1MBps bidirectional channel used for link training, link management, and device control.
    • A hot-plug-detect (HPD) signal line is used to determine whether a DisplayPort connection exists between the DisplayPort TX connector and an RX device. It is serves as an interrupt request by the RX device.
    +

    +Driver description

    +The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort TX soft IP, communicate and control an RX device/sink monitor over the AUX channel, and to initialize and transmit data streams over the main link.

    +This driver implements link layer functionality: a Link Policy Maker (LPM) and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.

      +
    • The LPM manages the main link and is responsible for keeping the link synchronized. It will establish a link with a downstream RX device by undergoing a link training sequence which consists of:
        +
      • Clock recovery: The clock needs to be recovered and PLLs need to be locked for all lanes.
      • Channel equalization: All lanes need to achieve channel equalization and and symbol lock, as well as for interlane alignment to take place.
      +
    • The SPM manages transportation of an isochronous stream. That is, it will initialize and maintain a video stream, establish a virtual channel to a sink monitor, and transmit the stream.
    +

    +Using AUX transactions to read/write from/to the sink's DisplayPort Configuration Data (DPCD) address space, the LPM obtains the link capabilities, obtains link configuration and link and sink status, and configures and controls the link and sink. The main link is trained this way.

    +I2C-over-AUX transactions are used to obtain the sink's Extended Display Identification Data (EDID) which give information on the display capabilities of the monitor. The SPM may use this information to determine what available screen resolutions and video timing are possible.

    +Device configuration

    +The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the xdptx_g.c file which is generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the DisplayPort instances present in the system. This information includes parameters that are defined in the driver's data/dptx.tcl file such as the base address of the memory-mapped device and the maximum number of lanes, maximum link rate, and video interface that the DisplayPort instance supports, among others.

    +Interrupt processing

    +DisplayPort interrupts occur on the HPD signal line when the DisplayPort cable is connected/disconnected or when the RX device sends a pulse. The user hardware design must contain an interrupt controller which the DisplayPort TX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts. When the XDptx_HpdInterruptHandler function is invoked, the handler will identify what type of DisplayPort interrupt has occurred, and will call either the HPD event handler function or the HPD pulse handler function, depending on whether a an HPD event on an HPD pulse event occurred.

    +The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of interrupt that has occured, and the XDptx_HpdInterruptHandler will use this information to decide which handler to call. An HPD event is identified if bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.

    +The HPD event handler may be set up by using the XDptx_SetHpdEventHandler function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler function.

    +Multi-stream transport (MST) mode

    +The driver handles MST mode functionality, including sideband messaging, topology discovery, virtual channel payload ID table management, and directing streams to different sinks.

    +MST testing has been done at all possible link rate/lane count/topology/ resolution/color depth combinations with each setting using following values:

      +
    • Link rate: 1.62, 2.70, and 5.40Gbps per lane.
    • Lane count: 1, 2, and 4 lanes.
    • Number of sink displays: 1, 2, 3, and 4 sink displays in both a daisy-chain configuration and in a configuration using a combination of a 1-to-3 hub and daisy-chain. Each stream was using the same resolution.
    • Resolutions (60Hz): 640x480, 800x600, 1024x768, 1280x800, 1280x1024, 1360x768, 1400x1050, 1680x1050, 1920x1080, 1920x2160, and 3840x2160.
    • Color depths: 18, 24, 30, 36, and 48 bits per pixel.
    +

    +Audio

    +The driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.

    +Asserts

    +Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.

    +Limitations

    +

      +
    • For MST mode to correctly display, the current version of the driver requires that each of the DisplayPort TX streams be allocated without skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems were experienced if skipping stream 2 and assigning stream 4 instead). skipping monitors in a daisy chain is OK as long as they are assigned to streams in order.
    • In MST mode, the current version of the driver does not support removal of an allocated stream from the virtual channel payload ID table without clearing the entire table.
    • Some sideband messages have not been implemented in the current version of the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY sideband message.
    • The driver does not handle audio. See the audio example in the driver examples directory for the required sequence for enabling audio.
    +

    +

    Note:
    For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.
    +
    + MODIFICATION HISTORY:

    +

     Ver   Who  Date     Changes
    + ----- ---- -------- -----------------------------------------------
    + 1.0   als  05/17/14 Initial release.
    +       als  08/03/14 Initial MST addition.
    + 2.0   als  09/21/14 Added XDptx_DiscoverTopology function and changed
    +                     XDptx_IsConnected from macro to function.
    + 3.0   als  12/16/14 Updated to use common video library.
    +                     Added topology reordering functions:
    +                         XDptx_TopologySwapSinks,
    +                         XDptx_TopologySortSinksByTiling
    +                     Added wrapper functions for remote DPCD/I2C read/writes:
    +                         XDptx_RemoteDpcdRead, XDptx_RemoteDpcdWrite,
    +                         XDptx_RemoteIicRead, XDptx_RemoteIicWrite
    +                     Added EDID utility functions:
    +                         XDptx_GetRemoteEdid, XDptx_GetEdidBlock,
    +                         XDptx_GetRemoteEdidBlock,
    +                         XDptx_GetRemoteEdidDispIdExt,
    +                         XDptx_GetDispIdDataBlock,
    +                         XDptx_GetRemoteTiledDisplayDb
    +                     Remove unused arguments from functions:
    +                         LinkCountTotal, RelativeAddress from
    +                             XDptx_AllocatePayloadVcIdTable
    +                         RegStartAddress from XDptx_IicWrite
    + 

    #include "xdptx_hw.h"
    #include "xil_assert.h"
    #include "xil_types.h"
    +#include "xvid.h"

    @@ -35,8 +102,6 @@ - - @@ -54,294 +119,177 @@ - + - + - - - - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - +

    Classes

    struct  XDptx_LinkConfig
    struct  XDptx_DmtMode
    struct  XDptx_MainStreamAttributes
    struct  XDptx_MstStream
    struct  XDptx

    Typedefs

    typedef void(*) XDptx_TimerHandler (void *InstancePtr, u32 MicroSeconds)
    typedef void(*) XDptx_TimerHandler (void *InstancePtr, u32 MicroSeconds)
    typedef void(*) XDptx_HpdEventHandler (void *InstancePtr)
    typedef void(*) XDptx_HpdEventHandler (void *InstancePtr)
    typedef void(*) XDptx_HpdPulseHandler (void *InstancePtr)

    Enumerations

    enum  XDptx_VideoMode {
    -  XDPTX_VM_640x480_60_P, -XDPTX_VM_800x600_60_P, -XDPTX_VM_848x480_60_P, -XDPTX_VM_1024x768_60_P, -
    -  XDPTX_VM_1280x768_60_P_RB, -XDPTX_VM_1280x768_60_P, -XDPTX_VM_1280x800_60_P_RB, -XDPTX_VM_1280x800_60_P, -
    -  XDPTX_VM_1280x960_60_P, -XDPTX_VM_1280x1024_60_P, -XDPTX_VM_1360x768_60_P, -XDPTX_VM_1400x1050_60_P_RB, -
    -  XDPTX_VM_1400x1050_60_P, -XDPTX_VM_1440x900_60_P_RB, -XDPTX_VM_1440x900_60_P, -XDPTX_VM_1600x1200_60_P, -
    -  XDPTX_VM_1680x1050_60_P_RB, -XDPTX_VM_1680x1050_60_P, -XDPTX_VM_1792x1344_60_P, -XDPTX_VM_1856x1392_60_P, -
    -  XDPTX_VM_1920x1200_60_P_RB, -XDPTX_VM_1920x1200_60_P, -XDPTX_VM_1920x1440_60_P, -XDPTX_VM_2560x1600_60_P_RB, -
    -  XDPTX_VM_2560x1600_60_P, -XDPTX_VM_800x600_56_P, -XDPTX_VM_1600x1200_65_P, -XDPTX_VM_1600x1200_70_P, -
    -  XDPTX_VM_1024x768_70_P, -XDPTX_VM_640x480_72_P, -XDPTX_VM_800x600_72_P, -XDPTX_VM_640x480_75_P, -
    -  XDPTX_VM_800x600_75_P, -XDPTX_VM_1024x768_75_P, -XDPTX_VM_1152x864_75_P, -XDPTX_VM_1280x768_75_P, -
    -  XDPTX_VM_1280x800_75_P, -XDPTX_VM_1280x1024_75_P, -XDPTX_VM_1400x1050_75_P, -XDPTX_VM_1440x900_75_P, -
    -  XDPTX_VM_1600x1200_75_P, -XDPTX_VM_1680x1050_75_P, -XDPTX_VM_1792x1344_75_P, -XDPTX_VM_1856x1392_75_P, -
    -  XDPTX_VM_1920x1200_75_P, -XDPTX_VM_1920x1440_75_P, -XDPTX_VM_2560x1600_75_P, -XDPTX_VM_640x350_85_P, -
    -  XDPTX_VM_640x400_85_P, -XDPTX_VM_720x400_85_P, -XDPTX_VM_640x480_85_P, -XDPTX_VM_800x600_85_P, -
    -  XDPTX_VM_1024x768_85_P, -XDPTX_VM_1280x768_85_P, -XDPTX_VM_1280x800_85_P, -XDPTX_VM_1280x960_85_P, -
    -  XDPTX_VM_1280x1024_85_P, -XDPTX_VM_1400x1050_85_P, -XDPTX_VM_1440x900_85_P, -XDPTX_VM_1600x1200_85_P, -
    -  XDPTX_VM_1680x1050_85_P, -XDPTX_VM_1920x1200_85_P, -XDPTX_VM_2560x1600_85_P, -XDPTX_VM_800x600_120_P_RB, -
    -  XDPTX_VM_1024x768_120_P_RB, -XDPTX_VM_1280x768_120_P_RB, -XDPTX_VM_1280x800_120_P_RB, -XDPTX_VM_1280x960_120_P_RB, -
    -  XDPTX_VM_1280x1024_120_P_RB, -XDPTX_VM_1360x768_120_P_RB, -XDPTX_VM_1400x1050_120_P_RB, -XDPTX_VM_1440x900_120_P_RB, -
    -  XDPTX_VM_1600x1200_120_P_RB, -XDPTX_VM_1680x1050_120_P_RB, -XDPTX_VM_1792x1344_120_P_RB, -XDPTX_VM_1856x1392_120_P_RB, -
    -  XDPTX_VM_1920x1200_120_P_RB, -XDPTX_VM_1920x1440_120_P_RB, -XDPTX_VM_2560x1600_120_P_RB, -XDPTX_VM_1366x768_60_P, -
    -  XDPTX_VM_1920x1080_60_P, -XDPTX_VM_UHD_30_P, -XDPTX_VM_720_60_P, -XDPTX_VM_480_60_P, -
    -  XDPTX_VM_UHD2_60_P, -XDPTX_VM_UHD_60, -XDPTX_VM_USE_EDID_PREFERRED, -XDPTX_VM_LAST = XDPTX_VM_USE_EDID_PREFERRED -
    - }
    typedef void(*) XDptx_HpdPulseHandler (void *InstancePtr)

    Functions

    u32 XDptx_InitializeTx (XDptx *InstancePtr)
    u32 XDptx_InitializeTx (XDptx *InstancePtr)
    void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr)
    void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr)
    u32 XDptx_GetRxCapabilities (XDptx *InstancePtr)
    u32 XDptx_GetRxCapabilities (XDptx *InstancePtr)
    u32 XDptx_CfgMainLinkMax (XDptx *InstancePtr)
    u32 XDptx_CfgMainLinkMax (XDptx *InstancePtr)
    u32 XDptx_EstablishLink (XDptx *InstancePtr)
    u32 XDptx_EstablishLink (XDptx *InstancePtr)
    u32 XDptx_CheckLinkStatus (XDptx *InstancePtr, u8 LaneCount)
    u32 XDptx_CheckLinkStatus (XDptx *InstancePtr, u8 LaneCount)
    void XDptx_EnableTrainAdaptive (XDptx *InstancePtr, u8 Enable)
    void XDptx_EnableTrainAdaptive (XDptx *InstancePtr, u8 Enable)
    void XDptx_SetHasRedriverInPath (XDptx *InstancePtr, u8 Set)
    void XDptx_SetHasRedriverInPath (XDptx *InstancePtr, u8 Set)
    void XDptx_CfgTxVsOffset (XDptx *InstancePtr, u8 Offset)
    void XDptx_CfgTxVsOffset (XDptx *InstancePtr, u8 Offset)
    void XDptx_CfgTxVsLevel (XDptx *InstancePtr, u8 Level, u8 TxLevel)
    void XDptx_CfgTxVsLevel (XDptx *InstancePtr, u8 Level, u8 TxLevel)
    void XDptx_CfgTxPeLevel (XDptx *InstancePtr, u8 Level, u8 TxLevel)
    void XDptx_CfgTxPeLevel (XDptx *InstancePtr, u8 Level, u8 TxLevel)
    u32 XDptx_AuxRead (XDptx *InstancePtr, u32 Address, u32 BytesToRead, void *ReadData)
    u32 XDptx_AuxRead (XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToRead, void *ReadData)
    u32 XDptx_AuxWrite (XDptx *InstancePtr, u32 Address, u32 BytesToWrite, void *WriteData)
    u32 XDptx_AuxWrite (XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, void *WriteData)
    u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData)
    u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData)
    u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData)
    u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData)
    u32 XDptx_SetDownspread (XDptx *InstancePtr, u8 Enable)
    u32 XDptx_SetDownspread (XDptx *InstancePtr, u8 Enable)
    u32 XDptx_SetEnhancedFrameMode (XDptx *InstancePtr, u8 Enable)
    u32 XDptx_SetEnhancedFrameMode (XDptx *InstancePtr, u8 Enable)
    u32 XDptx_SetLaneCount (XDptx *InstancePtr, u8 LaneCount)
    u32 XDptx_SetLaneCount (XDptx *InstancePtr, u8 LaneCount)
    u32 XDptx_SetLinkRate (XDptx *InstancePtr, u8 LinkRate)
    u32 XDptx_SetLinkRate (XDptx *InstancePtr, u8 LinkRate)
    u32 XDptx_SetScrambler (XDptx *InstancePtr, u8 Enable)
    u32 XDptx_SetScrambler (XDptx *InstancePtr, u8 Enable)
    u32 XDptx_IsConnected (XDptx *InstancePtr)
    u32 XDptx_IsConnected (XDptx *InstancePtr)
    void XDptx_EnableMainLink (XDptx *InstancePtr)
    void XDptx_EnableMainLink (XDptx *InstancePtr)
    void XDptx_DisableMainLink (XDptx *InstancePtr)
    void XDptx_DisableMainLink (XDptx *InstancePtr)
    void XDptx_ResetPhy (XDptx *InstancePtr, u32 Reset)
    void XDptx_ResetPhy (XDptx *InstancePtr, u32 Reset)
    void XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds)
    void XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds)
    void XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef)
    void XDptx_CfgMsaRecalculate (XDptx *InstancePtr, u8 Stream)
    void XDptx_CfgMsaRecalculate (XDptx *InstancePtr, u8 Stream)
    void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XDptx_VideoMode VideoMode)
    void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XVid_VideoMode VideoMode)
    void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr, u8 Stream, u8 *Edid)
    void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr, u8 Stream, u8 *Edid)
    void XDptx_CfgMsaUseCustom (XDptx *InstancePtr, u8 Stream, XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
    void XDptx_CfgMsaUseCustom (XDptx *InstancePtr, u8 Stream, XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
    void XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 Stream, u8 BitsPerColor)
    void XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 Stream, u8 BitsPerColor)
    void XDptx_CfgMsaEnSynchClkMode (XDptx *InstancePtr, u8 Stream, u8 Enable)
    void XDptx_CfgMsaEnSynchClkMode (XDptx *InstancePtr, u8 Stream, u8 Enable)
    void XDptx_SetVideoMode (XDptx *InstancePtr, u8 Stream)
    void XDptx_SetVideoMode (XDptx *InstancePtr, u8 Stream)
    void XDptx_ClearMsaValues (XDptx *InstancePtr, u8 Stream)
    void XDptx_ClearMsaValues (XDptx *InstancePtr, u8 Stream)
    void XDptx_SetMsaValues (XDptx *InstancePtr, u8 Stream)
    void XDptx_SetMsaValues (XDptx *InstancePtr, u8 Stream)
    void XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
    void XDptx_HpdInterruptHandler (XDptx *InstancePtr)
    void XDptx_HpdInterruptHandler (XDptx *InstancePtr)
    u32 XDptx_SelfTest (XDptx *InstancePtr)
    u32 XDptx_SelfTest (XDptx *InstancePtr)
    XDptx_ConfigXDptx_LookupConfig (u16 DeviceId)
    XDptx_ConfigXDptx_LookupConfig (u16 DeviceId)
    void XDptx_MstCfgModeEnable (XDptx *InstancePtr)
    void XDptx_MstCfgModeEnable (XDptx *InstancePtr)
    void XDptx_MstCfgModeDisable (XDptx *InstancePtr)
    void XDptx_MstCfgModeDisable (XDptx *InstancePtr)
    u32 XDptx_MstCapable (XDptx *InstancePtr)
    u32 XDptx_MstCapable (XDptx *InstancePtr)
    u32 XDptx_MstEnable (XDptx *InstancePtr)
    u32 XDptx_MstEnable (XDptx *InstancePtr)
    u32 XDptx_MstDisable (XDptx *InstancePtr)
    u32 XDptx_MstDisable (XDptx *InstancePtr)
    void XDptx_MstCfgStreamEnable (XDptx *InstancePtr, u8 Stream)
    void XDptx_MstCfgStreamEnable (XDptx *InstancePtr, u8 Stream)
    void XDptx_MstCfgStreamDisable (XDptx *InstancePtr, u8 Stream)
    void XDptx_MstCfgStreamDisable (XDptx *InstancePtr, u8 Stream)
    u8 XDptx_MstStreamIsEnabled (XDptx *InstancePtr, u8 Stream)
    u8 XDptx_MstStreamIsEnabled (XDptx *InstancePtr, u8 Stream)
    void XDptx_SetStreamSelectFromSinkList (XDptx *InstancePtr, u8 Stream, u8 SinkNum)
    void XDptx_SetStreamSelectFromSinkList (XDptx *InstancePtr, u8 Stream, u8 SinkNum)
    void XDptx_SetStreamSinkRad (XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress)
    void XDptx_SetStreamSinkRad (XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_DiscoverTopology (XDptx *InstancePtr)
    u32 XDptx_DiscoverTopology (XDptx *InstancePtr)
    u32 XDptx_FindAccessibleDpDevices (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_FindAccessibleDpDevices (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)
    void XDptx_TopologySwapSinks (XDptx *InstancePtr, u8 Index0, u8 Index1)
    void XDptx_TopologySwapSinks (XDptx *InstancePtr, u8 Index0, u8 Index1)
    void XDptx_TopologySortSinksByTiling (XDptx *InstancePtr)
    void XDptx_TopologySortSinksByTiling (XDptx *InstancePtr)
    u32 XDptx_RemoteDpcdRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
    u32 XDptx_RemoteDpcdRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
    u32 XDptx_RemoteDpcdWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
    u32 XDptx_RemoteDpcdWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
    u32 XDptx_RemoteIicRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData)
    u32 XDptx_RemoteIicRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData)
    u32 XDptx_RemoteIicWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData)
    u32 XDptx_RemoteIicWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData)
    u32 XDptx_AllocatePayloadStreams (XDptx *InstancePtr)
    u32 XDptx_AllocatePayloadStreams (XDptx *InstancePtr)
    u32 XDptx_AllocatePayloadVcIdTable (XDptx *InstancePtr, u8 VcId, u8 Ts)
    u32 XDptx_AllocatePayloadVcIdTable (XDptx *InstancePtr, u8 VcId, u8 Ts)
    u32 XDptx_ClearPayloadVcIdTable (XDptx *InstancePtr)
    u32 XDptx_ClearPayloadVcIdTable (XDptx *InstancePtr)
    u32 XDptx_SendSbMsgRemoteDpcdWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
    u32 XDptx_SendSbMsgRemoteDpcdWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
    u32 XDptx_SendSbMsgRemoteDpcdRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
    u32 XDptx_SendSbMsgRemoteDpcdRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
    u32 XDptx_SendSbMsgRemoteIicWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData)
    u32 XDptx_SendSbMsgRemoteIicWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData)
    u32 XDptx_SendSbMsgRemoteIicRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData)
    u32 XDptx_SendSbMsgRemoteIicRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData)
    u32 XDptx_SendSbMsgLinkAddress (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo)
    u32 XDptx_SendSbMsgLinkAddress (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo)
    u32 XDptx_SendSbMsgEnumPathResources (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn)
    u32 XDptx_SendSbMsgEnumPathResources (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn)
    u32 XDptx_SendSbMsgAllocatePayload (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn)
    u32 XDptx_SendSbMsgAllocatePayload (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn)
    u32 XDptx_SendSbMsgClearPayloadIdTable (XDptx *InstancePtr)
    u32 XDptx_SendSbMsgClearPayloadIdTable (XDptx *InstancePtr)
    void XDptx_WriteGuid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 Guid[4])
    void XDptx_WriteGuid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 Guid[4])
    void XDptx_GetGuid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 *Guid)
    void XDptx_GetGuid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 *Guid)
    u32 XDptx_GetEdid (XDptx *InstancePtr, u8 *Edid)
    u32 XDptx_GetEdid (XDptx *InstancePtr, u8 *Edid)
    u32 XDptx_GetRemoteEdid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid)
    u32 XDptx_GetRemoteEdid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid)
    u32 XDptx_GetEdidBlock (XDptx *InstancePtr, u8 *Data, u8 BlockNum)
    u32 XDptx_GetEdidBlock (XDptx *InstancePtr, u8 *Data, u8 BlockNum)
    u32 XDptx_GetRemoteEdidBlock (XDptx *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_GetRemoteEdidBlock (XDptx *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_GetRemoteEdidDispIdExt (XDptx *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_GetRemoteEdidDispIdExt (XDptx *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_GetDispIdDataBlock (u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr)
    u32 XDptx_GetDispIdDataBlock (u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr)
    u32 XDptx_GetRemoteTiledDisplayDb (XDptx *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr)

    Variables

    XDptx_DmtMode XDptx_DmtModes []
    u32 XDptx_GetRemoteTiledDisplayDb (XDptx *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr)

    Typedef Documentation

    - +
    - +
    typedef void(*) XDptx_HpdEventHandler(void *InstancePtr) typedef void(*) XDptx_HpdEventHandler(void *InstancePtr)
    @@ -358,12 +306,12 @@ Callback type which represents the handler for a Hot-Plug-Detect (HPD) event int

    - +

    - +
    typedef void(*) XDptx_HpdPulseHandler(void *InstancePtr) typedef void(*) XDptx_HpdPulseHandler(void *InstancePtr)
    @@ -380,12 +328,12 @@ Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse int

    - +

    - +
    typedef void(*) XDptx_TimerHandler(void *InstancePtr, u32 MicroSeconds) typedef void(*) XDptx_TimerHandler(void *InstancePtr, u32 MicroSeconds)
    @@ -401,208 +349,10 @@ Callback type which represents a custom timer wait handler. This is only used fo
    Note:
    None.
    -
    -

    -


    Enumeration Type Documentation

    - -
    -
    - - - - -
    enum XDptx_VideoMode
    -
    -
    - -

    -This typedef enumerates the list of available standard display monitor timings as specified in the mode_table.c file. The naming format is:

    -XDPTX_VM_<RESOLUTION>_<REFRESH RATE (HZ)>_<P|RB>

    -Where RB stands for reduced blanking.

    Enumerator:
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    XDPTX_VM_640x480_60_P  -
    XDPTX_VM_800x600_60_P  -
    XDPTX_VM_848x480_60_P  -
    XDPTX_VM_1024x768_60_P  -
    XDPTX_VM_1280x768_60_P_RB  -
    XDPTX_VM_1280x768_60_P  -
    XDPTX_VM_1280x800_60_P_RB  -
    XDPTX_VM_1280x800_60_P  -
    XDPTX_VM_1280x960_60_P  -
    XDPTX_VM_1280x1024_60_P  -
    XDPTX_VM_1360x768_60_P  -
    XDPTX_VM_1400x1050_60_P_RB  -
    XDPTX_VM_1400x1050_60_P  -
    XDPTX_VM_1440x900_60_P_RB  -
    XDPTX_VM_1440x900_60_P  -
    XDPTX_VM_1600x1200_60_P  -
    XDPTX_VM_1680x1050_60_P_RB  -
    XDPTX_VM_1680x1050_60_P  -
    XDPTX_VM_1792x1344_60_P  -
    XDPTX_VM_1856x1392_60_P  -
    XDPTX_VM_1920x1200_60_P_RB  -
    XDPTX_VM_1920x1200_60_P  -
    XDPTX_VM_1920x1440_60_P  -
    XDPTX_VM_2560x1600_60_P_RB  -
    XDPTX_VM_2560x1600_60_P  -
    XDPTX_VM_800x600_56_P  -
    XDPTX_VM_1600x1200_65_P  -
    XDPTX_VM_1600x1200_70_P  -
    XDPTX_VM_1024x768_70_P  -
    XDPTX_VM_640x480_72_P  -
    XDPTX_VM_800x600_72_P  -
    XDPTX_VM_640x480_75_P  -
    XDPTX_VM_800x600_75_P  -
    XDPTX_VM_1024x768_75_P  -
    XDPTX_VM_1152x864_75_P  -
    XDPTX_VM_1280x768_75_P  -
    XDPTX_VM_1280x800_75_P  -
    XDPTX_VM_1280x1024_75_P  -
    XDPTX_VM_1400x1050_75_P  -
    XDPTX_VM_1440x900_75_P  -
    XDPTX_VM_1600x1200_75_P  -
    XDPTX_VM_1680x1050_75_P  -
    XDPTX_VM_1792x1344_75_P  -
    XDPTX_VM_1856x1392_75_P  -
    XDPTX_VM_1920x1200_75_P  -
    XDPTX_VM_1920x1440_75_P  -
    XDPTX_VM_2560x1600_75_P  -
    XDPTX_VM_640x350_85_P  -
    XDPTX_VM_640x400_85_P  -
    XDPTX_VM_720x400_85_P  -
    XDPTX_VM_640x480_85_P  -
    XDPTX_VM_800x600_85_P  -
    XDPTX_VM_1024x768_85_P  -
    XDPTX_VM_1280x768_85_P  -
    XDPTX_VM_1280x800_85_P  -
    XDPTX_VM_1280x960_85_P  -
    XDPTX_VM_1280x1024_85_P  -
    XDPTX_VM_1400x1050_85_P  -
    XDPTX_VM_1440x900_85_P  -
    XDPTX_VM_1600x1200_85_P  -
    XDPTX_VM_1680x1050_85_P  -
    XDPTX_VM_1920x1200_85_P  -
    XDPTX_VM_2560x1600_85_P  -
    XDPTX_VM_800x600_120_P_RB  -
    XDPTX_VM_1024x768_120_P_RB  -
    XDPTX_VM_1280x768_120_P_RB  -
    XDPTX_VM_1280x800_120_P_RB  -
    XDPTX_VM_1280x960_120_P_RB  -
    XDPTX_VM_1280x1024_120_P_RB  -
    XDPTX_VM_1360x768_120_P_RB  -
    XDPTX_VM_1400x1050_120_P_RB  -
    XDPTX_VM_1440x900_120_P_RB  -
    XDPTX_VM_1600x1200_120_P_RB  -
    XDPTX_VM_1680x1050_120_P_RB  -
    XDPTX_VM_1792x1344_120_P_RB  -
    XDPTX_VM_1856x1392_120_P_RB  -
    XDPTX_VM_1920x1200_120_P_RB  -
    XDPTX_VM_1920x1440_120_P_RB  -
    XDPTX_VM_2560x1600_120_P_RB  -
    XDPTX_VM_1366x768_60_P  -
    XDPTX_VM_1920x1080_60_P  -
    XDPTX_VM_UHD_30_P  -
    XDPTX_VM_720_60_P  -
    XDPTX_VM_480_60_P  -
    XDPTX_VM_UHD2_60_P  -
    XDPTX_VM_UHD_60  -
    XDPTX_VM_USE_EDID_PREFERRED  -
    XDPTX_VM_LAST  -
    -
    -


    Function Documentation

    - +
    @@ -637,7 +387,7 @@ This function will allocate bandwidth for all enabled stream.

    - +

    @@ -689,7 +439,7 @@ This function will allocate a bandwidth for a virtual channel in the payload ID

    - +

    @@ -743,7 +493,7 @@ This function issues a read request over the AUX channel that will read from the

    - +

    @@ -797,7 +547,7 @@ This function issues a write request over the AUX channel that will write to the

    - +

    @@ -842,7 +592,7 @@ This function retrieves the configuration for this DisplayPort TX instance and f

    - +

    @@ -872,7 +622,7 @@ This function determines the common capabilities between the DisplayPort TX core

    - +

    @@ -917,7 +667,7 @@ This function enables or disables synchronous clock mode for a video stream.

    - +

    @@ -957,7 +707,7 @@ This function calculates the following Main Stream Attributes (MSA):

      - +

    @@ -1002,7 +752,7 @@ This function sets the bits per color value of the video stream.

    - +

    @@ -1056,7 +806,7 @@ This function takes a the main stream attributes from MsaConfigCustom and copies

    - +

    @@ -1101,7 +851,7 @@ This function sets the main stream attribute values in the configuration structu

    - +

    @@ -1120,7 +870,7 @@ This function sets the main stream attribute values in the configuration structu - + @@ -1146,7 +896,7 @@ This function sets the Main Stream Attribute (MSA) values in the configuration s

    - +

    XDptx_VideoMode XVid_VideoMode  VideoMode 
    @@ -1191,7 +941,7 @@ This function sets the pre-emphasis level value in the DisplayPort TX that will

    - +

    @@ -1236,7 +986,7 @@ This function sets the voltage swing level value in the DisplayPort TX that will

    - +

    @@ -1274,7 +1024,7 @@ This function sets the voltage swing offset to use during training when no redri

    - +

    @@ -1314,7 +1064,7 @@ This function checks if the reciever's DisplayPort Configuration Data (DPCD) ind

    - +

    @@ -1352,7 +1102,7 @@ This function clears the main stream attributes registers of the DisplayPort TX

    - +

    @@ -1387,7 +1137,7 @@ This function will clear the virtual channel payload ID table in both the Displa

    - +

    @@ -1415,7 +1165,7 @@ This function disables the main link.

    - +

    @@ -1445,7 +1195,7 @@ This function will explore the DisplayPort topology of downstream devices connec

    - +

    @@ -1473,7 +1223,7 @@ This function enables the main link.

    - +

    @@ -1511,7 +1261,7 @@ This function enables or disables downshifting during the training process.

    - +

    @@ -1541,7 +1291,7 @@ This function checks if the link needs training and runs the training sequence i

    - +

    @@ -1588,7 +1338,7 @@ This function will explore the DisplayPort topology of downstream devices starti

    - +

    @@ -1635,7 +1385,7 @@ Given a section tag, search for and retrieve the appropriate section data block

    - +

    @@ -1675,7 +1425,7 @@ This function retrieves an immediately connected RX device's Extended Display Id

    - +

    @@ -1722,7 +1472,7 @@ Retrieve an immediately connected RX device's Extended Display Identification Da

    - +

    @@ -1774,7 +1524,7 @@ This function will obtain the global unique identifier (GUID) for the target Dis

    - +

    @@ -1828,7 +1578,7 @@ This function retrieves a remote RX device's Extended Display Identification Dat

    - +

    @@ -1889,7 +1639,7 @@ Retrieve a downstream DisplayPort device's Extended Display Identification Data

    - +

    @@ -1943,7 +1693,7 @@ Search for and retrieve a downstream DisplayPort device's Extended Display Ident

    - +

    @@ -2004,7 +1754,7 @@ Search for and retrieve a downstream DisplayPort device's Tiled Display Topology

    - +

    @@ -2034,7 +1784,7 @@ This function retrieves the RX device's capabilities from the RX device's Displa

    - +

    @@ -2063,7 +1813,7 @@ When an interrupt happens, it first detects what kind of interrupt happened, the

    - +

    @@ -2126,7 +1876,7 @@ This function performs an I2C read over the AUX channel. The read message will b

    - +

    @@ -2180,7 +1930,7 @@ This function performs an I2C write over the AUX channel.

    - +

    @@ -2210,7 +1960,7 @@ This function prepares the DisplayPort TX core for use.

    - +

    @@ -2239,7 +1989,7 @@ This function checks if there is a connected RX device.

    - +

    @@ -2267,7 +2017,7 @@ This function looks for the device configuration based on the unique device ID.

    - +

    @@ -2302,7 +2052,7 @@ This function will check if the immediate downstream RX device is capable of mul

    - +

    @@ -2330,7 +2080,7 @@ This function will disable multi-stream transport (MST) mode for the driver.

    - +

    @@ -2358,7 +2108,7 @@ This function will enable multi-stream transport (MST) mode for the driver.

    - +

    @@ -2396,7 +2146,7 @@ This function will configure the InstancePtr->MstStreamConfig structure to di

    - +

    @@ -2434,7 +2184,7 @@ This function will configure the InstancePtr->MstStreamConfig structure to en

    - +

    @@ -2469,7 +2219,7 @@ This function will disable multi-stream transport (MST) mode in both the Display

    - +

    @@ -2504,7 +2254,7 @@ This function will enable multi-stream transport (MST) mode in both the DisplayP

    - +

    @@ -2544,7 +2294,7 @@ This function will check whether

    - +

    @@ -2612,7 +2362,7 @@ This function performs a remote DisplayPort Configuration Data (DPCD) read by se

    - +

    @@ -2680,7 +2430,7 @@ This function performs a remote DisplayPort Configuration Data (DPCD) write by s

    - +

    @@ -2757,7 +2507,7 @@ This function performs a remote I2C read by sending a sideband message. In case

    - +

    @@ -2825,7 +2575,7 @@ This function performs a remote I2C write by sending a sideband message. In case

    - +

    @@ -2863,7 +2613,7 @@ This function does a PHY reset.

    - +

    @@ -2893,7 +2643,7 @@ This function runs a self-test on the XD

    - +

    @@ -2959,7 +2709,7 @@ This function will send an ALLOCATE_PAYLOAD sideband message which will allocate

    - +

    @@ -2994,7 +2744,7 @@ This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will de-

    - +

    @@ -3062,7 +2812,7 @@ FullPbn will be modified with the total PBN of the path from the reply.

    - +

    @@ -3121,7 +2871,7 @@ This function will send a LINK_ADDRESS sideband message to a target DisplayPort

    - +

    @@ -3194,7 +2944,7 @@ This function will send a REMOTE_DPCD_READ sideband message which will read from

    - +

    @@ -3267,7 +3017,7 @@ This function will send a REMOTE_DPCD_WRITE sideband message which will write so

    - +

    @@ -3347,7 +3097,7 @@ This function will send a REMOTE_I2C_READ sideband message which will read from

    - +

    @@ -3400,7 +3150,7 @@ This function will send a REMOTE_I2C_READ sideband message which will read from

    - +

    @@ -3440,7 +3190,7 @@ This function enables or disables 0.5% spreading of the clock for both the Displ

    - +

    @@ -3480,7 +3230,7 @@ This function enables or disables the enhanced framing symbol sequence for both

    - +

    @@ -3518,7 +3268,7 @@ This function sets a software switch that signifies whether or not a redriver ex

    - +

    @@ -3531,7 +3281,7 @@ This function sets a software switch that signifies whether or not a redriver ex - + @@ -3563,7 +3313,7 @@ This function installs a callback function for when a hot-plug-detect event inte

    - +

    XDptx_HpdEventHandler XDptx_HpdEventHandler  CallbackFunc,
    @@ -3576,7 +3326,7 @@ This function installs a callback function for when a hot-plug-detect event inte - + @@ -3608,7 +3358,7 @@ This function installs a callback function for when a hot-plug-detect pulse inte

    - +

    XDptx_HpdPulseHandler XDptx_HpdPulseHandler  CallbackFunc,
    @@ -3648,7 +3398,7 @@ This function sets the number of lanes to be used by the main link for both the

    - +

    @@ -3690,7 +3440,7 @@ This function sets the data rate to be used by the main link for both the Displa

    - +

    @@ -3728,7 +3478,7 @@ This function sets the main stream attributes registers of the DisplayPort TX co

    - +

    @@ -3768,7 +3518,7 @@ This function enables or disables scrambling of symbols for both the DisplayPort

    - +

    @@ -3814,7 +3564,7 @@ The topology will need to be determined prior to calling this function using the

    - +

    @@ -3866,7 +3616,7 @@ This function will map a stream to a downstream DisplayPort TX device determined

    - +

    @@ -3879,7 +3629,7 @@ This function will map a stream to a downstream DisplayPort TX device determined - + @@ -3911,7 +3661,7 @@ This function installs a custom delay/sleep function to be used by the XDdptx dr

    - +

    XDptx_TimerHandler XDptx_TimerHandler  CallbackFunc,
    @@ -3949,7 +3699,7 @@ This function clears the main stream attributes registers of the DisplayPort TX

    - +

    @@ -3977,7 +3727,7 @@ Order the sink list with all sinks of the same tiled display being sorted by 'ti

    - +

    @@ -4022,7 +3772,7 @@ Swap the ordering of the sinks in the topology's sink list. All sink information

    - +

    @@ -4060,7 +3810,7 @@ This function is the delay/sleep function for the +
    @@ -4110,22 +3860,6 @@ This function will write a global unique identifier (GUID) to the target Display
    Returns:
    None.
    Note:
    None.
    - -

    -


    Variable Documentation

    - -
    -
    -
    - - - -
    XDptx_DmtMode XDptx_DmtModes[]
    -
    -
    - -

    -This table contains the main stream attributes for various standard resolutions. Each entry is of the format: 1) XDPTX_VM_<HRES>x<VRES>_<REFRESH (HZ)>_P(_RB = Reduced Blanking) 2) Display Monitor Timing (DMT) ID 3) Horizontal resolution (pixels) 4) Vertical resolution (lines) 5) Pixel clock (KHz) 6) Interlaced (0=non-interlaced|1=interlaced) 7) Horizontal sync polarity (0=positive|1=negative) 8) Vertical sync polarity (0=positive|1=negative) 9) Horizontal front porch (pixels) 10) Horizontal sync time (pixels) 11) Horizontal back porch (pixels) 12) Vertical front porch (lines) 13) Vertical sync time (lines) 14) Vertical back porch (lines)

    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__edid_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__edid_8c.html index 9933ffbd..3095e160 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__edid_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__edid_8c.html @@ -36,23 +36,23 @@ This file contains functions related to accessing the Extended Display Identific - + - + - + - + - + - + - +

    Functions

    u32 XDptx_GetEdid (XDptx *InstancePtr, u8 *Edid)
    u32 XDptx_GetEdid (XDptx *InstancePtr, u8 *Edid)
    u32 XDptx_GetRemoteEdid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid)
    u32 XDptx_GetRemoteEdid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid)
    u32 XDptx_GetEdidBlock (XDptx *InstancePtr, u8 *Data, u8 BlockNum)
    u32 XDptx_GetEdidBlock (XDptx *InstancePtr, u8 *Data, u8 BlockNum)
    u32 XDptx_GetRemoteEdidBlock (XDptx *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_GetRemoteEdidBlock (XDptx *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_GetRemoteEdidDispIdExt (XDptx *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_GetRemoteEdidDispIdExt (XDptx *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_GetDispIdDataBlock (u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr)
    u32 XDptx_GetDispIdDataBlock (u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr)
    u32 XDptx_GetRemoteTiledDisplayDb (XDptx *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr)
    u32 XDptx_GetRemoteTiledDisplayDb (XDptx *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr)


    Function Documentation

    - +
    @@ -99,7 +99,7 @@ Given a section tag, search for and retrieve the appropriate section data block

    - +

    @@ -139,7 +139,7 @@ This function retrieves an immediately connected RX device's Extended Display Id

    - +

    @@ -186,7 +186,7 @@ Retrieve an immediately connected RX device's Extended Display Identification Da

    - +

    @@ -240,7 +240,7 @@ This function retrieves a remote RX device's Extended Display Identification Dat

    - +

    @@ -301,7 +301,7 @@ Retrieve a downstream DisplayPort device's Extended Display Identification Data

    - +

    @@ -355,7 +355,7 @@ Search for and retrieve a downstream DisplayPort device's Extended Display Ident

    - +

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__hw_8h.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__hw_8h.html index 875adb21..8d4f8cec 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__hw_8h.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__hw_8h.html @@ -30,1277 +30,1280 @@ This header file contains the identifiers and low-level driver functions (or mac ----- ---- -------- ----------------------------------------------- 1.0 als 05/17/14 Initial release. als 08/03/14 Initial MST addition. - + 3.0 als 12/16/14 Stream naming now starts at 1 to follow IP. +

    #include "xil_io.h"
    #include "xil_types.h"

    - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +

    DPTX core registers: Link configuration field.

    #define XDPTX_LINK_BW_SET   0x0000
    #define XDPTX_LINK_BW_SET   0x0000
    #define XDPTX_LANE_COUNT_SET   0x0004
    #define XDPTX_LANE_COUNT_SET   0x0004
    #define XDPTX_ENHANCED_FRAME_EN   0x0008
    #define XDPTX_ENHANCED_FRAME_EN   0x0008
    #define XDPTX_TRAINING_PATTERN_SET   0x000C
    #define XDPTX_TRAINING_PATTERN_SET   0x000C
    #define XDPTX_LINK_QUAL_PATTERN_SET   0x0010
    #define XDPTX_LINK_QUAL_PATTERN_SET   0x0010
    #define XDPTX_SCRAMBLING_DISABLE   0x0014
    #define XDPTX_SCRAMBLING_DISABLE   0x0014
    #define XDPTX_DOWNSPREAD_CTRL   0x0018
    #define XDPTX_DOWNSPREAD_CTRL   0x0018
    #define XDPTX_SOFT_RESET   0x001C
    #define XDPTX_SOFT_RESET   0x001C

    DPTX core registers: Core enables.

    #define XDPTX_ENABLE   0x0080
    #define XDPTX_ENABLE   0x0080
    #define XDPTX_ENABLE_MAIN_STREAM   0x0084
    #define XDPTX_ENABLE_MAIN_STREAM   0x0084
    #define XDPTX_ENABLE_SEC_STREAM   0x0088
    #define XDPTX_ENABLE_SEC_STREAM   0x0088
    #define XDPTX_FORCE_SCRAMBLER_RESET   0x00C0
    #define XDPTX_FORCE_SCRAMBLER_RESET   0x00C0
    #define XDPTX_TX_MST_CONFIG   0x00D0
    #define XDPTX_TX_MST_CONFIG   0x00D0

    DPTX core registers: Core ID.

    #define XDPTX_VERSION   0x00F8
    #define XDPTX_VERSION   0x00F8
    #define XDPTX_CORE_ID   0x00FC
    #define XDPTX_CORE_ID   0x00FC

    DPTX core registers: AUX channel interface.

    #define XDPTX_AUX_CMD   0x0100
    #define XDPTX_AUX_CMD   0x0100
    #define XDPTX_AUX_WRITE_FIFO   0x0104
    #define XDPTX_AUX_WRITE_FIFO   0x0104
    #define XDPTX_AUX_ADDRESS   0x0108
    #define XDPTX_AUX_ADDRESS   0x0108
    #define XDPTX_AUX_CLK_DIVIDER   0x010C
    #define XDPTX_AUX_CLK_DIVIDER   0x010C
    #define XDPTX_TX_USER_FIFO_OVERFLOW   0x0110
    #define XDPTX_TX_USER_FIFO_OVERFLOW   0x0110
    #define XDPTX_INTERRUPT_SIG_STATE   0x0130
    #define XDPTX_INTERRUPT_SIG_STATE   0x0130
    #define XDPTX_AUX_REPLY_DATA   0x0134
    #define XDPTX_AUX_REPLY_DATA   0x0134
    #define XDPTX_AUX_REPLY_CODE   0x0138
    #define XDPTX_AUX_REPLY_CODE   0x0138
    #define XDPTX_AUX_REPLY_COUNT   0x013C
    #define XDPTX_AUX_REPLY_COUNT   0x013C
    #define XDPTX_INTERRUPT_STATUS   0x0140
    #define XDPTX_INTERRUPT_STATUS   0x0140
    #define XDPTX_INTERRUPT_MASK   0x0144
    #define XDPTX_INTERRUPT_MASK   0x0144
    #define XDPTX_REPLY_DATA_COUNT   0x0148
    #define XDPTX_REPLY_DATA_COUNT   0x0148
    #define XDPTX_REPLY_STATUS   0x014C
    #define XDPTX_REPLY_STATUS   0x014C
    #define XDPTX_HPD_DURATION   0x0150
    #define XDPTX_HPD_DURATION   0x0150

    DPTX core registers: Main stream attributes for SST / MST STREAM0.

    #define XDPTX_STREAM0_MSA_START   0x0180

    DPTX core registers: Main stream attributes for SST / MST STREAM1.

    #define XDPTX_STREAM1_MSA_START   0x0180
    #define XDPTX_MAIN_STREAM_HTOTAL   0x0180
    #define XDPTX_MAIN_STREAM_HTOTAL   0x0180
    #define XDPTX_MAIN_STREAM_VTOTAL   0x0184
    #define XDPTX_MAIN_STREAM_VTOTAL   0x0184
    #define XDPTX_MAIN_STREAM_POLARITY   0x0188
    #define XDPTX_MAIN_STREAM_POLARITY   0x0188
    #define XDPTX_MAIN_STREAM_HSWIDTH   0x018C
    #define XDPTX_MAIN_STREAM_HSWIDTH   0x018C
    #define XDPTX_MAIN_STREAM_VSWIDTH   0x0190
    #define XDPTX_MAIN_STREAM_VSWIDTH   0x0190
    #define XDPTX_MAIN_STREAM_HRES   0x0194
    #define XDPTX_MAIN_STREAM_HRES   0x0194
    #define XDPTX_MAIN_STREAM_VRES   0x0198
    #define XDPTX_MAIN_STREAM_VRES   0x0198
    #define XDPTX_MAIN_STREAM_HSTART   0x019C
    #define XDPTX_MAIN_STREAM_HSTART   0x019C
    #define XDPTX_MAIN_STREAM_VSTART   0x01A0
    #define XDPTX_MAIN_STREAM_VSTART   0x01A0
    #define XDPTX_MAIN_STREAM_MISC0   0x01A4
    #define XDPTX_MAIN_STREAM_MISC0   0x01A4
    #define XDPTX_MAIN_STREAM_MISC1   0x01A8
    #define XDPTX_MAIN_STREAM_MISC1   0x01A8
    #define XDPTX_M_VID   0x01AC
    #define XDPTX_M_VID   0x01AC
    #define XDPTX_TU_SIZE   0x01B0
    #define XDPTX_TU_SIZE   0x01B0
    #define XDPTX_N_VID   0x01B4
    #define XDPTX_N_VID   0x01B4
    #define XDPTX_USER_PIXEL_WIDTH   0x01B8
    #define XDPTX_USER_PIXEL_WIDTH   0x01B8
    #define XDPTX_USER_DATA_COUNT_PER_LANE   0x01BC
    #define XDPTX_USER_DATA_COUNT_PER_LANE   0x01BC
    #define XDPTX_MAIN_STREAM_INTERLACED   0x01C0
    #define XDPTX_MAIN_STREAM_INTERLACED   0x01C0
    #define XDPTX_MIN_BYTES_PER_TU   0x01C4
    #define XDPTX_MIN_BYTES_PER_TU   0x01C4
    #define XDPTX_FRAC_BYTES_PER_TU   0x01C8
    #define XDPTX_FRAC_BYTES_PER_TU   0x01C8
    #define XDPTX_INIT_WAIT   0x01CC
    #define XDPTX_INIT_WAIT   0x01CC
    #define XDPTX_STREAM0   0x01D0
    #define XDPTX_STREAM1   0x01D0
    #define XDPTX_STREAM1   0x01D4
    #define XDPTX_STREAM2   0x01D4
    #define XDPTX_STREAM2   0x01D8
    #define XDPTX_STREAM3   0x01D8
    #define XDPTX_STREAM3   0x01DC
    #define XDPTX_STREAM4   0x01DC

    DPTX core registers: PHY configuration status.

    #define XDPTX_PHY_CONFIG   0x0200
    #define XDPTX_PHY_CONFIG   0x0200
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_0   0x0220
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_0   0x0220
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_1   0x0224
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_1   0x0224
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_2   0x0228
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_2   0x0228
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_3   0x022C
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_3   0x022C
    #define XDPTX_PHY_TRANSMIT_PRBS7   0x0230
    #define XDPTX_PHY_TRANSMIT_PRBS7   0x0230
    #define XDPTX_PHY_CLOCK_SELECT   0x0234
    #define XDPTX_PHY_CLOCK_SELECT   0x0234
    #define XDPTX_TX_PHY_POWER_DOWN   0x0238
    #define XDPTX_TX_PHY_POWER_DOWN   0x0238
    #define XDPTX_PHY_PRECURSOR_LANE_0   0x023C
    #define XDPTX_PHY_PRECURSOR_LANE_0   0x023C
    #define XDPTX_PHY_PRECURSOR_LANE_1   0x0240
    #define XDPTX_PHY_PRECURSOR_LANE_1   0x0240
    #define XDPTX_PHY_PRECURSOR_LANE_2   0x0244
    #define XDPTX_PHY_PRECURSOR_LANE_2   0x0244
    #define XDPTX_PHY_PRECURSOR_LANE_3   0x0248
    #define XDPTX_PHY_PRECURSOR_LANE_3   0x0248
    #define XDPTX_PHY_POSTCURSOR_LANE_0   0x024C
    #define XDPTX_PHY_POSTCURSOR_LANE_0   0x024C
    #define XDPTX_PHY_POSTCURSOR_LANE_1   0x0250
    #define XDPTX_PHY_POSTCURSOR_LANE_1   0x0250
    #define XDPTX_PHY_POSTCURSOR_LANE_2   0x0254
    #define XDPTX_PHY_POSTCURSOR_LANE_2   0x0254
    #define XDPTX_PHY_POSTCURSOR_LANE_3   0x0258
    #define XDPTX_PHY_POSTCURSOR_LANE_3   0x0258
    #define XDPTX_PHY_STATUS   0x0280
    #define XDPTX_PHY_STATUS   0x0280
    #define XDPTX_GT_DRP_COMMAND   0x02A0
    #define XDPTX_GT_DRP_COMMAND   0x02A0
    #define XDPTX_GT_DRP_READ_DATA   0x02A4
    #define XDPTX_GT_DRP_READ_DATA   0x02A4
    #define XDPTX_GT_DRP_CHANNEL_STATUS   0x02A8
    #define XDPTX_GT_DRP_CHANNEL_STATUS   0x02A8

    DPTX core registers: DisplayPort audio.

    #define XDPTX_TX_AUDIO_CONTROL   0x0300
    #define XDPTX_TX_AUDIO_CONTROL   0x0300
    #define XDPTX_TX_AUDIO_CHANNELS   0x0304
    #define XDPTX_TX_AUDIO_CHANNELS   0x0304
    #define XDPTX_TX_AUDIO_INFO_DATA   0x0308
    #define XDPTX_TX_AUDIO_INFO_DATA   0x0308
    #define XDPTX_TX_AUDIO_MAUD   0x0328
    #define XDPTX_TX_AUDIO_MAUD   0x0328
    #define XDPTX_TX_AUDIO_NAUD   0x032C
    #define XDPTX_TX_AUDIO_NAUD   0x032C
    #define XDPTX_TX_AUDIO_EXT_DATA   0x0330
    #define XDPTX_TX_AUDIO_EXT_DATA   0x0330

    DPTX core registers: Main stream attributes for MST STREAM1, 2, and 3.

    #define XDPTX_STREAM1_MSA_START   0x0500

    DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4.

    #define XDPTX_STREAM2_MSA_START   0x0500
    #define XDPTX_STREAM1_MSA_START_OFFSET
    #define XDPTX_STREAM2_MSA_START_OFFSET
    #define XDPTX_STREAM2_MSA_START   0x0550
    #define XDPTX_STREAM3_MSA_START   0x0550
    #define XDPTX_STREAM2_MSA_START_OFFSET
    #define XDPTX_STREAM3_MSA_START_OFFSET
    #define XDPTX_STREAM3_MSA_START   0x05A0
    #define XDPTX_STREAM4_MSA_START   0x05A0
    #define XDPTX_STREAM3_MSA_START_OFFSET
    #define XDPTX_STREAM4_MSA_START_OFFSET

    DPTX core masks, shifts, and register values.

    #define XDPTX_LINK_BW_SET_162GBPS   0x06
    #define XDPTX_LINK_BW_SET_162GBPS   0x06
    #define XDPTX_LINK_BW_SET_270GBPS   0x0A
    #define XDPTX_LINK_BW_SET_270GBPS   0x0A
    #define XDPTX_LINK_BW_SET_540GBPS   0x14
    #define XDPTX_LINK_BW_SET_540GBPS   0x14
    #define XDPTX_LANE_COUNT_SET_1   0x01
    #define XDPTX_LANE_COUNT_SET_1   0x01
    #define XDPTX_LANE_COUNT_SET_2   0x02
    #define XDPTX_LANE_COUNT_SET_2   0x02
    #define XDPTX_LANE_COUNT_SET_4   0x04
    #define XDPTX_LANE_COUNT_SET_4   0x04
    #define XDPTX_TRAINING_PATTERN_SET_OFF   0x0
    #define XDPTX_TRAINING_PATTERN_SET_OFF   0x0
    #define XDPTX_TRAINING_PATTERN_SET_TP1   0x1
    #define XDPTX_TRAINING_PATTERN_SET_TP1   0x1
    #define XDPTX_TRAINING_PATTERN_SET_TP2   0x2
    #define XDPTX_TRAINING_PATTERN_SET_TP2   0x2
    #define XDPTX_TRAINING_PATTERN_SET_TP3   0x3
    #define XDPTX_TRAINING_PATTERN_SET_TP3   0x3
    #define XDPTX_LINK_QUAL_PATTERN_SET_OFF   0x0
    #define XDPTX_LINK_QUAL_PATTERN_SET_OFF   0x0
    #define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1
    #define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1
    #define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES   0x2
    #define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES   0x2
    #define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7   0x3
    #define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7   0x3
    #define XDPTX_SOFT_RESET_VIDEO_STREAM0_MASK   0x00000001
    #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001
    #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000002
    #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002
    #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000004
    #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004
    #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000008
    #define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008
    #define XDPTX_SOFT_RESET_AUX_MASK   0x00000080
    #define XDPTX_SOFT_RESET_AUX_MASK   0x00000080
    #define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F
    #define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F
    #define XDPTX_TX_MST_CONFIG_MST_EN_MASK   0x00000001
    #define XDPTX_TX_MST_CONFIG_MST_EN_MASK   0x00000001
    #define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002
    #define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002
    #define XDPTX_VERSION_INTER_REV_MASK   0x0000000F
    #define XDPTX_VERSION_INTER_REV_MASK   0x0000000F
    #define XDPTX_VERSION_CORE_PATCH_MASK   0x00000030
    #define XDPTX_VERSION_CORE_PATCH_MASK   0x00000030
    #define XDPTX_VERSION_CORE_PATCH_SHIFT   8
    #define XDPTX_VERSION_CORE_PATCH_SHIFT   8
    #define XDPTX_VERSION_CORE_VER_REV_MASK   0x000000C0
    #define XDPTX_VERSION_CORE_VER_REV_MASK   0x000000C0
    #define XDPTX_VERSION_CORE_VER_REV_SHIFT   12
    #define XDPTX_VERSION_CORE_VER_REV_SHIFT   12
    #define XDPTX_VERSION_CORE_VER_MNR_MASK   0x00000F00
    #define XDPTX_VERSION_CORE_VER_MNR_MASK   0x00000F00
    #define XDPTX_VERSION_CORE_VER_MNR_SHIFT   16
    #define XDPTX_VERSION_CORE_VER_MNR_SHIFT   16
    #define XDPTX_VERSION_CORE_VER_MJR_MASK   0x0000F000
    #define XDPTX_VERSION_CORE_VER_MJR_MASK   0x0000F000
    #define XDPTX_VERSION_CORE_VER_MJR_SHIFT   24
    #define XDPTX_VERSION_CORE_VER_MJR_SHIFT   24
    #define XDPTX_CORE_ID_TYPE_MASK   0x0000000F
    #define XDPTX_CORE_ID_TYPE_MASK   0x0000000F
    #define XDPTX_CORE_ID_TYPE_TX   0x0
    #define XDPTX_CORE_ID_TYPE_TX   0x0
    #define XDPTX_CORE_ID_TYPE_RX   0x1
    #define XDPTX_CORE_ID_TYPE_RX   0x1
    #define XDPTX_CORE_ID_DP_REV_MASK   0x000000F0
    #define XDPTX_CORE_ID_DP_REV_MASK   0x000000F0
    #define XDPTX_CORE_ID_DP_REV_SHIFT   8
    #define XDPTX_CORE_ID_DP_REV_SHIFT   8
    #define XDPTX_CORE_ID_DP_MNR_VER_MASK   0x00000F00
    #define XDPTX_CORE_ID_DP_MNR_VER_MASK   0x00000F00
    #define XDPTX_CORE_ID_DP_MNR_VER_SHIFT   16
    #define XDPTX_CORE_ID_DP_MNR_VER_SHIFT   16
    #define XDPTX_CORE_ID_DP_MJR_VER_MASK   0x0000F000
    #define XDPTX_CORE_ID_DP_MJR_VER_MASK   0x0000F000
    #define XDPTX_CORE_ID_DP_MJR_VER_SHIFT   24
    #define XDPTX_CORE_ID_DP_MJR_VER_SHIFT   24
    #define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F
    #define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F
    #define XDPTX_AUX_CMD_MASK   0x00000F00
    #define XDPTX_AUX_CMD_MASK   0x00000F00
    #define XDPTX_AUX_CMD_SHIFT   8
    #define XDPTX_AUX_CMD_SHIFT   8
    #define XDPTX_AUX_CMD_I2C_WRITE   0x0
    #define XDPTX_AUX_CMD_I2C_WRITE   0x0
    #define XDPTX_AUX_CMD_I2C_READ   0x1
    #define XDPTX_AUX_CMD_I2C_READ   0x1
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS   0x2
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS   0x2
    #define XDPTX_AUX_CMD_I2C_WRITE_MOT   0x4
    #define XDPTX_AUX_CMD_I2C_WRITE_MOT   0x4
    #define XDPTX_AUX_CMD_I2C_READ_MOT   0x5
    #define XDPTX_AUX_CMD_I2C_READ_MOT   0x5
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6
    #define XDPTX_AUX_CMD_WRITE   0x8
    #define XDPTX_AUX_CMD_WRITE   0x8
    #define XDPTX_AUX_CMD_READ   0x9
    #define XDPTX_AUX_CMD_READ   0x9
    #define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000
    #define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000
    #define XDPTX_AUX_CLK_DIVIDER_VAL_MASK   0x0000000F
    #define XDPTX_AUX_CLK_DIVIDER_VAL_MASK   0x0000000F
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0x00000F00
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0x00000F00
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8
    #define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001
    #define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001
    #define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002
    #define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_AUX_REPLY_CODE_ACK   0x0
    #define XDPTX_AUX_REPLY_CODE_ACK   0x0
    #define XDPTX_AUX_REPLY_CODE_I2C_ACK   0x0
    #define XDPTX_AUX_REPLY_CODE_I2C_ACK   0x0
    #define XDPTX_AUX_REPLY_CODE_NACK   0x1
    #define XDPTX_AUX_REPLY_CODE_NACK   0x1
    #define XDPTX_AUX_REPLY_CODE_DEFER   0x2
    #define XDPTX_AUX_REPLY_CODE_DEFER   0x2
    #define XDPTX_AUX_REPLY_CODE_I2C_NACK   0x4
    #define XDPTX_AUX_REPLY_CODE_I2C_NACK   0x4
    #define XDPTX_AUX_REPLY_CODE_I2C_DEFER   0x8
    #define XDPTX_AUX_REPLY_CODE_I2C_DEFER   0x8
    #define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001
    #define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001
    #define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002
    #define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002
    #define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004
    #define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004
    #define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010
    #define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010
    #define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020
    #define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020
    #define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001
    #define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001
    #define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002
    #define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002
    #define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004
    #define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004
    #define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010
    #define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010
    #define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020
    #define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020
    #define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001
    #define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001
    #define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002
    #define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002
    #define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004
    #define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004
    #define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008
    #define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4
    #define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1
    #define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB   0x0
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB   0x0
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422   0x1
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422   0x1
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444   0x2
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444   0x2
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT   5
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT   5
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC   0x0
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC   0x0
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC   0x1
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC   0x1
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC   0x2
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC   0x2
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC   0x3
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC   0x3
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC   0x4
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC   0x4
    #define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1
    #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0010000
    #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0000000
    #define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0010001
    #define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0000001
    #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0010002
    #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0000002
    #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0010100
    #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0000100
    #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0010200
    #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0000200
    #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0010400
    #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0000400
    #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0011000
    #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0001000
    #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x001E000
    #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x000E000
    #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0010003
    #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0000003
    #define XDPTX_PHY_CLOCK_SELECT_162GBPS   0x1
    #define XDPTX_PHY_CLOCK_SELECT_162GBPS   0x1
    #define XDPTX_PHY_CLOCK_SELECT_270GBPS   0x3
    #define XDPTX_PHY_CLOCK_SELECT_270GBPS   0x3
    #define XDPTX_PHY_CLOCK_SELECT_540GBPS   0x5
    #define XDPTX_PHY_CLOCK_SELECT_540GBPS   0x5
    #define XDPTX_VS_LEVEL_0   0x2
    #define XDPTX_VS_LEVEL_0   0x2
    #define XDPTX_VS_LEVEL_1   0x5
    #define XDPTX_VS_LEVEL_1   0x5
    #define XDPTX_VS_LEVEL_2   0x8
    #define XDPTX_VS_LEVEL_2   0x8
    #define XDPTX_VS_LEVEL_3   0xF
    #define XDPTX_VS_LEVEL_3   0xF
    #define XDPTX_VS_LEVEL_OFFSET   0x4
    #define XDPTX_VS_LEVEL_OFFSET   0x4
    #define XDPTX_PE_LEVEL_0   0x00
    #define XDPTX_PE_LEVEL_0   0x00
    #define XDPTX_PE_LEVEL_1   0x0E
    #define XDPTX_PE_LEVEL_1   0x0E
    #define XDPTX_PE_LEVEL_2   0x14
    #define XDPTX_PE_LEVEL_2   0x14
    #define XDPTX_PE_LEVEL_3   0x1B
    #define XDPTX_PE_LEVEL_3   0x1B
    #define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003
    #define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003
    #define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C
    #define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C
    #define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010
    #define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010
    #define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020
    #define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020
    #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000020
    #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000040
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30
    #define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F
    #define XDPTX_PHY_STATUS_LANES_0_1_READY_MASK   0x00000013
    #define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F
    #define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F
    #define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080
    #define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00
    #define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16

    DisplayPort Configuration Data: Receiver capability field.

    #define XDPTX_DPCD_REV   0x00000
    #define XDPTX_DPCD_REV   0x00000
    #define XDPTX_DPCD_MAX_LINK_RATE   0x00001
    #define XDPTX_DPCD_MAX_LINK_RATE   0x00001
    #define XDPTX_DPCD_MAX_LANE_COUNT   0x00002
    #define XDPTX_DPCD_MAX_LANE_COUNT   0x00002
    #define XDPTX_DPCD_MAX_DOWNSPREAD   0x00003
    #define XDPTX_DPCD_MAX_DOWNSPREAD   0x00003
    #define XDPTX_DPCD_NORP_PWR_V_CAP   0x00004
    #define XDPTX_DPCD_NORP_PWR_V_CAP   0x00004
    #define XDPTX_DPCD_DOWNSP_PRESENT   0x00005
    #define XDPTX_DPCD_DOWNSP_PRESENT   0x00005
    #define XDPTX_DPCD_ML_CH_CODING_CAP   0x00006
    #define XDPTX_DPCD_ML_CH_CODING_CAP   0x00006
    #define XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI   0x00007
    #define XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI   0x00007
    #define XDPTX_DPCD_RX_PORT0_CAP_0   0x00008
    #define XDPTX_DPCD_RX_PORT0_CAP_0   0x00008
    #define XDPTX_DPCD_RX_PORT0_CAP_1   0x00009
    #define XDPTX_DPCD_RX_PORT0_CAP_1   0x00009
    #define XDPTX_DPCD_RX_PORT1_CAP_0   0x0000A
    #define XDPTX_DPCD_RX_PORT1_CAP_0   0x0000A
    #define XDPTX_DPCD_RX_PORT1_CAP_1   0x0000B
    #define XDPTX_DPCD_RX_PORT1_CAP_1   0x0000B
    #define XDPTX_DPCD_I2C_SPEED_CTL_CAP   0x0000C
    #define XDPTX_DPCD_I2C_SPEED_CTL_CAP   0x0000C
    #define XDPTX_DPCD_EDP_CFG_CAP   0x0000D
    #define XDPTX_DPCD_EDP_CFG_CAP   0x0000D
    #define XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL   0x0000E
    #define XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL   0x0000E
    #define XDPTX_DPCD_ADAPTER_CAP   0x0000F
    #define XDPTX_DPCD_ADAPTER_CAP   0x0000F
    #define XDPTX_DPCD_FAUX_CAP   0x00020
    #define XDPTX_DPCD_FAUX_CAP   0x00020
    #define XDPTX_DPCD_MSTM_CAP   0x00021
    #define XDPTX_DPCD_MSTM_CAP   0x00021
    #define XDPTX_DPCD_NUM_AUDIO_EPS   0x00022
    #define XDPTX_DPCD_NUM_AUDIO_EPS   0x00022
    #define XDPTX_DPCD_AV_GRANULARITY   0x00023
    #define XDPTX_DPCD_AV_GRANULARITY   0x00023
    #define XDPTX_DPCD_AUD_DEC_LAT_7_0   0x00024
    #define XDPTX_DPCD_AUD_DEC_LAT_7_0   0x00024
    #define XDPTX_DPCD_AUD_DEC_LAT_15_8   0x00025
    #define XDPTX_DPCD_AUD_DEC_LAT_15_8   0x00025
    #define XDPTX_DPCD_AUD_PP_LAT_7_0   0x00026
    #define XDPTX_DPCD_AUD_PP_LAT_7_0   0x00026
    #define XDPTX_DPCD_AUD_PP_LAT_15_8   0x00027
    #define XDPTX_DPCD_AUD_PP_LAT_15_8   0x00027
    #define XDPTX_DPCD_VID_INTER_LAT   0x00028
    #define XDPTX_DPCD_VID_INTER_LAT   0x00028
    #define XDPTX_DPCD_VID_PROG_LAT   0x00029
    #define XDPTX_DPCD_VID_PROG_LAT   0x00029
    #define XDPTX_DPCD_REP_LAT   0x0002A
    #define XDPTX_DPCD_REP_LAT   0x0002A
    #define XDPTX_DPCD_AUD_DEL_INS_7_0   0x0002B
    #define XDPTX_DPCD_AUD_DEL_INS_7_0   0x0002B
    #define XDPTX_DPCD_AUD_DEL_INS_15_8   0x0002C
    #define XDPTX_DPCD_AUD_DEL_INS_15_8   0x0002C
    #define XDPTX_DPCD_AUD_DEL_INS_23_16   0x0002D
    #define XDPTX_DPCD_AUD_DEL_INS_23_16   0x0002D
    #define XDPTX_DPCD_GUID   0x00030
    #define XDPTX_DPCD_GUID   0x00030
    #define XDPTX_DPCD_RX_GTC_VALUE_7_0   0x00054
    #define XDPTX_DPCD_RX_GTC_VALUE_7_0   0x00054
    #define XDPTX_DPCD_RX_GTC_VALUE_15_8   0x00055
    #define XDPTX_DPCD_RX_GTC_VALUE_15_8   0x00055
    #define XDPTX_DPCD_RX_GTC_VALUE_23_16   0x00056
    #define XDPTX_DPCD_RX_GTC_VALUE_23_16   0x00056
    #define XDPTX_DPCD_RX_GTC_VALUE_31_24   0x00057
    #define XDPTX_DPCD_RX_GTC_VALUE_31_24   0x00057
    #define XDPTX_DPCD_RX_GTC_MSTR_REQ   0x00058
    #define XDPTX_DPCD_RX_GTC_MSTR_REQ   0x00058
    #define XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE   0x00059
    #define XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE   0x00059
    #define XDPTX_DPCD_DOWNSP_0_CAP   0x00080
    #define XDPTX_DPCD_DOWNSP_0_CAP   0x00080
    #define XDPTX_DPCD_DOWNSP_1_CAP   0x00081
    #define XDPTX_DPCD_DOWNSP_1_CAP   0x00081
    #define XDPTX_DPCD_DOWNSP_2_CAP   0x00082
    #define XDPTX_DPCD_DOWNSP_2_CAP   0x00082
    #define XDPTX_DPCD_DOWNSP_3_CAP   0x00083
    #define XDPTX_DPCD_DOWNSP_3_CAP   0x00083
    #define XDPTX_DPCD_DOWNSP_0_DET_CAP   0x00080
    #define XDPTX_DPCD_DOWNSP_0_DET_CAP   0x00080
    #define XDPTX_DPCD_DOWNSP_1_DET_CAP   0x00084
    #define XDPTX_DPCD_DOWNSP_1_DET_CAP   0x00084
    #define XDPTX_DPCD_DOWNSP_2_DET_CAP   0x00088
    #define XDPTX_DPCD_DOWNSP_2_DET_CAP   0x00088
    #define XDPTX_DPCD_DOWNSP_3_DET_CAP   0x0008C
    #define XDPTX_DPCD_DOWNSP_3_DET_CAP   0x0008C

    DisplayPort Configuration Data: Link configuration field.

    #define XDPTX_DPCD_LINK_BW_SET   0x00100
    #define XDPTX_DPCD_LINK_BW_SET   0x00100
    #define XDPTX_DPCD_LANE_COUNT_SET   0x00101
    #define XDPTX_DPCD_LANE_COUNT_SET   0x00101
    #define XDPTX_DPCD_TP_SET   0x00102
    #define XDPTX_DPCD_TP_SET   0x00102
    #define XDPTX_DPCD_TRAINING_LANE0_SET   0x00103
    #define XDPTX_DPCD_TRAINING_LANE0_SET   0x00103
    #define XDPTX_DPCD_TRAINING_LANE1_SET   0x00104
    #define XDPTX_DPCD_TRAINING_LANE1_SET   0x00104
    #define XDPTX_DPCD_TRAINING_LANE2_SET   0x00105
    #define XDPTX_DPCD_TRAINING_LANE2_SET   0x00105
    #define XDPTX_DPCD_TRAINING_LANE3_SET   0x00106
    #define XDPTX_DPCD_TRAINING_LANE3_SET   0x00106
    #define XDPTX_DPCD_DOWNSPREAD_CTRL   0x00107
    #define XDPTX_DPCD_DOWNSPREAD_CTRL   0x00107
    #define XDPTX_DPCD_ML_CH_CODING_SET   0x00108
    #define XDPTX_DPCD_ML_CH_CODING_SET   0x00108
    #define XDPTX_DPCD_I2C_SPEED_CTL_SET   0x00109
    #define XDPTX_DPCD_I2C_SPEED_CTL_SET   0x00109
    #define XDPTX_DPCD_EDP_CFG_SET   0x0010A
    #define XDPTX_DPCD_EDP_CFG_SET   0x0010A
    #define XDPTX_DPCD_LINK_QUAL_LANE0_SET   0x0010B
    #define XDPTX_DPCD_LINK_QUAL_LANE0_SET   0x0010B
    #define XDPTX_DPCD_LINK_QUAL_LANE1_SET   0x0010C
    #define XDPTX_DPCD_LINK_QUAL_LANE1_SET   0x0010C
    #define XDPTX_DPCD_LINK_QUAL_LANE2_SET   0x0010D
    #define XDPTX_DPCD_LINK_QUAL_LANE2_SET   0x0010D
    #define XDPTX_DPCD_LINK_QUAL_LANE3_SET   0x0010E
    #define XDPTX_DPCD_LINK_QUAL_LANE3_SET   0x0010E
    #define XDPTX_DPCD_TRAINING_LANE0_1_SET2   0x0010F
    #define XDPTX_DPCD_TRAINING_LANE0_1_SET2   0x0010F
    #define XDPTX_DPCD_TRAINING_LANE2_3_SET2   0x00110
    #define XDPTX_DPCD_TRAINING_LANE2_3_SET2   0x00110
    #define XDPTX_DPCD_MSTM_CTRL   0x00111
    #define XDPTX_DPCD_MSTM_CTRL   0x00111
    #define XDPTX_DPCD_AUDIO_DELAY_7_0   0x00112
    #define XDPTX_DPCD_AUDIO_DELAY_7_0   0x00112
    #define XDPTX_DPCD_AUDIO_DELAY_15_8   0x00113
    #define XDPTX_DPCD_AUDIO_DELAY_15_8   0x00113
    #define XDPTX_DPCD_AUDIO_DELAY_23_6   0x00114
    #define XDPTX_DPCD_AUDIO_DELAY_23_6   0x00114
    #define XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED   0x00118
    #define XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED   0x00118
    #define XDPTX_DPCD_FAUX_MODE_CTRL   0x00120
    #define XDPTX_DPCD_FAUX_MODE_CTRL   0x00120
    #define XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET   0x00121
    #define XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET   0x00121
    #define XDPTX_DPCD_BACK_CH_STATUS   0x00122
    #define XDPTX_DPCD_BACK_CH_STATUS   0x00122
    #define XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT   0x00123
    #define XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT   0x00123
    #define XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME   0x00125
    #define XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME   0x00125
    #define XDPTX_DPCD_TX_GTC_VALUE_7_0   0x00154
    #define XDPTX_DPCD_TX_GTC_VALUE_7_0   0x00154
    #define XDPTX_DPCD_TX_GTC_VALUE_15_8   0x00155
    #define XDPTX_DPCD_TX_GTC_VALUE_15_8   0x00155
    #define XDPTX_DPCD_TX_GTC_VALUE_23_16   0x00156
    #define XDPTX_DPCD_TX_GTC_VALUE_23_16   0x00156
    #define XDPTX_DPCD_TX_GTC_VALUE_31_24   0x00157
    #define XDPTX_DPCD_TX_GTC_VALUE_31_24   0x00157
    #define XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN   0x00158
    #define XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN   0x00158
    #define XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE   0x00159
    #define XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE   0x00159
    #define XDPTX_DPCD_ADAPTER_CTRL   0x001A0
    #define XDPTX_DPCD_ADAPTER_CTRL   0x001A0
    #define XDPTX_DPCD_BRANCH_DEVICE_CTRL   0x001A1
    #define XDPTX_DPCD_BRANCH_DEVICE_CTRL   0x001A1
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_SET   0x001C0
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_SET   0x001C0
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT   0x001C1
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT   0x001C1
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT   0x001C2
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT   0x001C2

    DisplayPort Configuration Data: Link/sink status field.

    #define XDPTX_DPCD_SINK_COUNT   0x00200
    #define XDPTX_DPCD_SINK_COUNT   0x00200
    #define XDPTX_DPCD_DEVICE_SERVICE_IRQ   0x00201
    #define XDPTX_DPCD_DEVICE_SERVICE_IRQ   0x00201
    #define XDPTX_DPCD_STATUS_LANE_0_1   0x00202
    #define XDPTX_DPCD_STATUS_LANE_0_1   0x00202
    #define XDPTX_DPCD_STATUS_LANE_2_3   0x00203
    #define XDPTX_DPCD_STATUS_LANE_2_3   0x00203
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED   0x00204
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED   0x00204
    #define XDPTX_DPCD_SINK_STATUS   0x00205
    #define XDPTX_DPCD_SINK_STATUS   0x00205
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_1   0x00206
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_1   0x00206
    #define XDPTX_DPCD_ADJ_REQ_LANE_2_3   0x00207
    #define XDPTX_DPCD_ADJ_REQ_LANE_2_3   0x00207
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_0   0x00208
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_0   0x00208
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_1   0x00209
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_1   0x00209
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_2   0x0020A
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_2   0x0020A
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_3   0x0020B
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_3   0x0020B
    #define XDPTX_DPCD_ADJ_REQ_PC2   0x0020C
    #define XDPTX_DPCD_ADJ_REQ_PC2   0x0020C
    #define XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT   0x0020D
    #define XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT   0x0020D
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0   0x00210
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0   0x00210
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1   0x00212
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1   0x00212
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2   0x00214
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2   0x00214
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3   0x00216
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3   0x00216

    DisplayPort Configuration Data: Automated testing sub-field.

    #define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS   0x00280
    #define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS   0x00280
    #define XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET   0x00281
    #define XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET   0x00281
    #define XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL   0x00282
    #define XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL   0x00282
    #define XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS   0x002C0
    #define XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS   0x002C0
    #define XDPTX_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum)   (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)
    #define XDPTX_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum)   (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)

    DisplayPort Configuration Data: Sink control field.

    #define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE   0x00600
    #define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE   0x00600

    DisplayPort Configuration Data: Sideband message buffers.

    #define XDPTX_DPCD_DOWN_REQ   0x01000
    #define XDPTX_DPCD_DOWN_REQ   0x01000
    #define XDPTX_DPCD_UP_REP   0x01200
    #define XDPTX_DPCD_UP_REP   0x01200
    #define XDPTX_DPCD_DOWN_REP   0x01400
    #define XDPTX_DPCD_DOWN_REP   0x01400
    #define XDPTX_DPCD_UP_REQ   0x01600
    #define XDPTX_DPCD_UP_REQ   0x01600

    DisplayPort Configuration Data: Event status indicator field.

    #define XDPTX_DPCD_SINK_COUNT_ESI   0x02002
    #define XDPTX_DPCD_SINK_COUNT_ESI   0x02002
    #define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x02003
    #define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x02003
    #define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x02004
    #define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x02004
    #define XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0   0x02005
    #define XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0   0x02005
    #define XDPTX_DPCD_SINK_LANE0_1_STATUS   0x0200C
    #define XDPTX_DPCD_SINK_LANE0_1_STATUS   0x0200C
    #define XDPTX_DPCD_SINK_LANE2_3_STATUS   0x0200D
    #define XDPTX_DPCD_SINK_LANE2_3_STATUS   0x0200D
    #define XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI   0x0200E
    #define XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI   0x0200E
    #define XDPTX_DPCD_SINK_STATUS_ESI   0x0200F
    #define XDPTX_DPCD_SINK_STATUS_ESI   0x0200F

    DisplayPort Configuration Data: Field addresses and sizes.

    #define XDPTX_DPCD_RECEIVER_CAP_FIELD_START   XDPTX_DPCD_REV
    #define XDPTX_DPCD_RECEIVER_CAP_FIELD_START   XDPTX_DPCD_REV
    #define XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE   0x100
    #define XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE   0x100
    #define XDPTX_DPCD_LINK_CFG_FIELD_START   XDPTX_DPCD_LINK_BW_SET
    #define XDPTX_DPCD_LINK_CFG_FIELD_START   XDPTX_DPCD_LINK_BW_SET
    #define XDPTX_DPCD_LINK_CFG_FIELD_SIZE   0x100
    #define XDPTX_DPCD_LINK_CFG_FIELD_SIZE   0x100
    #define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START   XDPTX_DPCD_SINK_COUNT
    #define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START   XDPTX_DPCD_SINK_COUNT
    #define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE   0x17
    #define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE   0x17

    DisplayPort Configuration Data: Receiver capability field masks,

    shifts, and register values.

    #define XDPTX_DPCD_REV_MNR_MASK   0x0F
    #define XDPTX_DPCD_REV_MNR_MASK   0x0F
    #define XDPTX_DPCD_REV_MJR_MASK   0xF0
    #define XDPTX_DPCD_REV_MJR_MASK   0xF0
    #define XDPTX_DPCD_REV_MJR_SHIFT   4
    #define XDPTX_DPCD_REV_MJR_SHIFT   4
    #define XDPTX_DPCD_MAX_LINK_RATE_162GBPS   0x06
    #define XDPTX_DPCD_MAX_LINK_RATE_162GBPS   0x06
    #define XDPTX_DPCD_MAX_LINK_RATE_270GBPS   0x0A
    #define XDPTX_DPCD_MAX_LINK_RATE_270GBPS   0x0A
    #define XDPTX_DPCD_MAX_LINK_RATE_540GBPS   0x14
    #define XDPTX_DPCD_MAX_LINK_RATE_540GBPS   0x14
    #define XDPTX_DPCD_MAX_LANE_COUNT_MASK   0x1F
    #define XDPTX_DPCD_MAX_LANE_COUNT_MASK   0x1F
    #define XDPTX_DPCD_MAX_LANE_COUNT_1   0x01
    #define XDPTX_DPCD_MAX_LANE_COUNT_1   0x01
    #define XDPTX_DPCD_MAX_LANE_COUNT_2   0x02
    #define XDPTX_DPCD_MAX_LANE_COUNT_2   0x02
    #define XDPTX_DPCD_MAX_LANE_COUNT_4   0x04
    #define XDPTX_DPCD_MAX_LANE_COUNT_4   0x04
    #define XDPTX_DPCD_TPS3_SUPPORT_MASK   0x40
    #define XDPTX_DPCD_TPS3_SUPPORT_MASK   0x40
    #define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK   0x80
    #define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK   0x80
    #define XDPTX_DPCD_MAX_DOWNSPREAD_MASK   0x01
    #define XDPTX_DPCD_MAX_DOWNSPREAD_MASK   0x01
    #define XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK   0x40
    #define XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK   0x40
    #define XDPTX_DPCD_DOWNSP_PRESENT_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_PRESENT_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_TYPE_MASK   0x06
    #define XDPTX_DPCD_DOWNSP_TYPE_MASK   0x06
    #define XDPTX_DPCD_DOWNSP_TYPE_SHIFT   1
    #define XDPTX_DPCD_DOWNSP_TYPE_SHIFT   1
    #define XDPTX_DPCD_DOWNSP_TYPE_DP   0x0
    #define XDPTX_DPCD_DOWNSP_TYPE_DP   0x0
    #define XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII   0x1
    #define XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII   0x1
    #define XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP   0x2
    #define XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP   0x2
    #define XDPTX_DPCD_DOWNSP_TYPE_OTHERS   0x3
    #define XDPTX_DPCD_DOWNSP_TYPE_OTHERS   0x3
    #define XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK   0x08
    #define XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK   0x08
    #define XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK   0x10
    #define XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK   0x10
    #define XDPTX_DPCD_ML_CH_CODING_MASK   0x01
    #define XDPTX_DPCD_ML_CH_CODING_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_COUNT_MASK   0x0F
    #define XDPTX_DPCD_DOWNSP_COUNT_MASK   0x0F
    #define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK   0x40
    #define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK   0x40
    #define XDPTX_DPCD_OUI_SUPPORT_MASK   0x80
    #define XDPTX_DPCD_OUI_SUPPORT_MASK   0x80
    #define XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK   0x02
    #define XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK   0x02
    #define XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK   0x04
    #define XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK   0x04
    #define XDPTX_DPCD_I2C_SPEED_CTL_NONE   0x00
    #define XDPTX_DPCD_I2C_SPEED_CTL_NONE   0x00
    #define XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS   0x01
    #define XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS   0x01
    #define XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS   0x02
    #define XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS   0x02
    #define XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS   0x04
    #define XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS   0x04
    #define XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS   0x08
    #define XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS   0x08
    #define XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS   0x10
    #define XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS   0x10
    #define XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS   0x20
    #define XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS   0x20
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US   0x00
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US   0x00
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS   0x01
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS   0x01
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS   0x02
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS   0x02
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS   0x03
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS   0x03
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS   0x04
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS   0x04
    #define XDPTX_DPCD_FAUX_CAP_MASK   0x01
    #define XDPTX_DPCD_FAUX_CAP_MASK   0x01
    #define XDPTX_DPCD_MST_CAP_MASK   0x01
    #define XDPTX_DPCD_MST_CAP_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK   0x07
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK   0x07
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP   0x0
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP   0x0
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA   0x1
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA   0x1
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI   0x2
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI   0x2
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI   0x3
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI   0x3
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS   0x4
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS   0x4
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP   0x5
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP   0x5
    #define XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK   0x80
    #define XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK   0x80
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK   0xF0
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK   0xF0
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT   4
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT   4
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60   0x1
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60   0x1
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50   0x2
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50   0x2
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60   0x3
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60   0x3
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50   0x4
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50   0x4
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60   0x5
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60   0x5
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50   0x7
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50   0x7
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK   0x03
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK   0x03
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8   0x0
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8   0x0
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10   0x1
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10   0x1
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12   0x2
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12   0x2
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16   0x3
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16   0x3
    #define XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK   0x02
    #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK   0x02
    #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK   0x04
    #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK   0x04

    DisplayPort Configuration Data: Link configuration field masks,

    shifts, and register values.

    #define XDPTX_DPCD_LINK_BW_SET_162GBPS   0x06
    #define XDPTX_DPCD_LINK_BW_SET_162GBPS   0x06
    #define XDPTX_DPCD_LINK_BW_SET_270GBPS   0x0A
    #define XDPTX_DPCD_LINK_BW_SET_270GBPS   0x0A
    #define XDPTX_DPCD_LINK_BW_SET_540GBPS   0x14
    #define XDPTX_DPCD_LINK_BW_SET_540GBPS   0x14
    #define XDPTX_DPCD_LANE_COUNT_SET_MASK   0x1F
    #define XDPTX_DPCD_LANE_COUNT_SET_MASK   0x1F
    #define XDPTX_DPCD_LANE_COUNT_SET_1   0x01
    #define XDPTX_DPCD_LANE_COUNT_SET_1   0x01
    #define XDPTX_DPCD_LANE_COUNT_SET_2   0x02
    #define XDPTX_DPCD_LANE_COUNT_SET_2   0x02
    #define XDPTX_DPCD_LANE_COUNT_SET_4   0x04
    #define XDPTX_DPCD_LANE_COUNT_SET_4   0x04
    #define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK   0x80
    #define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK   0x80
    #define XDPTX_DPCD_TP_SEL_MASK   0x03
    #define XDPTX_DPCD_TP_SEL_MASK   0x03
    #define XDPTX_DPCD_TP_SEL_OFF   0x0
    #define XDPTX_DPCD_TP_SEL_OFF   0x0
    #define XDPTX_DPCD_TP_SEL_TP1   0x1
    #define XDPTX_DPCD_TP_SEL_TP1   0x1
    #define XDPTX_DPCD_TP_SEL_TP2   0x2
    #define XDPTX_DPCD_TP_SEL_TP2   0x2
    #define XDPTX_DPCD_TP_SEL_TP3   0x3
    #define XDPTX_DPCD_TP_SEL_TP3   0x3
    #define XDPTX_DPCD_TP_SET_LQP_MASK   0x06
    #define XDPTX_DPCD_TP_SET_LQP_MASK   0x06
    #define XDPTX_DPCD_TP_SET_LQP_SHIFT   2
    #define XDPTX_DPCD_TP_SET_LQP_SHIFT   2
    #define XDPTX_DPCD_TP_SET_LQP_OFF   0x0
    #define XDPTX_DPCD_TP_SET_LQP_OFF   0x0
    #define XDPTX_DPCD_TP_SET_LQP_D102_TEST   0x1
    #define XDPTX_DPCD_TP_SET_LQP_D102_TEST   0x1
    #define XDPTX_DPCD_TP_SET_LQP_SER_MES   0x2
    #define XDPTX_DPCD_TP_SET_LQP_SER_MES   0x2
    #define XDPTX_DPCD_TP_SET_LQP_PRBS7   0x3
    #define XDPTX_DPCD_TP_SET_LQP_PRBS7   0x3
    #define XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK   0x10
    #define XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK   0x10
    #define XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK   0x20
    #define XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK   0x20
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK   0xC0
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK   0xC0
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT   6
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT   6
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE   0x0
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE   0x0
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE   0x1
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE   0x1
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE   0x2
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE   0x2
    #define XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK   0x03
    #define XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK   0x03
    #define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK   0x04
    #define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK   0x04
    #define XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK   0x18
    #define XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK   0x18
    #define XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT   3
    #define XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT   3
    #define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK   0x20
    #define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK   0x20
    #define XDPTX_DPCD_SPREAD_AMP_MASK   0x10
    #define XDPTX_DPCD_SPREAD_AMP_MASK   0x10
    #define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK   0x80
    #define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK   0x80
    #define XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK   0x03
    #define XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK   0x03
    #define XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK   0x04
    #define XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK   0x04
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK   0x30
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK   0x30
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT   4
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT   4
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK   0x40
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK   0x40
    #define XDPTX_DPCD_MST_EN_MASK   0x01
    #define XDPTX_DPCD_MST_EN_MASK   0x01
    #define XDPTX_DPCD_UP_REQ_EN_MASK   0x02
    #define XDPTX_DPCD_UP_REQ_EN_MASK   0x02
    #define XDPTX_DPCD_UP_IS_SRC_MASK   0x03
    #define XDPTX_DPCD_UP_IS_SRC_MASK   0x03

    DisplayPort Configuration Data: Link/sink status field masks, shifts,

    and register values.

    #define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK   0x01
    #define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK   0x01
    #define XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK   0x02
    #define XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK   0x02
    #define XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK   0x04
    #define XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK   0x04
    #define XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK   0x10
    #define XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK   0x10
    #define XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK   0x20
    #define XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK   0x20
    #define XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK   0x40
    #define XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK   0x40
    #define XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK   0x01
    #define XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK   0x01
    #define XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK   0x02
    #define XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK   0x02
    #define XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK   0x04
    #define XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK   0x04
    #define XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK   0x10
    #define XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK   0x10
    #define XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK   0x20
    #define XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK   0x20
    #define XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK   0x40
    #define XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK   0x40
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK   0x01
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK   0x01
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK   0x40
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK   0x40
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK   0x80
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK   0x80
    #define XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK   0x01
    #define XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK   0x01
    #define XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK   0x02
    #define XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK   0x02
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK   0x03
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK   0x03
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK   0x0C
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK   0x0C
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT   2
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT   2
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK   0x30
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK   0x30
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT   4
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT   4
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK   0xC0
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK   0xC0
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT   6
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT   6
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK   0x03
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK   0x03
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK   0x0C
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK   0x0C
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT   2
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT   2
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK   0x30
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK   0x30
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT   4
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT   4
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK   0xC0
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK   0xC0
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT   6
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT   6

    Extended Display Identification Data: Field addresses and sizes.

    #define XDPTX_SEGPTR_ADDR   0x30
    #define XDPTX_SEGPTR_ADDR   0x30
    #define XDPTX_EDID_ADDR   0x50
    #define XDPTX_EDID_ADDR   0x50
    #define XDPTX_EDID_BLOCK_SIZE   128
    #define XDPTX_EDID_BLOCK_SIZE   128
    #define XDPTX_EDID_DTD_DD(Num)   (0x36 + (18 * Num))
    #define XDPTX_EDID_DTD_DD(Num)   (0x36 + (18 * Num))
    #define XDPTX_EDID_PTM   XDPTX_EDID_DTD_DD(0)
    #define XDPTX_EDID_PTM   XDPTX_EDID_DTD_DD(0)
    #define XDPTX_EDID_EXT_BLOCK_COUNT   0x7E
    #define XDPTX_EDID_EXT_BLOCK_COUNT   0x7E

    Extended Display Identification Data: Register offsets for the

    Detailed Timing Descriptor (DTD).

    #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB   0x00
    #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB   0x00
    #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB   0x01
    #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB   0x01
    #define XDPTX_EDID_DTD_HRES_LSB   0x02
    #define XDPTX_EDID_DTD_HRES_LSB   0x02
    #define XDPTX_EDID_DTD_HBLANK_LSB   0x03
    #define XDPTX_EDID_DTD_HBLANK_LSB   0x03
    #define XDPTX_EDID_DTD_HRES_HBLANK_U4   0x04
    #define XDPTX_EDID_DTD_HRES_HBLANK_U4   0x04
    #define XDPTX_EDID_DTD_VRES_LSB   0x05
    #define XDPTX_EDID_DTD_VRES_LSB   0x05
    #define XDPTX_EDID_DTD_VBLANK_LSB   0x06
    #define XDPTX_EDID_DTD_VBLANK_LSB   0x06
    #define XDPTX_EDID_DTD_VRES_VBLANK_U4   0x07
    #define XDPTX_EDID_DTD_VRES_VBLANK_U4   0x07
    #define XDPTX_EDID_DTD_HFPORCH_LSB   0x08
    #define XDPTX_EDID_DTD_HFPORCH_LSB   0x08
    #define XDPTX_EDID_DTD_HSPW_LSB   0x09
    #define XDPTX_EDID_DTD_HSPW_LSB   0x09
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4   0x0A
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4   0x0A
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2   0x0B
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2   0x0B
    #define XDPTX_EDID_DTD_HIMGSIZE_MM_LSB   0x0C
    #define XDPTX_EDID_DTD_HIMGSIZE_MM_LSB   0x0C
    #define XDPTX_EDID_DTD_VIMGSIZE_MM_LSB   0x0D
    #define XDPTX_EDID_DTD_VIMGSIZE_MM_LSB   0x0D
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4   0x0E
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4   0x0E
    #define XDPTX_EDID_DTD_HBORDER   0x0F
    #define XDPTX_EDID_DTD_HBORDER   0x0F
    #define XDPTX_EDID_DTD_VBORDER   0x10
    #define XDPTX_EDID_DTD_VBORDER   0x10
    #define XDPTX_EDID_DTD_SIGNAL   0x11
    #define XDPTX_EDID_DTD_SIGNAL   0x11

    Extended Display Identification Data: Masks, shifts, and register

    values.

    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK   0x0F
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK   0x0F
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK   0xF0
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK   0xF0
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT   4
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT   4
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK   0x0F
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK   0x0F
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK   0xF0
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK   0xF0
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT   4
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT   4
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK   0xC0
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK   0xC0
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK   0x30
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK   0x30
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK   0x0C
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK   0x0C
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK   0x03
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK   0x03
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT   6
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT   6
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT   4
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT   4
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT   2
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT   2
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK   0x0F
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK   0x0F
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK   0xF0
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK   0xF0
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT   4
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT   4
    #define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK   0x02
    #define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK   0x02
    #define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK   0x04
    #define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK   0x04
    #define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT   1
    #define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT   1
    #define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT   2
    #define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT   2

    Extended Display Identification Data: Register offsets for the

    DisplayID extension block.

    #define XDPTX_EDID_EXT_BLOCK_TAG   0x00
    #define XDPTX_EDID_EXT_BLOCK_TAG   0x00
    #define XDPTX_DISPID_VER_REV   0x00
    #define XDPTX_DISPID_VER_REV   0x00
    #define XDPTX_DISPID_SIZE   0x01
    #define XDPTX_DISPID_SIZE   0x01
    #define XDPTX_DISPID_TYPE   0x02
    #define XDPTX_DISPID_TYPE   0x02
    #define XDPTX_DISPID_EXT_COUNT   0x03
    #define XDPTX_DISPID_EXT_COUNT   0x03
    #define XDPTX_DISPID_PAYLOAD_START   0x04
    #define XDPTX_DISPID_PAYLOAD_START   0x04
    #define XDPTX_DISPID_DB_SEC_TAG   0x00
    #define XDPTX_DISPID_DB_SEC_TAG   0x00
    #define XDPTX_DISPID_DB_SEC_REV   0x01
    #define XDPTX_DISPID_DB_SEC_REV   0x01
    #define XDPTX_DISPID_DB_SEC_SIZE   0x02
    #define XDPTX_DISPID_DB_SEC_SIZE   0x02

    Extended Display Identification Data: Masks, shifts, and register

    values for the DisplayID extension block.

    #define XDPTX_EDID_EXT_BLOCK_TAG_DISPID   0x70
    #define XDPTX_EDID_EXT_BLOCK_TAG_DISPID   0x70
    #define XDPTX_DISPID_TDT_TAG   0x12
    #define XDPTX_DISPID_TDT_TAG   0x12

    Extended Display Identification Data: Register offsets for the

    Tiled Display Topology (TDT) section data block.

    #define XDPTX_DISPID_TDT_TOP0   0x04
    #define XDPTX_DISPID_TDT_TOP0   0x04
    #define XDPTX_DISPID_TDT_TOP1   0x05
    #define XDPTX_DISPID_TDT_TOP1   0x05
    #define XDPTX_DISPID_TDT_TOP2   0x06
    #define XDPTX_DISPID_TDT_TOP2   0x06
    #define XDPTX_DISPID_TDT_HSIZE0   0x07
    #define XDPTX_DISPID_TDT_HSIZE0   0x07
    #define XDPTX_DISPID_TDT_HSIZE1   0x08
    #define XDPTX_DISPID_TDT_HSIZE1   0x08
    #define XDPTX_DISPID_TDT_VSIZE0   0x09
    #define XDPTX_DISPID_TDT_VSIZE0   0x09
    #define XDPTX_DISPID_TDT_VSIZE1   0x0A
    #define XDPTX_DISPID_TDT_VSIZE1   0x0A
    #define XDPTX_DISPID_TDT_VENID0   0x10
    #define XDPTX_DISPID_TDT_VENID0   0x10
    #define XDPTX_DISPID_TDT_VENID1   0x11
    #define XDPTX_DISPID_TDT_VENID1   0x11
    #define XDPTX_DISPID_TDT_VENID2   0x12
    #define XDPTX_DISPID_TDT_VENID2   0x12
    #define XDPTX_DISPID_TDT_PCODE0   0x13
    #define XDPTX_DISPID_TDT_PCODE0   0x13
    #define XDPTX_DISPID_TDT_PCODE1   0x14
    #define XDPTX_DISPID_TDT_PCODE1   0x14
    #define XDPTX_DISPID_TDT_SN0   0x15
    #define XDPTX_DISPID_TDT_SN0   0x15
    #define XDPTX_DISPID_TDT_SN1   0x16
    #define XDPTX_DISPID_TDT_SN1   0x16
    #define XDPTX_DISPID_TDT_SN2   0x17
    #define XDPTX_DISPID_TDT_SN2   0x17
    #define XDPTX_DISPID_TDT_SN3   0x18
    #define XDPTX_DISPID_TDT_SN3   0x18

    Extended Display Identification Data: Masks, shifts, and register

    values for the Tiled Display Topology (TDT) section data block.

    #define XDPTX_DISPID_TDT_TOP0_HTOT_L_SHIFT   4
    #define XDPTX_DISPID_TDT_TOP0_HTOT_L_SHIFT   4
    #define XDPTX_DISPID_TDT_TOP0_HTOT_L_MASK   (0xF << 4)
    #define XDPTX_DISPID_TDT_TOP0_HTOT_L_MASK   (0xF << 4)
    #define XDPTX_DISPID_TDT_TOP0_VTOT_L_MASK   0xF
    #define XDPTX_DISPID_TDT_TOP0_VTOT_L_MASK   0xF
    #define XDPTX_DISPID_TDT_TOP1_HLOC_L_SHIFT   4
    #define XDPTX_DISPID_TDT_TOP1_HLOC_L_SHIFT   4
    #define XDPTX_DISPID_TDT_TOP1_HLOC_L_MASK   (0xF << 4)
    #define XDPTX_DISPID_TDT_TOP1_HLOC_L_MASK   (0xF << 4)
    #define XDPTX_DISPID_TDT_TOP1_VLOC_L_MASK   0xF
    #define XDPTX_DISPID_TDT_TOP1_VLOC_L_MASK   0xF
    #define XDPTX_DISPID_TDT_TOP2_HTOT_H_SHIFT   6
    #define XDPTX_DISPID_TDT_TOP2_HTOT_H_SHIFT   6
    #define XDPTX_DISPID_TDT_TOP2_HTOT_H_MASK   (0x3 << 6)
    #define XDPTX_DISPID_TDT_TOP2_HTOT_H_MASK   (0x3 << 6)
    #define XDPTX_DISPID_TDT_TOP2_VTOT_H_SHIFT   4
    #define XDPTX_DISPID_TDT_TOP2_VTOT_H_SHIFT   4
    #define XDPTX_DISPID_TDT_TOP2_VTOT_H_MASK   (0x3 << 4)
    #define XDPTX_DISPID_TDT_TOP2_VTOT_H_MASK   (0x3 << 4)
    #define XDPTX_DISPID_TDT_TOP2_HLOC_H_SHIFT   2
    #define XDPTX_DISPID_TDT_TOP2_HLOC_H_SHIFT   2
    #define XDPTX_DISPID_TDT_TOP2_HLOC_H_MASK   (0x3 << 2)
    #define XDPTX_DISPID_TDT_TOP2_HLOC_H_MASK   (0x3 << 2)
    #define XDPTX_DISPID_TDT_TOP2_VLOC_H_MASK   0x3
    #define XDPTX_DISPID_TDT_TOP2_VLOC_H_MASK   0x3

    Stream identification.

    #define XDPTX_STREAM_ID0   0
    #define XDPTX_STREAM_ID1   1
    #define XDPTX_STREAM_ID1   1
    #define XDPTX_STREAM_ID2   2
    #define XDPTX_STREAM_ID2   2
    #define XDPTX_STREAM_ID3   3
    #define XDPTX_STREAM_ID3   3
    #define XDPTX_STREAM_ID4   4

    Sideband message codes when the driver is in MST mode.

    #define XDPTX_SBMSG_LINK_ADDRESS   0x01
    #define XDPTX_SBMSG_LINK_ADDRESS   0x01
    #define XDPTX_SBMSG_ENUM_PATH_RESOURCES   0x10
    #define XDPTX_SBMSG_ENUM_PATH_RESOURCES   0x10
    #define XDPTX_SBMSG_ALLOCATE_PAYLOAD   0x11
    #define XDPTX_SBMSG_ALLOCATE_PAYLOAD   0x11
    #define XDPTX_SBMSG_CLEAR_PAYLOAD_ID_TABLE   0x14
    #define XDPTX_SBMSG_CLEAR_PAYLOAD_ID_TABLE   0x14
    #define XDPTX_SBMSG_REMOTE_DPCD_READ   0x20
    #define XDPTX_SBMSG_REMOTE_DPCD_READ   0x20
    #define XDPTX_SBMSG_REMOTE_DPCD_WRITE   0x21
    #define XDPTX_SBMSG_REMOTE_DPCD_WRITE   0x21
    #define XDPTX_SBMSG_REMOTE_I2C_READ   0x22
    #define XDPTX_SBMSG_REMOTE_I2C_READ   0x22
    #define XDPTX_SBMSG_REMOTE_I2C_WRITE   0x23
    #define XDPTX_SBMSG_REMOTE_I2C_WRITE   0x23

    Register access macro definitions.

    #define XDptx_In32   Xil_In32
    #define XDptx_In32   Xil_In32
    #define XDptx_Out32   Xil_Out32
    #define XDptx_Out32   Xil_Out32

    Defines

    #define XDPTX_VC_PAYLOAD_BUFFER_ADDR   0x0800
    #define XDPTX_VC_PAYLOAD_BUFFER_ADDR   0x0800
    #define XDptx_ReadReg(BaseAddress, RegOffset)   XDptx_In32((BaseAddress) + (RegOffset))
    #define XDptx_ReadReg(BaseAddress, RegOffset)   XDptx_In32((BaseAddress) + (RegOffset))
    #define XDptx_WriteReg(BaseAddress, RegOffset, Data)   XDptx_Out32((BaseAddress) + (RegOffset), (Data))
    #define XDptx_WriteReg(BaseAddress, RegOffset, Data)   XDptx_Out32((BaseAddress) + (RegOffset), (Data))
    #define XDptx_IsEdidExtBlockDispId(Ext)   (Ext[XDPTX_EDID_EXT_BLOCK_TAG] == XDPTX_EDID_EXT_BLOCK_TAG_DISPID)
    #define XDptx_IsEdidExtBlockDispId(Ext)   (Ext[XDPTX_EDID_EXT_BLOCK_TAG] == XDPTX_EDID_EXT_BLOCK_TAG_DISPID)
    #define XDptx_GetDispIdTdtHTotal(Tdt)
    #define XDptx_GetDispIdTdtHTotal(Tdt)
    #define XDptx_GetDispIdTdtVTotal(Tdt)
    #define XDptx_GetDispIdTdtVTotal(Tdt)
    #define XDptx_GetDispIdTdtHLoc(Tdt)
    #define XDptx_GetDispIdTdtHLoc(Tdt)
    #define XDptx_GetDispIdTdtVLoc(Tdt)
    #define XDptx_GetDispIdTdtVLoc(Tdt)
    #define XDptx_GetDispIdTdtNumTiles(Tdt)   (XDptx_GetDispIdTdtHTotal(Tdt) * XDptx_GetDispIdTdtVTotal(Tdt))
    #define XDptx_GetDispIdTdtNumTiles(Tdt)   (XDptx_GetDispIdTdtHTotal(Tdt) * XDptx_GetDispIdTdtVTotal(Tdt))
    #define XDptx_GetDispIdTdtTileOrder(Tdt)
    #define XDptx_GetDispIdTdtTileOrder(Tdt)

    Define Documentation

    - +
    @@ -1312,10 +1315,10 @@ This header file contains the identifiers and low-level driver functions (or mac

    -Specifies the address of current AUX command. +Specifies the address of current AUX command.

    - +

    @@ -1327,10 +1330,10 @@ Specifies the address of current AUX command.

    -Clock divider value for generating the internal 1MHz clock. +Clock divider value for generating the internal 1MHz clock.

    - +

    @@ -1342,10 +1345,10 @@ Clock divider value for generating the internal 1MHz clock.

    -AUX (noise) signal width filter. +AUX (noise) signal width filter.

    - +

    @@ -1357,10 +1360,10 @@ AUX (noise) signal width filter.

    -Shift bits for AUX signal width filter. +Shift bits for AUX signal width filter.

    - +

    @@ -1372,10 +1375,10 @@ Shift bits for AUX signal width filter.

    -Clock divider value. +Clock divider value.

    - +

    @@ -1387,10 +1390,10 @@ Clock divider value.

    -Initiates AUX commands. +Initiates AUX commands.

    - +

    @@ -1402,10 +1405,10 @@ Initiates AUX commands.

    -Address only transfer enable (STOP will be sent after command). +Address only transfer enable (STOP will be sent after command).

    - +

    @@ -1417,10 +1420,10 @@ Address only transfer enable (STOP will be sent after command).

    -I2C-over-AUX read command. +I2C-over-AUX read command.

    - +

    @@ -1432,10 +1435,10 @@ I2C-over-AUX read command.

    -I2C-over-AUX read MOT (middle-of-transaction) command. +I2C-over-AUX read MOT (middle-of-transaction) command.

    - +

    @@ -1447,10 +1450,10 @@ I2C-over-AUX read MOT (middle-of-transaction) command.

    -I2C-over-AUX write command. +I2C-over-AUX write command.

    - +

    @@ -1462,10 +1465,10 @@ I2C-over-AUX write command.

    -I2C-over-AUX write MOT (middle-of-transaction) command. +I2C-over-AUX write MOT (middle-of-transaction) command.

    - +

    @@ -1477,10 +1480,10 @@ I2C-over-AUX write MOT (middle-of-transaction) command.

    -I2C-over-AUX write status command. +I2C-over-AUX write status command.

    - +

    @@ -1492,10 +1495,10 @@ I2C-over-AUX write status command.

    -I2C-over-AUX write status MOT (middle-of- transaction) command. +I2C-over-AUX write status MOT (middle-of- transaction) command.

    - +

    @@ -1507,10 +1510,10 @@ I2C-over-AUX write status MOT (middle-of- transaction) command.

    -AUX command. +AUX command.

    - +

    @@ -1522,10 +1525,10 @@ AUX command.

    -Number of bytes to transfer with the current AUX command. +Number of bytes to transfer with the current AUX command.

    - +

    @@ -1537,10 +1540,10 @@ Number of bytes to transfer with the current AUX command.

    -AUX read command. +AUX read command.

    - +

    @@ -1552,10 +1555,10 @@ AUX read command.

    -Shift bits for command. +Shift bits for command.

    - +

    @@ -1567,10 +1570,10 @@ Shift bits for command.

    -AUX write command. +AUX write command.

    - +

    @@ -1582,10 +1585,10 @@ AUX write command.

    -Reply code received from the most recent AUX command. +Reply code received from the most recent AUX command.

    - +

    @@ -1597,10 +1600,10 @@ Reply code received from the most recent AUX command.

    -AUX command ACKed. +AUX command ACKed.

    - +

    @@ -1612,10 +1615,10 @@ AUX command ACKed.

    -AUX command deferred. +AUX command deferred.

    - +

    @@ -1627,10 +1630,10 @@ AUX command deferred.

    -I2C-over-AUX command not ACKed. +I2C-over-AUX command not ACKed.

    - +

    @@ -1642,10 +1645,10 @@ I2C-over-AUX command not ACKed.

    -I2C-over-AUX command deferred. +I2C-over-AUX command deferred.

    - +

    @@ -1657,10 +1660,10 @@ I2C-over-AUX command deferred.

    -I2C-over-AUX command not ACKed. +I2C-over-AUX command not ACKed.

    - +

    @@ -1672,10 +1675,10 @@ I2C-over-AUX command not ACKed.

    -AUX command not ACKed. +AUX command not ACKed.

    - +

    @@ -1687,10 +1690,10 @@ AUX command not ACKed.

    -Number of reply transactions receieved over AUX. +Number of reply transactions receieved over AUX.

    - +

    @@ -1705,7 +1708,7 @@ Number of reply transactions receieved over AUX. Reply data received during the AUX reply.

    - +

    @@ -1720,7 +1723,7 @@ Reply data received during the AUX reply. Write data for the current AUX command.

    - +

    @@ -1735,7 +1738,7 @@ Write data for the current AUX command. DisplayPort revision.

    - +

    @@ -1750,7 +1753,7 @@ DisplayPort revision. DisplayPort protocol major version.

    - +

    @@ -1765,7 +1768,7 @@ DisplayPort protocol major version. Shift bits for DisplayPort protocol major version.

    - +

    @@ -1780,7 +1783,7 @@ Shift bits for DisplayPort protocol major version. DisplayPort protocol minor version.

    - +

    @@ -1795,7 +1798,7 @@ DisplayPort protocol minor version. Shift bits for DisplayPort protocol major version.

    - +

    @@ -1810,7 +1813,7 @@ Shift bits for DisplayPort protocol major version. DisplayPort protocol revision.

    - +

    @@ -1825,7 +1828,7 @@ DisplayPort protocol revision. Shift bits for DisplayPort protocol revision.

    - +

    @@ -1840,7 +1843,7 @@ Shift bits for DisplayPort protocol revision. Core type.

    - +

    @@ -1855,7 +1858,7 @@ Core type. Core is a receiver.

    - +

    @@ -1870,7 +1873,7 @@ Core is a receiver. Core is a transmitter.

    - +

    @@ -1885,7 +1888,7 @@ Core is a transmitter.

    - +

    @@ -1900,7 +1903,7 @@ Core is a transmitter.

    - +

    @@ -1915,7 +1918,7 @@ Core is a transmitter.

    - +

    @@ -1930,7 +1933,7 @@ Core is a transmitter.

    - +

    @@ -1945,7 +1948,7 @@ Core is a transmitter.

    - +

    @@ -1960,7 +1963,7 @@ Core is a transmitter.

    - +

    @@ -1975,7 +1978,7 @@ Core is a transmitter.

    - +

    @@ -1990,7 +1993,7 @@ Core is a transmitter.

    - +

    @@ -2005,7 +2008,7 @@ Core is a transmitter.

    - +

    @@ -2020,7 +2023,7 @@ Core is a transmitter.

    - +

    @@ -2035,7 +2038,7 @@ Core is a transmitter.

    - +

    @@ -2050,7 +2053,7 @@ Core is a transmitter.

    - +

    @@ -2065,7 +2068,7 @@ Core is a transmitter.

    - +

    @@ -2080,7 +2083,7 @@ Core is a transmitter.

    - +

    @@ -2095,7 +2098,7 @@ Core is a transmitter.

    - +

    @@ -2110,7 +2113,7 @@ Core is a transmitter.

    - +

    @@ -2125,7 +2128,7 @@ Core is a transmitter.

    - +

    @@ -2140,7 +2143,7 @@ Core is a transmitter.

    - +

    @@ -2155,7 +2158,7 @@ Core is a transmitter.

    - +

    @@ -2170,7 +2173,7 @@ Core is a transmitter.

    - +

    @@ -2185,7 +2188,7 @@ Core is a transmitter.

    - +

    @@ -2200,7 +2203,7 @@ Core is a transmitter.

    - +

    @@ -2215,7 +2218,7 @@ Core is a transmitter.

    - +

    @@ -2230,7 +2233,7 @@ Core is a transmitter.

    - +

    @@ -2245,7 +2248,7 @@ Core is a transmitter.

    - +

    @@ -2260,7 +2263,7 @@ Core is a transmitter.

    - +

    @@ -2275,7 +2278,7 @@ Core is a transmitter.

    - +

    @@ -2290,7 +2293,7 @@ Core is a transmitter.

    - +

    @@ -2305,7 +2308,7 @@ Core is a transmitter.

    - +

    @@ -2320,7 +2323,7 @@ Core is a transmitter.

    - +

    @@ -2335,7 +2338,7 @@ Core is a transmitter.

    - +

    @@ -2350,7 +2353,7 @@ Core is a transmitter.

    - +

    @@ -2365,7 +2368,7 @@ Core is a transmitter.

    - +

    @@ -2380,7 +2383,7 @@ Core is a transmitter.

    - +

    @@ -2395,7 +2398,7 @@ Core is a transmitter.

    - +

    @@ -2410,7 +2413,7 @@ Core is a transmitter.

    - +

    @@ -2425,7 +2428,7 @@ Core is a transmitter.

    - +

    @@ -2440,7 +2443,7 @@ Core is a transmitter.

    - +

    @@ -2452,10 +2455,10 @@ Core is a transmitter.

    -Enable a 0.5% spreading of the clock. +Enable a 0.5% spreading of the clock.

    - +

    @@ -2470,7 +2473,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2485,7 +2488,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2500,7 +2503,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2515,7 +2518,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2530,7 +2533,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2545,7 +2548,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2560,7 +2563,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2575,7 +2578,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2590,7 +2593,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2605,7 +2608,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2620,7 +2623,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2635,7 +2638,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2650,7 +2653,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2665,7 +2668,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2680,7 +2683,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2695,7 +2698,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2710,7 +2713,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2725,7 +2728,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2740,7 +2743,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2755,7 +2758,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2770,7 +2773,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2785,7 +2788,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2800,7 +2803,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2815,7 +2818,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2830,7 +2833,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2845,7 +2848,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2860,7 +2863,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2875,7 +2878,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2890,7 +2893,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2905,7 +2908,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2920,7 +2923,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2935,7 +2938,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2950,7 +2953,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2965,7 +2968,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2980,7 +2983,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -2995,7 +2998,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3010,7 +3013,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3025,7 +3028,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3040,7 +3043,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3055,7 +3058,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3070,7 +3073,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3085,7 +3088,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3100,7 +3103,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3115,7 +3118,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3130,7 +3133,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3145,7 +3148,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3160,7 +3163,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3175,7 +3178,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3190,7 +3193,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3205,7 +3208,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3220,7 +3223,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3235,7 +3238,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3250,7 +3253,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3265,7 +3268,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3280,7 +3283,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3295,7 +3298,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3310,7 +3313,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3325,7 +3328,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3340,7 +3343,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3355,7 +3358,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3370,7 +3373,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3385,7 +3388,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3400,7 +3403,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3415,7 +3418,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3430,7 +3433,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3445,7 +3448,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3460,7 +3463,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3475,7 +3478,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3490,7 +3493,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3505,7 +3508,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3520,7 +3523,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3535,7 +3538,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3550,7 +3553,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3565,7 +3568,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3580,7 +3583,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3595,7 +3598,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3610,7 +3613,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3625,7 +3628,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3640,7 +3643,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3655,7 +3658,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3670,7 +3673,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3685,7 +3688,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3700,7 +3703,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3715,7 +3718,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3730,7 +3733,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3745,7 +3748,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3760,7 +3763,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3775,7 +3778,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3790,7 +3793,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3805,7 +3808,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3820,7 +3823,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3835,7 +3838,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3850,7 +3853,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3865,7 +3868,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3880,7 +3883,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3895,7 +3898,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3910,7 +3913,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3925,7 +3928,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3940,7 +3943,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3955,7 +3958,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3970,7 +3973,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -3985,7 +3988,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4000,7 +4003,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4015,7 +4018,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4030,7 +4033,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4045,7 +4048,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4060,7 +4063,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4075,7 +4078,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4090,7 +4093,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4105,7 +4108,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4120,7 +4123,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4135,7 +4138,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4150,7 +4153,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4165,7 +4168,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4180,7 +4183,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4195,7 +4198,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4210,7 +4213,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4225,7 +4228,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4240,7 +4243,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4255,7 +4258,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4270,7 +4273,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4285,7 +4288,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4300,7 +4303,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4315,7 +4318,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4330,7 +4333,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4345,7 +4348,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4360,7 +4363,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4375,7 +4378,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4390,7 +4393,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4405,7 +4408,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4420,7 +4423,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4435,7 +4438,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4450,7 +4453,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4465,7 +4468,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4480,7 +4483,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4495,7 +4498,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4510,7 +4513,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4525,7 +4528,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4540,7 +4543,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4555,7 +4558,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4570,7 +4573,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4585,7 +4588,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4600,7 +4603,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4615,7 +4618,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4630,7 +4633,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4645,7 +4648,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4660,7 +4663,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4675,7 +4678,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4690,7 +4693,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4705,7 +4708,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4720,7 +4723,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4735,7 +4738,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4750,7 +4753,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4765,7 +4768,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4780,7 +4783,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4795,7 +4798,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4810,7 +4813,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4825,7 +4828,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4840,7 +4843,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4855,7 +4858,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4870,7 +4873,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4885,7 +4888,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4900,7 +4903,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4915,7 +4918,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4930,7 +4933,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4945,7 +4948,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4960,7 +4963,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4975,7 +4978,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -4990,7 +4993,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5005,7 +5008,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5020,7 +5023,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5035,7 +5038,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5050,7 +5053,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5065,7 +5068,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5080,7 +5083,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5095,7 +5098,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5110,7 +5113,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5125,7 +5128,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5140,7 +5143,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5155,7 +5158,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5170,7 +5173,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5185,7 +5188,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5200,7 +5203,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5215,7 +5218,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5230,7 +5233,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5245,7 +5248,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5260,7 +5263,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5275,7 +5278,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5290,7 +5293,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5305,7 +5308,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5320,7 +5323,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5335,7 +5338,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5350,7 +5353,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5365,7 +5368,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5380,7 +5383,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5395,7 +5398,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5410,7 +5413,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5425,7 +5428,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5440,7 +5443,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5455,7 +5458,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5470,7 +5473,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5485,7 +5488,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5500,7 +5503,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5515,7 +5518,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5530,7 +5533,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5545,7 +5548,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5560,7 +5563,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5575,7 +5578,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5590,7 +5593,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5605,7 +5608,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5620,7 +5623,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5635,7 +5638,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5650,7 +5653,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5665,7 +5668,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5680,7 +5683,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5695,7 +5698,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5710,7 +5713,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5725,7 +5728,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5740,7 +5743,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5755,7 +5758,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5770,7 +5773,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5785,7 +5788,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5800,7 +5803,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5815,7 +5818,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5830,7 +5833,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5845,7 +5848,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5860,7 +5863,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5875,7 +5878,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5890,7 +5893,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5905,7 +5908,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5920,7 +5923,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5935,7 +5938,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5950,7 +5953,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5965,7 +5968,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5980,7 +5983,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -5995,7 +5998,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6010,7 +6013,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6025,7 +6028,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6040,7 +6043,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6055,7 +6058,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6070,7 +6073,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6085,7 +6088,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6100,7 +6103,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6115,7 +6118,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6130,7 +6133,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6145,7 +6148,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6160,7 +6163,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6175,7 +6178,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6190,7 +6193,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6205,7 +6208,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6220,7 +6223,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6235,7 +6238,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6250,7 +6253,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6265,7 +6268,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6280,7 +6283,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6295,7 +6298,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6310,7 +6313,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6325,7 +6328,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6340,7 +6343,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6355,7 +6358,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6370,7 +6373,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6390,7 +6393,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6405,7 +6408,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6420,7 +6423,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6435,7 +6438,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6450,7 +6453,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6470,7 +6473,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6485,7 +6488,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6500,7 +6503,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6515,7 +6518,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6530,7 +6533,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6545,7 +6548,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6560,7 +6563,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6575,7 +6578,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6590,7 +6593,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6605,7 +6608,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6620,7 +6623,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6635,7 +6638,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6650,7 +6653,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6665,7 +6668,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6680,7 +6683,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6695,7 +6698,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6710,7 +6713,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6725,7 +6728,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6740,7 +6743,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6755,7 +6758,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6770,7 +6773,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6785,7 +6788,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6800,7 +6803,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6815,7 +6818,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6830,7 +6833,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6845,7 +6848,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6860,7 +6863,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6875,7 +6878,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6890,7 +6893,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6905,7 +6908,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6920,7 +6923,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6935,7 +6938,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6950,7 +6953,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6965,7 +6968,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6980,7 +6983,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -6995,7 +6998,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -7010,7 +7013,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -7025,7 +7028,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -7040,7 +7043,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -7055,7 +7058,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -7070,7 +7073,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -7085,7 +7088,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -7100,7 +7103,7 @@ Enable a 0.5% spreading of the clock.

    - +

    @@ -7112,10 +7115,10 @@ Enable a 0.5% spreading of the clock.

    -Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled. +Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled.

    - +

    @@ -7127,10 +7130,10 @@ Enable the basic operations of the DisplayPort TX core or output stuffing symbol

    -Enable transmission of main link video info. +Enable transmission of main link video info.

    - +

    @@ -7142,10 +7145,10 @@ Enable transmission of main link video info.

    -Enable the transmission of secondary link info. +Enable the transmission of secondary link info.

    - +

    @@ -7157,10 +7160,10 @@ Enable the transmission of secondary link info.

    -Enable enhanced framing symbol sequence. +Enable enhanced framing symbol sequence.

    - +

    @@ -7172,10 +7175,10 @@ Enable enhanced framing symbol sequence.

    -Force a scrambler reset. +Force a scrambler reset.

    - +

    @@ -7190,7 +7193,7 @@ Force a scrambler reset. The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.

    - +

    @@ -7207,10 +7210,10 @@ The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register val

    -Value:

    ((((Tdt[XDPTX_DISPID_TDT_TOP2] & XDPTX_DISPID_TDT_TOP2_HLOC_H_MASK) \
    -        >> XDPTX_DISPID_TDT_TOP2_HLOC_H_SHIFT) << 4) | \
    -        ((Tdt[XDPTX_DISPID_TDT_TOP1] & XDPTX_DISPID_TDT_TOP1_HLOC_L_MASK) >> \
    -        XDPTX_DISPID_TDT_TOP1_HLOC_L_SHIFT))
    +Value:Given a Tiled Display Topology (TDT) data block, retrieve the horizontal tile location in the tiled display. The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

    Parameters:
    @@ -7218,11 +7221,11 @@ The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register val
    Returns:
    The horizontal tile location in the tiled display represented by the specified TDT.
    -
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtHLoc(u8 *Tdt)
    +
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtHLoc(u8 *Tdt)

    - +

    @@ -7239,10 +7242,10 @@ The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register val

    -Value:

    (((((Tdt[XDPTX_DISPID_TDT_TOP2] & XDPTX_DISPID_TDT_TOP2_HTOT_H_MASK) \
    -        >> XDPTX_DISPID_TDT_TOP2_HTOT_H_SHIFT) << 4) | \
    -        ((Tdt[XDPTX_DISPID_TDT_TOP0] & XDPTX_DISPID_TDT_TOP0_HTOT_L_MASK) >> \
    -        XDPTX_DISPID_TDT_TOP0_HTOT_L_SHIFT)) + 1)
    +Value:Given a Tiled Display Topology (TDT) data block, retrieve the total number of horizontal tiles in the tiled display. The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

    Parameters:
    @@ -7250,11 +7253,11 @@ The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register val
    Returns:
    The total number of horizontal tiles in the tiled display.
    -
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtHTotal(u8 *Tdt)
    +
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtHTotal(u8 *Tdt)

    - +

    @@ -7278,11 +7281,11 @@ Given a Tiled Display Topology (TDT) data block, retrieve the total number of ti
    Returns:
    The total number of tiles in the tiled display.
    -
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtNumTiles(u8 *Tdt)
    +
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtNumTiles(u8 *Tdt)

    - +

    @@ -7299,8 +7302,8 @@ Given a Tiled Display Topology (TDT) data block, retrieve the total number of ti

    -Value:

    ((XDptx_GetDispIdTdtVLoc(Tdt) * XDptx_GetDispIdTdtHTotal(Tdt)) + \
    -        XDptx_GetDispIdTdtHLoc(Tdt))
    +Value:Given a Tiled Display Topology (TDT) data block, calculate the tiling order of the associated tile. The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID. The tiling order starts at 0 for x,y coordinate 0,0 and increments as the horizontal location increases. Once the last horizontal tile has been reached, the next tile in the order is 0,y+1.

    Parameters:
    @@ -7308,11 +7311,11 @@ Given a Tiled Display Topology (TDT) data block, retrieve the total number of ti
    Returns:
    The total number of horizontal tiles in the tiled display.
    -
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtTileOrder(u8 *Tdt)
    +
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtTileOrder(u8 *Tdt)

    - +

    @@ -7329,8 +7332,8 @@ Given a Tiled Display Topology (TDT) data block, retrieve the total number of ti

    -Value:

    (((Tdt[XDPTX_DISPID_TDT_TOP2] & XDPTX_DISPID_TDT_TOP2_VLOC_H_MASK) << \
    -        4) | (Tdt[XDPTX_DISPID_TDT_TOP1] & XDPTX_DISPID_TDT_TOP1_VLOC_L_MASK))
    +Value:Given a Tiled Display Topology (TDT) data block, retrieve the vertical tile location in the tiled display. The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

    Parameters:
    @@ -7338,11 +7341,11 @@ Given a Tiled Display Topology (TDT) data block, retrieve the total number of ti
    Returns:
    The vertical tile location in the tiled display represented by the specified TDT.
    -
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtVLoc(u8 *Tdt)
    +
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtVLoc(u8 *Tdt)

    - +

    @@ -7359,9 +7362,9 @@ Given a Tiled Display Topology (TDT) data block, retrieve the total number of ti

    -Value:

    (((((Tdt[XDPTX_DISPID_TDT_TOP2] & XDPTX_DISPID_TDT_TOP2_VTOT_H_MASK) \
    -        >> XDPTX_DISPID_TDT_TOP2_VTOT_H_SHIFT) << 4) | \
    -        (Tdt[XDPTX_DISPID_TDT_TOP0] & XDPTX_DISPID_TDT_TOP0_VTOT_L_MASK)) + 1)
    +Value:Given a Tiled Display Topology (TDT) data block, retrieve the total number of vertical tiles in the tiled display. The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

    Parameters:
    @@ -7369,11 +7372,11 @@ Given a Tiled Display Topology (TDT) data block, retrieve the total number of ti
    Returns:
    The total number of vertical tiles in the tiled display.
    -
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtVTotal(u8 *Tdt)
    +
    Note:
    C-style signature: u8 XDptx_GetDispIdTdtVTotal(u8 *Tdt)

    - +

    @@ -7385,10 +7388,10 @@ Given a Tiled Display Topology (TDT) data block, retrieve the total number of ti

    -Provides access to GT DRP channel status. +Provides access to GT DRP channel status.

    - +

    @@ -7400,10 +7403,10 @@ Provides access to GT DRP channel status.

    -Provides acces to the GT DRP ports. +Provides acces to the GT DRP ports.

    - +

    @@ -7415,10 +7418,10 @@ Provides acces to the GT DRP ports.

    -DRP address. +DRP address.

    - +

    @@ -7430,10 +7433,10 @@ DRP address.

    -DRP read/write command (Read=0, Write=1). +DRP read/write command (Read=0, Write=1).

    - +

    @@ -7445,10 +7448,10 @@ DRP read/write command (Read=0, Write=1).

    -DRP write data. +DRP write data.

    - +

    @@ -7460,10 +7463,10 @@ DRP write data.

    -Shift bits for DRP write data. +Shift bits for DRP write data.

    - +

    @@ -7475,10 +7478,10 @@ Shift bits for DRP write data.

    -Provides access to GT DRP read data. +Provides access to GT DRP read data.

    - +

    @@ -7490,10 +7493,10 @@ Provides access to GT DRP read data.

    -Duration of the HPD pulse in microseconds. +Duration of the HPD pulse in microseconds.

    - +

    @@ -7508,7 +7511,7 @@ Duration of the HPD pulse in microseconds.

    - +

    @@ -7520,10 +7523,10 @@ Duration of the HPD pulse in microseconds.

    -Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. +Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.

    - +

    @@ -7535,10 +7538,10 @@ Number of initial wait cycles at the start of a new line by the framing logic, a

    -Masks the specified interrupt sources. +Masks the specified interrupt sources.

    - +

    @@ -7550,10 +7553,10 @@ Masks the specified interrupt sources.

    -Mask extended packet transmit interrupt. +Mask extended packet transmit interrupt.

    - +

    @@ -7565,10 +7568,10 @@ Mask extended packet transmit interrupt.

    -Mask HPD event interrupt. +Mask HPD event interrupt.

    - +

    @@ -7580,10 +7583,10 @@ Mask HPD event interrupt.

    -Mask HPD IRQ interrupt. +Mask HPD IRQ interrupt.

    - +

    @@ -7595,10 +7598,10 @@ Mask HPD IRQ interrupt.

    -Mask HPD pulse detected interrupt. +Mask HPD pulse detected interrupt.

    - +

    @@ -7610,10 +7613,10 @@ Mask HPD pulse detected interrupt.

    -Mask reply received interrupt. +Mask reply received interrupt.

    - +

    @@ -7625,10 +7628,10 @@ Mask reply received interrupt.

    -Mask reply received interrupt. +Mask reply received interrupt.

    - +

    @@ -7640,10 +7643,10 @@ Mask reply received interrupt.

    -The raw signal values for interupt events. +The raw signal values for interupt events.

    - +

    @@ -7655,10 +7658,10 @@ The raw signal values for interupt events.

    -Raw state of the HPD pin on the DP connector. +Raw state of the HPD pin on the DP connector.

    - +

    @@ -7670,10 +7673,10 @@ Raw state of the HPD pin on the DP connector.

    -A reply is currently being received. +A reply is currently being received.

    - +

    @@ -7685,10 +7688,10 @@ A reply is currently being received.

    -A reply timeout has occurred. +A reply timeout has occurred.

    - +

    @@ -7700,10 +7703,10 @@ A reply timeout has occurred.

    -A request is currently being sent. +A request is currently being sent.

    - +

    @@ -7715,10 +7718,10 @@ A request is currently being sent.

    -Status for interrupt events. +Status for interrupt events.

    - +

    @@ -7730,10 +7733,10 @@ Status for interrupt events.

    -Extended packet has been transmitted and the core is ready to accept a new packet. +Extended packet has been transmitted and the core is ready to accept a new packet.

    - +

    @@ -7745,10 +7748,10 @@ Extended packet has been transmitted and the core is ready to accept a new packe

    -Detected the presence of the HPD signal. +Detected the presence of the HPD signal.

    - +

    @@ -7760,10 +7763,10 @@ Detected the presence of the HPD signal.

    -Detected an IRQ framed with the proper timing on the HPD signal. +Detected an IRQ framed with the proper timing on the HPD signal.

    - +

    @@ -7775,10 +7778,10 @@ Detected an IRQ framed with the proper timing on the HPD signal.

    -A pulse on the HPD line was detected. +A pulse on the HPD line was detected.

    - +

    @@ -7790,10 +7793,10 @@ A pulse on the HPD line was detected.

    -An AUX reply transaction has been detected. +An AUX reply transaction has been detected.

    - +

    @@ -7808,7 +7811,7 @@ An AUX reply transaction has been detected. A reply timeout has occurred.

    - +

    @@ -7834,11 +7837,11 @@ Check if an Extended Display Identification Data (EDID) extension block is of ty
    Returns:
    • 1 if the extension block is of type DisplayID.
    • Otherwise.
    -
    Note:
    C-style signature: u8 XDptx_IsEdidExtBlockDispId(u8 *Ext)
    +
    Note:
    C-style signature: u8 XDptx_IsEdidExtBlockDispId(u8 *Ext)

    - +

    @@ -7850,10 +7853,10 @@ Check if an Extended Display Identification Data (EDID) extension block is of ty

    -Set lane count setting. +Set lane count setting.

    - +

    @@ -7865,10 +7868,10 @@ Set lane count setting.

    -Lane count of 1. +Lane count of 1.

    - +

    @@ -7880,10 +7883,10 @@ Lane count of 1.

    -Lane count of 2. +Lane count of 2.

    - +

    @@ -7895,10 +7898,10 @@ Lane count of 2.

    -Lane count of 4. +Lane count of 4.

    - +

    @@ -7910,10 +7913,10 @@ Lane count of 4.

    -Set main link bandwidth setting. +Set main link bandwidth setting.

    - +

    @@ -7925,10 +7928,10 @@ Set main link bandwidth setting.

    -1.62 Gbps link rate. +1.62 Gbps link rate.

    - +

    @@ -7940,10 +7943,10 @@ Set main link bandwidth setting.

    -2.70 Gbps link rate. +2.70 Gbps link rate.

    - +

    @@ -7955,10 +7958,10 @@ Set main link bandwidth setting.

    -5.40 Gbps link rate. +5.40 Gbps link rate.

    - +

    @@ -7970,10 +7973,10 @@ Set main link bandwidth setting.

    -Transmit the link quality pattern. +Transmit the link quality pattern.

    - +

    @@ -7985,10 +7988,10 @@ Transmit the link quality pattern.

    -D10.2 unscrambled test pattern transmitted. +D10.2 unscrambled test pattern transmitted.

    - +

    @@ -8000,10 +8003,10 @@ D10.2 unscrambled test pattern transmitted.

    -Link quality test pattern not transmitted. +Link quality test pattern not transmitted.

    - +

    @@ -8015,10 +8018,10 @@ Link quality test pattern not transmitted.

    -Pseudo random bit sequence 7 transmitted. +Pseudo random bit sequence 7 transmitted.

    - +

    @@ -8030,10 +8033,10 @@ Pseudo random bit sequence 7 transmitted.

    -Symbol error rate measurement pattern transmitted. +Symbol error rate measurement pattern transmitted.

    - +

    @@ -8045,10 +8048,10 @@ Symbol error rate measurement pattern transmitted.

    -M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.

    - +

    @@ -8060,10 +8063,10 @@ M value for the video stream as computed by the source core in asynchronous cloc

    -Number of active pixels per line (the horizontal resolution). +Number of active pixels per line (the horizontal resolution).

    - +

    @@ -8075,10 +8078,10 @@ Number of active pixels per line (the horizontal resolution).

    -Number of clocks between the leading edge of the horizontal sync and the start of active data. +Number of clocks between the leading edge of the horizontal sync and the start of active data.

    - +

    @@ -8090,10 +8093,10 @@ Number of clocks between the leading edge of the horizontal sync and the start o

    -Width of the horizontal sync pulse. +Width of the horizontal sync pulse.

    - +

    @@ -8105,10 +8108,10 @@ Width of the horizontal sync pulse.

    -Total number of clocks in the horizontal framing period. +Total number of clocks in the horizontal framing period.

    - +

    @@ -8120,10 +8123,10 @@ Total number of clocks in the horizontal framing period.

    -Video is interlaced. +Video is interlaced.

    - +

    @@ -8135,10 +8138,10 @@ Video is interlaced.

    -Miscellaneous stream attributes. +Miscellaneous stream attributes.

    - +

    @@ -8150,10 +8153,10 @@ Miscellaneous stream attributes.

    -Miscellaneous stream attributes. +Miscellaneous stream attributes.

    - +

    @@ -8165,10 +8168,10 @@ Miscellaneous stream attributes.

    -Polarity for the video sync signals. +Polarity for the video sync signals.

    - +

    @@ -8180,10 +8183,10 @@ Polarity for the video sync signals.

    -Number of active lines (the vertical resolution). +Number of active lines (the vertical resolution).

    - +

    @@ -8195,10 +8198,10 @@ Number of active lines (the vertical resolution).

    -Number of lines between the leading edge of the vertical sync and the first line of active data. +Number of lines between the leading edge of the vertical sync and the first line of active data.

    - +

    @@ -8210,10 +8213,10 @@ Number of lines between the leading edge of the vertical sync and the first line

    -Width of the vertical sync pulse. +Width of the vertical sync pulse.

    - +

    @@ -8225,10 +8228,10 @@ Width of the vertical sync pulse.

    -Total number of lines in the video frame. +Total number of lines in the video frame.

    - +

    @@ -8240,10 +8243,10 @@ Total number of lines in the video frame.

    -10 bits per component. +10 bits per component.

    - +

    @@ -8255,10 +8258,10 @@ Total number of lines in the video frame.

    -12 bits per component. +12 bits per component.

    - +

    @@ -8270,10 +8273,10 @@ Total number of lines in the video frame.

    -16 bits per component. +16 bits per component.

    - +

    @@ -8285,10 +8288,10 @@ Total number of lines in the video frame.

    -6 bits per component. +6 bits per component.

    - +

    @@ -8300,10 +8303,10 @@ Total number of lines in the video frame.

    -8 bits per component. +8 bits per component.

    - +

    @@ -8315,10 +8318,10 @@ Total number of lines in the video frame.

    -Bit depth per color component (BDC). +Bit depth per color component (BDC).

    - +

    @@ -8330,10 +8333,10 @@ Bit depth per color component (BDC).

    -Shift bits for BDC. +Shift bits for BDC.

    - +

    @@ -8345,10 +8348,10 @@ Shift bits for BDC.

    -Component format. +Component format.

    - +

    @@ -8360,10 +8363,10 @@ Component format.

    -Stream's component format is RGB. +Stream's component format is RGB.

    - +

    @@ -8375,10 +8378,10 @@ Stream's component format is RGB.

    -Shift bits for component format. +Shift bits for component format.

    - +

    @@ -8390,10 +8393,10 @@ Shift bits for component format.

    -Stream's component format is YcbCr 4:2:2. +Stream's component format is YcbCr 4:2:2.

    - +

    @@ -8405,10 +8408,10 @@ Stream's component format is YcbCr 4:2:2.

    -Stream's component format is YcbCr 4:4:4. +Stream's component format is YcbCr 4:4:4.

    - +

    @@ -8420,10 +8423,10 @@ Stream's component format is YcbCr 4:4:4.

    -Dynamic range. +Dynamic range.

    - +

    @@ -8435,10 +8438,10 @@ Dynamic range.

    -Shift bits for dynamic range. +Shift bits for dynamic range.

    - +

    @@ -8450,10 +8453,10 @@ Shift bits for dynamic range.

    -Synchronous clock. +Synchronous clock.

    - +

    @@ -8465,10 +8468,10 @@ Synchronous clock.

    -YCbCr colorimetry. +YCbCr colorimetry.

    - +

    @@ -8480,10 +8483,10 @@ YCbCr colorimetry.

    -Shift bits for YCbCr colorimetry. +Shift bits for YCbCr colorimetry.

    - +

    @@ -8495,10 +8498,10 @@ Shift bits for YCbCr colorimetry.

    -Interlaced vertical total even. +Interlaced vertical total even.

    - +

    @@ -8510,10 +8513,10 @@ Interlaced vertical total even.

    -Stereo video attribute. +Stereo video attribute.

    - +

    @@ -8525,10 +8528,10 @@ Stereo video attribute.

    -Shift bits for stereo video attribute. +Shift bits for stereo video attribute.

    - +

    @@ -8540,10 +8543,10 @@ Shift bits for stereo video attribute.

    -Polarity of the horizontal sync pulse. +Polarity of the horizontal sync pulse.

    - +

    @@ -8555,10 +8558,10 @@ Polarity of the horizontal sync pulse.

    -Polarity of the vertical sync pulse. +Polarity of the vertical sync pulse.

    - +

    @@ -8570,10 +8573,10 @@ Polarity of the vertical sync pulse.

    -Shift bits for polarity of the vertical sync pulse. +Shift bits for polarity of the vertical sync pulse.

    - +

    @@ -8585,10 +8588,10 @@ Shift bits for polarity of the vertical sync pulse.

    -The minimum number of bytes per transfer unit. +The minimum number of bytes per transfer unit.

    - +

    @@ -8600,10 +8603,10 @@ The minimum number of bytes per transfer unit.

    -N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.

    - +

    @@ -8618,7 +8621,7 @@ N value for the video stream as computed by the source core in asynchronous cloc

    - +

    @@ -8630,10 +8633,10 @@ N value for the video stream as computed by the source core in asynchronous cloc

    -Pre-emphasis level 0. +Pre-emphasis level 0.

    - +

    @@ -8645,10 +8648,10 @@ Pre-emphasis level 0.

    -Pre-emphasis level 1. +Pre-emphasis level 1.

    - +

    @@ -8660,10 +8663,10 @@ Pre-emphasis level 1.

    -Pre-emphasis level 2. +Pre-emphasis level 2.

    - +

    @@ -8675,10 +8678,10 @@ Pre-emphasis level 2.

    -Pre-emphasis level 3. +Pre-emphasis level 3.

    - +

    @@ -8690,10 +8693,10 @@ Pre-emphasis level 3.

    -Instructs the PHY PLL to generate the proper clock frequency for the required link rate. +Instructs the PHY PLL to generate the proper clock frequency for the required link rate.

    - +

    @@ -8705,10 +8708,10 @@ Instructs the PHY PLL to generate the proper clock frequency for the required li

    -1.62 Gbps link. +1.62 Gbps link.

    - +

    @@ -8720,10 +8723,10 @@ Instructs the PHY PLL to generate the proper clock frequency for the required li

    -2.70 Gbps link. +2.70 Gbps link.

    - +

    @@ -8735,10 +8738,10 @@ Instructs the PHY PLL to generate the proper clock frequency for the required li

    -5.40 Gbps link. +5.40 Gbps link.

    - +

    @@ -8750,145 +8753,145 @@ Instructs the PHY PLL to generate the proper clock frequency for the required li

    -Transceiver PHY reset and configuration. +Transceiver PHY reset and configuration.

    - +

    - +
    #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0010003 #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0000003

    -Rest GT and PHY. +Rest GT and PHY.

    - +

    - +
    #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0010002 #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0000002

    -Hold GTTXRESET in reset. +Hold GTTXRESET in reset.

    - +

    - +
    #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0010000 #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0000000

    -Release reset. +Release reset.

    - +

    - +
    #define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0010001 #define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0000001

    -Hold the PHY in reset. +Hold the PHY in reset.

    - +

    - +
    #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x001E000 #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x000E000

    -Set TX_PHY_LOOPBACK. +Set TX_PHY_LOOPBACK.

    - +

    - +
    #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0010200 #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0000200

    -HOLD TX_PHY_PCS reset. +HOLD TX_PHY_PCS reset.

    - +

    - +
    #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0010100 #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0000100

    -Hold TX_PHY_PMA reset. +Hold TX_PHY_PMA reset.

    - +

    - +
    #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0010400 #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0000400

    -Set TX_PHY_POLARITY. +Set TX_PHY_POLARITY.

    - +

    - +
    #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0011000 #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0001000

    -Set TX_PHY_PRBSFORCEERR. +Set TX_PHY_PRBSFORCEERR.

    - +

    @@ -8900,10 +8903,10 @@ Set TX_PHY_PRBSFORCEERR.

    -Controls the post-cursor level. +Controls the post-cursor level.

    - +

    @@ -8915,10 +8918,10 @@ Controls the post-cursor level.

    -Controls the post-cursor level. +Controls the post-cursor level.

    - +

    @@ -8930,10 +8933,10 @@ Controls the post-cursor level.

    -Controls the post-cursor level. +Controls the post-cursor level.

    - +

    @@ -8945,10 +8948,10 @@ Controls the post-cursor level.

    -Controls the post-cursor level. +Controls the post-cursor level.

    - +

    @@ -8960,10 +8963,10 @@ Controls the post-cursor level.

    -Controls the pre-cursor level. +Controls the pre-cursor level.

    - +

    @@ -8975,10 +8978,10 @@ Controls the pre-cursor level.

    -Controls the pre-cursor level. +Controls the pre-cursor level.

    - +

    @@ -8990,10 +8993,10 @@ Controls the pre-cursor level.

    -Controls the pre-cursor level. +Controls the pre-cursor level.

    - +

    @@ -9005,10 +9008,10 @@ Controls the pre-cursor level.

    -Controls the pre-cursor level. +Controls the pre-cursor level.

    - +

    @@ -9020,10 +9023,10 @@ Controls the pre-cursor level.

    -Current PHY status. +Current PHY status.

    - +

    @@ -9035,25 +9038,40 @@ Current PHY status.

    -All lanes are ready. +All lanes are ready.

    - +

    - +
    #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000020 #define XDPTX_PHY_STATUS_LANES_0_1_READY_MASK   0x00000013

    -FPGA fabric clock PLL locked. +Lanes 0 and 1 are ready.

    - + +

    +
    + + + + +
    #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000040
    +
    +
    + +

    +FPGA fabric clock PLL locked. +

    +

    +

    @@ -9065,10 +9083,10 @@ FPGA fabric clock PLL locked.

    -PLL locked for lanes 0 and 1. +PLL locked for lanes 0 and 1.

    - +

    @@ -9080,10 +9098,10 @@ PLL locked for lanes 0 and 1.

    -PLL locked for lanes 2 and 3. +PLL locked for lanes 2 and 3.

    - +

    @@ -9095,10 +9113,10 @@ PLL locked for lanes 2 and 3.

    -Reset done for lanes 0 and 1. +Reset done for lanes 0 and 1.

    - +

    @@ -9110,10 +9128,10 @@ Reset done for lanes 0 and 1.

    -Reset done for lanes 2 and 3. +Reset done for lanes 2 and 3.

    - +

    @@ -9125,10 +9143,10 @@ Reset done for lanes 2 and 3.

    -TX buffer status lane 0. +TX buffer status lane 0.

    - +

    @@ -9140,10 +9158,10 @@ TX buffer status lane 0.

    -Shift bits for TX buffer status lane 0. +Shift bits for TX buffer status lane 0.

    - +

    @@ -9155,10 +9173,10 @@ Shift bits for TX buffer status lane 0.

    -TX buffer status lane 1. +TX buffer status lane 1.

    - +

    @@ -9170,10 +9188,10 @@ TX buffer status lane 1.

    -Shift bits for TX buffer status lane 1. +Shift bits for TX buffer status lane 1.

    - +

    @@ -9185,10 +9203,10 @@ Shift bits for TX buffer status lane 1.

    -TX buffer status lane 2. +TX buffer status lane 2.

    - +

    @@ -9200,10 +9218,10 @@ TX buffer status lane 2.

    -Shift bits for TX buffer status lane 2. +Shift bits for TX buffer status lane 2.

    - +

    @@ -9215,10 +9233,10 @@ Shift bits for TX buffer status lane 2.

    -TX buffer status lane 3. +TX buffer status lane 3.

    - +

    @@ -9230,10 +9248,10 @@ TX buffer status lane 3.

    -Shift bits for TX buffer status lane 3. +Shift bits for TX buffer status lane 3.

    - +

    @@ -9245,10 +9263,10 @@ Shift bits for TX buffer status lane 3.

    -TX error on lane 0. +TX error on lane 0.

    - +

    @@ -9260,10 +9278,10 @@ TX error on lane 0.

    -Shift bits for TX error on lane 0. +Shift bits for TX error on lane 0.

    - +

    @@ -9275,10 +9293,10 @@ Shift bits for TX error on lane 0.

    -TX error on lane 1. +TX error on lane 1.

    - +

    @@ -9290,10 +9308,10 @@ TX error on lane 1.

    -Shift bits for TX error on lane 1. +Shift bits for TX error on lane 1.

    - +

    @@ -9305,10 +9323,10 @@ Shift bits for TX error on lane 1.

    -TX error on lane 2. +TX error on lane 2.

    - +

    @@ -9320,10 +9338,10 @@ TX error on lane 2.

    -Shift bits for TX error on lane 2. +Shift bits for TX error on lane 2.

    - +

    @@ -9335,10 +9353,10 @@ Shift bits for TX error on lane 2.

    -TX error on lane 3. +TX error on lane 3.

    - +

    @@ -9350,10 +9368,10 @@ TX error on lane 3.

    -Shift bits for TX error on lane 3. +Shift bits for TX error on lane 3.

    - +

    @@ -9365,10 +9383,10 @@ Shift bits for TX error on lane 3.

    -Enable pseudo random bit sequence 7 pattern transmission for link quality assessment. +Enable pseudo random bit sequence 7 pattern transmission for link quality assessment.

    - +

    @@ -9380,10 +9398,10 @@ Enable pseudo random bit sequence 7 pattern transmission for link quality assess

    -Controls the differential voltage swing. +Controls the differential voltage swing.

    - +

    @@ -9395,10 +9413,10 @@ Controls the differential voltage swing.

    -Controls the differential voltage swing. +Controls the differential voltage swing.

    - +

    @@ -9410,10 +9428,10 @@ Controls the differential voltage swing.

    -Controls the differential voltage swing. +Controls the differential voltage swing.

    - +

    @@ -9425,10 +9443,10 @@ Controls the differential voltage swing.

    -Controls the differential voltage swing. +Controls the differential voltage swing.

    - +

    @@ -9456,11 +9474,11 @@ This is a low-level function that reads from the specified register.

    Returns:
    The 32-bit value of the specified register.
    -
    Note:
    C-style signature: u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset)
    +
    Note:
    C-style signature: u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset)

    - +

    @@ -9472,10 +9490,10 @@ This is a low-level function that reads from the specified register.

    -Total number of data bytes actually received during a transaction. +Total number of data bytes actually received during a transaction.

    - +

    @@ -9487,10 +9505,10 @@ Total number of data bytes actually received during a transaction.

    -Reply status of most recent AUX transaction. +Reply status of most recent AUX transaction.

    - +

    @@ -9502,10 +9520,10 @@ Reply status of most recent AUX transaction.

    -Detected an error in the AUX reply of the most recent transaction. +Detected an error in the AUX reply of the most recent transaction.

    - +

    @@ -9517,10 +9535,10 @@ Detected an error in the AUX reply of the most recent transaction.

    -AUX reply is currently being received. +AUX reply is currently being received.

    - +

    @@ -9532,10 +9550,10 @@ AUX reply is currently being received.

    -AUX transaction is complete and a valid reply transaction received. +AUX transaction is complete and a valid reply transaction received.

    - +

    @@ -9547,10 +9565,10 @@ AUX transaction is complete and a valid reply transaction received.

    -Internal AUX reply state machine status bits. +Internal AUX reply state machine status bits.

    - +

    @@ -9562,10 +9580,10 @@ Internal AUX reply state machine status bits.

    -Shift bits for the internal AUX reply state machine status. +Shift bits for the internal AUX reply state machine status.

    - +

    @@ -9577,10 +9595,10 @@ Shift bits for the internal AUX reply state machine status.

    -AUX request is currently being transmitted. +AUX request is currently being transmitted.

    - +

    @@ -9595,7 +9613,7 @@ AUX request is currently being transmitted.

    - +

    @@ -9610,7 +9628,7 @@ AUX request is currently being transmitted.

    - +

    @@ -9625,7 +9643,7 @@ AUX request is currently being transmitted.

    - +

    @@ -9640,7 +9658,7 @@ AUX request is currently being transmitted.

    - +

    @@ -9655,7 +9673,7 @@ AUX request is currently being transmitted.

    - +

    @@ -9670,7 +9688,7 @@ AUX request is currently being transmitted.

    - +

    @@ -9685,7 +9703,7 @@ AUX request is currently being transmitted.

    - +

    @@ -9700,7 +9718,7 @@ AUX request is currently being transmitted.

    - +

    @@ -9715,7 +9733,7 @@ AUX request is currently being transmitted. Disable scrambler and transmit all symbols.

    - +

    @@ -9730,7 +9748,7 @@ Disable scrambler and transmit all symbols.

    - +

    @@ -9742,10 +9760,10 @@ Disable scrambler and transmit all symbols.

    -Software reset. +Software reset.

    - +

    @@ -9757,70 +9775,70 @@ Software reset.

    -Reset AUX logic. +Reset AUX logic.

    - +

    - +
    #define XDPTX_SOFT_RESET_VIDEO_STREAM0_MASK   0x00000001 #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001

    -Reset video logic. +Reset video logic.

    - +

    - +
    #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000002 #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002

    -Reset video logic. +Reset video logic.

    - +

    - +
    #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000004 #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004

    -Reset video logic. +Reset video logic.

    - +

    - +
    #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000008 #define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008

    -Reset video logic. +Reset video logic.

    - +

    @@ -9832,117 +9850,70 @@ Reset video logic.

    -Reset video logic for all streams. +Reset video logic for all streams.

    - +

    - +
    #define XDPTX_STREAM0   0x01D0 #define XDPTX_STREAM1   0x01D0

    -Average stream symbol timeslots per MTP config. +Average stream symbol timeslots per MTP config.

    - +

    - +
    #define XDPTX_STREAM0_MSA_START   0x0180 #define XDPTX_STREAM1_MSA_START   0x0180

    -Start of the MSA registers for stream 0. +Start of the MSA registers for stream 1.

    - +

    - +
    #define XDPTX_STREAM1   0x01D4 #define XDPTX_STREAM2   0x01D4

    -Average stream symbol timeslots per MTP config. +Average stream symbol timeslots per MTP config.

    - +

    - +
    #define XDPTX_STREAM1_MSA_START   0x0500 #define XDPTX_STREAM2_MSA_START   0x0500

    -Start of the MSA registers for stream 1. +Start of the MSA registers for stream 2.

    - -

    -
    - - - - -
    #define XDPTX_STREAM1_MSA_START_OFFSET
    -
    -
    - -

    -Value:

    The MSA registers for stream 1 are at an offset from the corresponding registers of stream 0. -
    -

    - -

    -
    - - - - -
    #define XDPTX_STREAM2   0x01D8
    -
    -
    - -

    -Average stream symbol timeslots per MTP config. -

    -

    - -

    -
    - - - - -
    #define XDPTX_STREAM2_MSA_START   0x0550
    -
    -
    - -

    -Start of the MSA registers for stream 2. -

    -

    - +

    @@ -9954,42 +9925,42 @@ Start of the MSA registers for stream 2.

    -Value:

    The MSA registers for stream 2 are at an offset from the corresponding registers of stream 0. +Value:The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1.

    - +

    - +
    #define XDPTX_STREAM3   0x01DC #define XDPTX_STREAM3   0x01D8

    -Average stream symbol timeslots per MTP config. +Average stream symbol timeslots per MTP config.

    - +

    - +
    #define XDPTX_STREAM3_MSA_START   0x05A0 #define XDPTX_STREAM3_MSA_START   0x0550

    -Start of the MSA registers for stream 3. +Start of the MSA registers for stream 3.

    - +

    @@ -10001,27 +9972,59 @@ Start of the MSA registers for stream 3.

    -Value:

    The MSA registers for stream 3 are at an offset from the corresponding registers of stream 0. +Value:The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1.

    - +

    - +
    #define XDPTX_STREAM_ID0   0 #define XDPTX_STREAM4   0x01DC

    - +Average stream symbol timeslots per MTP config.

    - + +

    +
    + + + + +
    #define XDPTX_STREAM4_MSA_START   0x05A0
    +
    +
    + +

    +Start of the MSA registers for stream 4. +

    +

    + +

    +
    + + + + +
    #define XDPTX_STREAM4_MSA_START_OFFSET
    +
    +
    + +

    +Value:

    The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. +
    +

    +

    @@ -10036,7 +10039,7 @@ Start of the MSA registers for stream 3.

    - +

    @@ -10051,7 +10054,7 @@ Start of the MSA registers for stream 3.

    - +

    @@ -10066,7 +10069,22 @@ Start of the MSA registers for stream 3.

    - + +

    +
    +
    + + + +
    #define XDPTX_STREAM_ID4   4
    +
    +
    + +

    + +

    +

    +

    @@ -10078,10 +10096,10 @@ Start of the MSA registers for stream 3.

    -Set the link training pattern. +Set the link training pattern.

    - +

    @@ -10093,10 +10111,10 @@ Set the link training pattern.

    -Training off. +Training off.

    - +

    @@ -10108,10 +10126,10 @@ Training off.

    -Training pattern 1 used for clock recovery. +Training pattern 1 used for clock recovery.

    - +

    @@ -10123,10 +10141,10 @@ Training pattern 1 used for clock recovery.

    -Training pattern 2 used for channel equalization. +Training pattern 2 used for channel equalization.

    - +

    @@ -10138,10 +10156,10 @@ Training pattern 2 used for channel equalization.

    -Training pattern 3 used for channel equalization for cores with DP v1.2. +Training pattern 3 used for channel equalization for cores with DP v1.2.

    - +

    @@ -10153,10 +10171,10 @@ Training pattern 3 used for channel equalization for cores with DP v1.2.

    -Size of a transfer unit in the framing logic. +Size of a transfer unit in the framing logic.

    - +

    @@ -10168,10 +10186,10 @@ Size of a transfer unit in the framing logic.

    -Used to input active channel count. +Used to input active channel count.

    - +

    @@ -10183,10 +10201,10 @@ Used to input active channel count.

    -Enables audio stream packets in main link and buffer control. +Enables audio stream packets in main link and buffer control.

    - +

    @@ -10198,10 +10216,10 @@ Enables audio stream packets in main link and buffer control.

    -Word formatted as per extension packet. +Word formatted as per extension packet.

    - +

    @@ -10213,10 +10231,10 @@ Word formatted as per extension packet.

    -Word formatted as per CEA 861-C info frame. +Word formatted as per CEA 861-C info frame.

    - +

    @@ -10228,10 +10246,10 @@ Word formatted as per CEA 861-C info frame.

    -M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. +M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous.

    - +

    @@ -10243,10 +10261,10 @@ M value of audio stream as computed by the DisplayPort TX core when audio and li

    -N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. +N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous.

    - +

    @@ -10258,10 +10276,10 @@ N value of audio stream as computed by the DisplayPort TX core when audio and li

    -Enable MST. +Enable MST.

    - +

    @@ -10273,10 +10291,10 @@ Enable MST.

    -Enable MST. +Enable MST.

    - +

    @@ -10288,10 +10306,10 @@ Enable MST.

    -The VC payload has been updated in the sink. +The VC payload has been updated in the sink.

    - +

    @@ -10303,10 +10321,10 @@ The VC payload has been updated in the sink.

    -Controls PHY power down. +Controls PHY power down.

    - +

    @@ -10318,10 +10336,10 @@ Controls PHY power down.

    -Indicates an overflow in user FIFO. +Indicates an overflow in user FIFO.

    - +

    @@ -10333,10 +10351,10 @@ Indicates an overflow in user FIFO.

    -Used to translate the number of pixels per line to the native internal 16-bit datapath. +Used to translate the number of pixels per line to the native internal 16-bit datapath.

    - +

    @@ -10348,10 +10366,10 @@ Used to translate the number of pixels per line to the native internal 16-bit da

    -Selects the width of the user data input port. +Selects the width of the user data input port.

    - +

    @@ -10363,10 +10381,10 @@ Selects the width of the user data input port.

    -Virtual channel payload table (0xFF bytes). +Virtual channel payload table (0xFF bytes).

    - +

    @@ -10378,10 +10396,10 @@ Virtual channel payload table (0xFF bytes).

    -Core version. +Core version.

    - +

    @@ -10393,10 +10411,10 @@ Core version.

    -Core patch details. +Core patch details.

    - +

    @@ -10408,10 +10426,10 @@ Core patch details.

    -Shift bits for core patch details. +Shift bits for core patch details.

    - +

    @@ -10423,10 +10441,10 @@ Shift bits for core patch details.

    -Core major version. +Core major version.

    - +

    @@ -10438,10 +10456,10 @@ Core major version.

    -Shift bits for core major version. +Shift bits for core major version.

    - +

    @@ -10453,10 +10471,10 @@ Shift bits for core major version.

    -Core minor version. +Core minor version.

    - +

    @@ -10468,10 +10486,10 @@ Core minor version.

    -Shift bits for core minor version. +Shift bits for core minor version.

    - +

    @@ -10483,10 +10501,10 @@ Shift bits for core minor version.

    -Core version revision. +Core version revision.

    - +

    @@ -10498,10 +10516,10 @@ Core version revision.

    -Shift bits for core version revision. +Shift bits for core version revision.

    - +

    @@ -10513,10 +10531,10 @@ Shift bits for core version revision.

    -Internal revision. +Internal revision.

    - +

    @@ -10528,10 +10546,10 @@ Internal revision.

    -Voltage swing level 0. +Voltage swing level 0.

    - +

    @@ -10543,10 +10561,10 @@ Voltage swing level 0.

    -Voltage swing level 1. +Voltage swing level 1.

    - +

    @@ -10558,10 +10576,10 @@ Voltage swing level 1.

    -Voltage swing level 2. +Voltage swing level 2.

    - +

    @@ -10573,10 +10591,10 @@ Voltage swing level 2.

    -Voltage swing level 3. +Voltage swing level 3.

    - +

    @@ -10588,10 +10606,10 @@ Voltage swing level 3.

    -Voltage swing compensation offset used when there's no redriver in display path. +Voltage swing compensation offset used when there's no redriver in display path.

    - +

    @@ -10623,7 +10641,7 @@ This is a low-level function that writes to the specified register.

    Returns:
    None.
    -
    Note:
    C-style signature: void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
    +
    Note:
    C-style signature: void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__intr_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__intr_8c.html index cc1a7aed..32ce977a 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__intr_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__intr_8c.html @@ -29,21 +29,23 @@ This file contains functions related to

     Ver   Who  Date     Changes
      ----- ---- -------- -----------------------------------------------
      1.0   als  05/17/14 Initial release.
    - 
    + 3.0 als 12/16/14 Increased debounce duration for HPD to 0.500ms. + Added masking of interrupts during servicing. +

    #include "xdptx.h"
    - + - + - +

    Functions

    void XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
    void XDptx_HpdInterruptHandler (XDptx *InstancePtr)
    void XDptx_HpdInterruptHandler (XDptx *InstancePtr)


    Function Documentation

    - +
    @@ -72,7 +74,7 @@ When an interrupt happens, it first detects what kind of interrupt happened, the

    - +

    @@ -85,7 +87,7 @@ When an interrupt happens, it first detects what kind of interrupt happened, the - + @@ -117,7 +119,7 @@ This function installs a callback function for when a hot-plug-detect event inte

    - +

    XDptx_HpdEventHandler XDptx_HpdEventHandler  CallbackFunc,
    @@ -130,7 +132,7 @@ This function installs a callback function for when a hot-plug-detect event inte - + diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__mst_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__mst_8c.html index 415c217f..0a05508b 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__mst_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__mst_8c.html @@ -28,7 +28,15 @@ ----- ---- -------- ----------------------------------------------- 1.0 als 08/03/14 Initial release. 2.0 als 09/21/14 Improvements to topology discovery and sideband messages. - + 3.0 als 12/16/14 Updated to use common video library. + Stream naming now starts at 1 to follow IP. + Added topology reordering functions: + XDptx_TopologySwapSinks, + XDptx_TopologySortSinksByTiling + Added wrapper functions for remote DPCD/I2C read/writes: + XDptx_RemoteDpcdRead, XDptx_RemoteDpcdWrite, + XDptx_RemoteIicRead, XDptx_RemoteIicWrite +

    #include "string.h"
    #include "xdptx.h"
    @@ -45,79 +53,79 @@

    - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +
    XDptx_HpdPulseHandler XDptx_HpdPulseHandler  CallbackFunc,
    struct  XDptx_SidebandReply

    Defines

    #define XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT   5000
    #define XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT   5000
    #define XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT   30
    #define XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT   30

    Functions

    void XDptx_MstCfgModeEnable (XDptx *InstancePtr)
    void XDptx_MstCfgModeEnable (XDptx *InstancePtr)
    void XDptx_MstCfgModeDisable (XDptx *InstancePtr)
    void XDptx_MstCfgModeDisable (XDptx *InstancePtr)
    u32 XDptx_MstCapable (XDptx *InstancePtr)
    u32 XDptx_MstCapable (XDptx *InstancePtr)
    u32 XDptx_MstEnable (XDptx *InstancePtr)
    u32 XDptx_MstEnable (XDptx *InstancePtr)
    u32 XDptx_MstDisable (XDptx *InstancePtr)
    u32 XDptx_MstDisable (XDptx *InstancePtr)
    u8 XDptx_MstStreamIsEnabled (XDptx *InstancePtr, u8 Stream)
    u8 XDptx_MstStreamIsEnabled (XDptx *InstancePtr, u8 Stream)
    void XDptx_MstCfgStreamEnable (XDptx *InstancePtr, u8 Stream)
    void XDptx_MstCfgStreamEnable (XDptx *InstancePtr, u8 Stream)
    void XDptx_MstCfgStreamDisable (XDptx *InstancePtr, u8 Stream)
    void XDptx_MstCfgStreamDisable (XDptx *InstancePtr, u8 Stream)
    void XDptx_SetStreamSelectFromSinkList (XDptx *InstancePtr, u8 Stream, u8 SinkNum)
    void XDptx_SetStreamSelectFromSinkList (XDptx *InstancePtr, u8 Stream, u8 SinkNum)
    void XDptx_SetStreamSinkRad (XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress)
    void XDptx_SetStreamSinkRad (XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_DiscoverTopology (XDptx *InstancePtr)
    u32 XDptx_DiscoverTopology (XDptx *InstancePtr)
    u32 XDptx_FindAccessibleDpDevices (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)
    u32 XDptx_FindAccessibleDpDevices (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)
    void XDptx_TopologySwapSinks (XDptx *InstancePtr, u8 Index0, u8 Index1)
    void XDptx_TopologySwapSinks (XDptx *InstancePtr, u8 Index0, u8 Index1)
    void XDptx_TopologySortSinksByTiling (XDptx *InstancePtr)
    void XDptx_TopologySortSinksByTiling (XDptx *InstancePtr)
    u32 XDptx_RemoteDpcdRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
    u32 XDptx_RemoteDpcdRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
    u32 XDptx_RemoteDpcdWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
    u32 XDptx_RemoteDpcdWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
    u32 XDptx_RemoteIicRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData)
    u32 XDptx_RemoteIicRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData)
    u32 XDptx_RemoteIicWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData)
    u32 XDptx_RemoteIicWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData)
    u32 XDptx_AllocatePayloadStreams (XDptx *InstancePtr)
    u32 XDptx_AllocatePayloadStreams (XDptx *InstancePtr)
    u32 XDptx_AllocatePayloadVcIdTable (XDptx *InstancePtr, u8 VcId, u8 Ts)
    u32 XDptx_AllocatePayloadVcIdTable (XDptx *InstancePtr, u8 VcId, u8 Ts)
    u32 XDptx_ClearPayloadVcIdTable (XDptx *InstancePtr)
    u32 XDptx_ClearPayloadVcIdTable (XDptx *InstancePtr)
    u32 XDptx_SendSbMsgRemoteDpcdWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
    u32 XDptx_SendSbMsgRemoteDpcdWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
    u32 XDptx_SendSbMsgRemoteDpcdRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
    u32 XDptx_SendSbMsgRemoteDpcdRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
    u32 XDptx_SendSbMsgRemoteIicWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData)
    u32 XDptx_SendSbMsgRemoteIicWrite (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData)
    u32 XDptx_SendSbMsgRemoteIicRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData)
    u32 XDptx_SendSbMsgRemoteIicRead (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData)
    u32 XDptx_SendSbMsgLinkAddress (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo)
    u32 XDptx_SendSbMsgLinkAddress (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo)
    u32 XDptx_SendSbMsgEnumPathResources (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn)
    u32 XDptx_SendSbMsgEnumPathResources (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn)
    u32 XDptx_SendSbMsgAllocatePayload (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn)
    u32 XDptx_SendSbMsgAllocatePayload (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn)
    u32 XDptx_SendSbMsgClearPayloadIdTable (XDptx *InstancePtr)
    u32 XDptx_SendSbMsgClearPayloadIdTable (XDptx *InstancePtr)
    void XDptx_WriteGuid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 Guid[4])
    void XDptx_WriteGuid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 Guid[4])
    void XDptx_GetGuid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 *Guid)
    void XDptx_GetGuid (XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 *Guid)

    Variables

    u32 GuidTable [16][4]
    u32 GuidTable [16][4]

    Define Documentation

    - +
    @@ -132,7 +140,7 @@

    - +

    @@ -148,7 +156,7 @@


    Function Documentation

    - +
    @@ -183,7 +191,7 @@ This function will allocate bandwidth for all enabled stream.

    - +

    @@ -235,7 +243,7 @@ This function will allocate a bandwidth for a virtual channel in the payload ID

    - +

    @@ -270,7 +278,7 @@ This function will clear the virtual channel payload ID table in both the Displa

    - +

    @@ -300,7 +308,7 @@ This function will explore the DisplayPort topology of downstream devices connec

    - +

    @@ -347,7 +355,7 @@ This function will explore the DisplayPort topology of downstream devices starti

    - +

    @@ -399,7 +407,7 @@ This function will obtain the global unique identifier (GUID) for the target Dis

    - +

    @@ -434,7 +442,7 @@ This function will check if the immediate downstream RX device is capable of mul

    - +

    @@ -462,7 +470,7 @@ This function will disable multi-stream transport (MST) mode for the driver.

    - +

    @@ -490,7 +498,7 @@ This function will enable multi-stream transport (MST) mode for the driver.

    - +

    @@ -528,7 +536,7 @@ This function will configure the InstancePtr->MstStreamConfig structure to di

    - +

    @@ -566,7 +574,7 @@ This function will configure the InstancePtr->MstStreamConfig structure to en

    - +

    @@ -601,7 +609,7 @@ This function will disable multi-stream transport (MST) mode in both the Display

    - +

    @@ -636,7 +644,7 @@ This function will enable multi-stream transport (MST) mode in both the DisplayP

    - +

    @@ -676,7 +684,7 @@ This function will check whether

    - +

    @@ -744,7 +752,7 @@ This function performs a remote DisplayPort Configuration Data (DPCD) read by se

    - +

    @@ -812,7 +820,7 @@ This function performs a remote DisplayPort Configuration Data (DPCD) write by s

    - +

    @@ -889,7 +897,7 @@ This function performs a remote I2C read by sending a sideband message. In case

    - +

    @@ -957,7 +965,7 @@ This function performs a remote I2C write by sending a sideband message. In case

    - +

    @@ -1023,7 +1031,7 @@ This function will send an ALLOCATE_PAYLOAD sideband message which will allocate

    - +

    @@ -1058,7 +1066,7 @@ This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will de-

    - +

    @@ -1126,7 +1134,7 @@ FullPbn will be modified with the total PBN of the path from the reply.

    - +

    @@ -1185,7 +1193,7 @@ This function will send a LINK_ADDRESS sideband message to a target DisplayPort

    - +

    @@ -1258,7 +1266,7 @@ This function will send a REMOTE_DPCD_READ sideband message which will read from

    - +

    @@ -1331,7 +1339,7 @@ This function will send a REMOTE_DPCD_WRITE sideband message which will write so

    - +

    @@ -1411,7 +1419,7 @@ This function will send a REMOTE_I2C_READ sideband message which will read from

    - +

    @@ -1464,7 +1472,7 @@ This function will send a REMOTE_I2C_READ sideband message which will read from

    - +

    @@ -1510,7 +1518,7 @@ The topology will need to be determined prior to calling this function using the

    - +

    @@ -1562,7 +1570,7 @@ This function will map a stream to a downstream DisplayPort TX device determined

    - +

    @@ -1590,7 +1598,7 @@ Order the sink list with all sinks of the same tiled display being sorted by 'ti

    - +

    @@ -1635,7 +1643,7 @@ Swap the ordering of the sinks in the topology's sink list. All sink information

    - +

    @@ -1688,12 +1696,12 @@ This function will write a global unique identifier (GUID) to the target Display


    Variable Documentation

    - +
    - +
    u32 GuidTable[16][4] u32 GuidTable[16][4]
    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__selftest_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__selftest_8c.html index 5167ac3e..51d0f795 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__selftest_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__selftest_8c.html @@ -29,23 +29,24 @@ This file contains a diagnostic self-test function for the xdptx.h"
    #include "xstatus.h"
    - + - + - +

    Functions

    u32 XDptx_SelfTest (XDptx *InstancePtr)
    u32 XDptx_SelfTest (XDptx *InstancePtr)

    Variables

    u32 ResetValues [53][2]
    u32 ResetValues [53][2]
    u32 ResetValuesMsa [20][2]
    u32 ResetValuesMsa [20][2]

    Function Documentation

    - +
    @@ -76,27 +77,27 @@ This function runs a self-test on the XD


    Variable Documentation

    -
    +
    - +
    u32 ResetValues[53][2] u32 ResetValues[53][2]

    -This table contains the default values for the DisplayPort TX core's general usage registers. +This table contains the default values for the DisplayPort TX core's general usage registers.

    - +

    - +
    u32 ResetValuesMsa[20][2] u32 ResetValuesMsa[20][2]
    @@ -105,28 +106,28 @@ This table contains the default values for the DisplayPort TX core's general usa

    Initial value:

    This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers. +
    This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers.

    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__sinit_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__sinit_8c.html index 7f8952bb..4f24fdf2 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__sinit_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__sinit_8c.html @@ -36,14 +36,14 @@ This file contains static initialization methods for the

    Functions

    -XDptx_ConfigXDptx_LookupConfig (u16 DeviceId) +XDptx_ConfigXDptx_LookupConfig (u16 DeviceId)

    Variables

    -XDptx_Config XDptx_ConfigTable [XPAR_XDPTX_NUM_INSTANCES] +XDptx_Config XDptx_ConfigTable [XPAR_XDPTX_NUM_INSTANCES]

    Function Documentation

    - +
    @@ -72,12 +72,12 @@ This function looks for the device configuration based on the unique device ID.


    Variable Documentation

    - +
    - +
    XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES] XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES]
    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html index 9002b34d..5a20c8c7 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html @@ -30,7 +30,9 @@ This file contains the stream policy maker functions for the + 3.0 als 12/16/14 Updated to use common video library. + Stream naming now starts at 1 to follow IP. +

    #include "xdptx.h"
    #include "xdptx_hw.h"
    @@ -38,27 +40,27 @@ This file contains the stream policy maker functions for the

    Functions

    -void XDptx_CfgMsaRecalculate (XDptx *InstancePtr, u8 Stream) +void XDptx_CfgMsaRecalculate (XDptx *InstancePtr, u8 Stream) -void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XDptx_VideoMode VideoMode) +void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XVid_VideoMode VideoMode) -void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr, u8 Stream, u8 *Edid) +void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr, u8 Stream, u8 *Edid) -void XDptx_CfgMsaUseCustom (XDptx *InstancePtr, u8 Stream, XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate) +void XDptx_CfgMsaUseCustom (XDptx *InstancePtr, u8 Stream, XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate) -void XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 Stream, u8 BitsPerColor) +void XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 Stream, u8 BitsPerColor) -void XDptx_CfgMsaEnSynchClkMode (XDptx *InstancePtr, u8 Stream, u8 Enable) +void XDptx_CfgMsaEnSynchClkMode (XDptx *InstancePtr, u8 Stream, u8 Enable) -void XDptx_SetVideoMode (XDptx *InstancePtr, u8 Stream) +void XDptx_SetVideoMode (XDptx *InstancePtr, u8 Stream) -void XDptx_ClearMsaValues (XDptx *InstancePtr, u8 Stream) +void XDptx_ClearMsaValues (XDptx *InstancePtr, u8 Stream) -void XDptx_SetMsaValues (XDptx *InstancePtr, u8 Stream) +void XDptx_SetMsaValues (XDptx *InstancePtr, u8 Stream)

    Function Documentation

    - +
    @@ -103,7 +105,7 @@ This function enables or disables synchronous clock mode for a video stream.

    - +

    @@ -143,7 +145,7 @@ This function calculates the following Main Stream Attributes (MSA):

      - +

    @@ -188,7 +190,7 @@ This function sets the bits per color value of the video stream.

    - +

    @@ -242,7 +244,7 @@ This function takes a the main stream attributes from MsaConfigCustom and copies

    - +

    @@ -287,7 +289,7 @@ This function sets the main stream attribute values in the configuration structu

    - +

    @@ -306,7 +308,7 @@ This function sets the main stream attribute values in the configuration structu - + @@ -332,7 +334,7 @@ This function sets the Main Stream Attribute (MSA) values in the configuration s

    - +

    XDptx_VideoMode XVid_VideoMode  VideoMode 
    @@ -370,7 +372,7 @@ This function clears the main stream attributes registers of the DisplayPort TX

    - +

    @@ -408,7 +410,7 @@ This function sets the main stream attributes registers of the DisplayPort TX co

    - +