diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c
index e3b7d796..50e06362 100755
--- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c
+++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c
@@ -93,7 +93,7 @@
 *                    Added RX threshold reset(1) after transfer in polled and
 *                    interrupt transfers. Made changes to make sure threshold
 *                    change is done only when no transfer is in progress.
-* 3.1   hk  06/19/14 When writng configuration register, set/reset
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
 *                    required bits leaving reserved bits untouched. CR# 796813.
 *
 * </pre>
@@ -275,8 +275,10 @@ void XQspiPs_Reset(XQspiPs *InstancePtr)
 	 */
 	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
 			 XQSPIPS_CR_OFFSET);
+	ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+	ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
 	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
-			  ConfigReg | XQSPIPS_CR_RESET_STATE);
+			  ConfigReg);
 }
 
 /*****************************************************************************/
diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h
index e2409228..b0e1b450 100755
--- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h
+++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h
@@ -263,7 +263,7 @@
 *                    change is done only when no transfer is in progress.
 *                    Updated linear init API for parallel and stacked modes.
 *                    CR#737760.
-* 3.1   hk  06/19/14 When writng configuration register, set/reset
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
 *                    required bits leaving reserved bits untouched. CR# 796813.
 *
 * </pre>
diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.c b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.c
index ae375c93..303bc9f0 100755
--- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.c
+++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.c
@@ -42,7 +42,7 @@
 * Ver   Who Date     Changes
 * ----- --- -------- -----------------------------------------------
 * 2.03a hk  09/17/13 First release
-* 3.1   hk  06/19/14 When writng configuration register, set/reset
+* 3.1   hk  06/19/14 When writing to the configuration register, set/reset
 *                    required bits leaving reserved bits untouched. CR# 796813.
 *
 * </pre>
@@ -140,8 +140,9 @@ void XQspiPs_ResetHw(u32 BaseAddress)
 	 * Write default value to configuration register
 	 */
 	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
-	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
-				ConfigReg | XQSPIPS_CR_RESET_STATE);
+	ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+	ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
 
 	/*
 	 * De-select linear mode
@@ -167,6 +168,7 @@ void XQspiPs_LinearInit(u32 BaseAddress)
 {
 	u32 BaudRateDiv;
 	u32 LinearCfg;
+	u32 ConfigReg;
 
 	/*
 	 * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
@@ -178,10 +180,10 @@ void XQspiPs_LinearInit(u32 BaseAddress)
 	 * Write configuration register with default values, slave selected &
 	 * pre-scaler value for divide by 4
 	 */
-	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
-				((XQSPIPS_CR_RESET_STATE |
-				XQSPIPS_CR_HOLD_B_MASK | BaudRateDiv) &
-				(~XQSPIPS_CR_SSCTRL_MASK) ));
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
+	ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
 
 	/*
 	 * Write linear configuration register with default value -
diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h
index 2246c40a..08dc53c1 100755
--- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h
+++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h
@@ -55,10 +55,9 @@
 * 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
 *                    linear mode initialization for boot. Added related
 *                    constant definitions.
-* 3.1   hk  06/19/14 Changed definition of XQSPIPS_CR_RESET_STATE to set/reset
+* 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
 *                    required bits leaving reserved bits untouched. CR# 796813.
 *
-*
 * </pre>
 *
 ******************************************************************************/
@@ -137,19 +136,19 @@ extern "C" {
 #define XQSPIPS_CR_REF_CLK_MASK   0x00000100 /**< Ref clk bit - should be 0 */
 
 /* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_STATE    ((XQSPIPS_CR_IFMODE_MASK | \
+#define XQSPIPS_CR_RESET_MASK_SET  XQSPIPS_CR_IFMODE_MASK | \
 				   XQSPIPS_CR_SSCTRL_MASK | \
 				   XQSPIPS_CR_DATA_SZ_MASK | \
 				   XQSPIPS_CR_MSTREN_MASK | \
 				   XQSPIPS_CR_SSFORCE_MASK | \
-				   XQSPIPS_CR_HOLD_B_MASK) & \
-				   (~(XQSPIPS_CR_CPOL_MASK | \
+				   XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR  XQSPIPS_CR_CPOL_MASK | \
 				   XQSPIPS_CR_CPHA_MASK | \
 				   XQSPIPS_CR_PRESC_MASK | \
 				   XQSPIPS_CR_MANSTRTEN_MASK | \
 				   XQSPIPS_CR_MANSTRT_MASK | \
 				   XQSPIPS_CR_ENDIAN_MASK | \
-				   XQSPIPS_CR_REF_CLK_MASK)))
+				   XQSPIPS_CR_REF_CLK_MASK
 /* @} */