From e3b8e045d048cdf4a5236c163ca1a331bbc2c4ff Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Patakamuri Date: Mon, 6 Oct 2014 15:28:28 +0530 Subject: [PATCH] sw_apps:zynq_fsbl:Updated ps7 init files in misc folder Updated ps7 init files in misc folder for zc702, zc706,zed,microzed boards Signed-off-by: Krishna Chaitanya Patakamuri --- .../zynq_fsbl/misc/microzed/ps7_init.c | 1230 ++++++++----- .../zynq_fsbl/misc/microzed/ps7_init.h | 43 +- .../zynq_fsbl/misc/microzed/ps7_init_gpl.c | 1214 +++++++----- .../zynq_fsbl/misc/microzed/ps7_init_gpl.h | 26 +- lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c | 1620 ++++++++++------- lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h | 43 +- .../zynq_fsbl/misc/zc702/ps7_init_gpl.c | 1604 +++++++++------- .../zynq_fsbl/misc/zc702/ps7_init_gpl.h | 26 +- lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c | 1608 +++++++++------- lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h | 43 +- .../zynq_fsbl/misc/zc706/ps7_init_gpl.c | 1592 ++++++++++------ .../zynq_fsbl/misc/zc706/ps7_init_gpl.h | 26 +- lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c | 1080 +++++++---- lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.h | 43 +- lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c | 1064 +++++++---- lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.h | 26 +- 16 files changed, 7146 insertions(+), 4142 deletions(-) diff --git a/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init.c index 17e3a403..15f742a3 100644 --- a/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init.c +++ b/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init.c @@ -1,32 +1,28 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. * ******************************************************************************/ /****************************************************************************/ @@ -3654,8 +3650,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -3748,153 +3742,281 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -7826,8 +7948,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -7926,153 +8046,281 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -11931,8 +12179,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -12031,153 +12277,281 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // diff --git a/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init.h index 33e084c8..3f801a6a 100644 --- a/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init.h +++ b/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init.h @@ -1,34 +1,31 @@ + /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or * (b) that interact with a Xilinx device through a bus or interconnect. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. * -******************************************************************************/ +*******************************************************************************/ /****************************************************************************/ /** * diff --git a/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init_gpl.c b/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init_gpl.c index 385f7fa4..427a2ded 100644 --- a/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init_gpl.c +++ b/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init_gpl.c @@ -1,31 +1,31 @@ /****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* Copyright (C) 2012 - 2014 Xilinx Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. * -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. +* You should have received a copy of the GNU General Public License along +* with this program; if not, see * -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . * ******************************************************************************/ /****************************************************************************/ /** * -* @file ps7_init.c +* @file ps7_init_gpl.c * * This file is automatically generated * *****************************************************************************/ -#include "ps7_init.h" +#include "ps7_init_gpl.h" unsigned long ps7_pll_init_data_3_0[] = { // START: top @@ -3641,8 +3641,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -3735,153 +3733,281 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -7813,8 +7939,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -7913,153 +8037,281 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -11918,8 +12170,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -12018,153 +12268,281 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // diff --git a/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init_gpl.h index 1a25c9a8..fdb86ef2 100644 --- a/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init_gpl.h +++ b/lib/sw_apps/zynq_fsbl/misc/microzed/ps7_init_gpl.h @@ -1,21 +1,23 @@ + /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx Inc. +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. * -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. * -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . +* You should have received a copy of the GNU General Public License along +* with this program; if not, see * -******************************************************************************/ +* +*******************************************************************************/ /****************************************************************************/ /** * diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c index 02dd98b1..a8927679 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c +++ b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c @@ -1,32 +1,28 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. * ******************************************************************************/ /****************************************************************************/ @@ -3693,8 +3689,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -3787,221 +3781,349 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -7978,8 +8100,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -8078,221 +8198,349 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -12196,8 +12444,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -12296,221 +12542,349 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h index 04faa678..6fc4ff23 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h +++ b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h @@ -1,34 +1,31 @@ + /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or * (b) that interact with a Xilinx device through a bus or interconnect. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. * -******************************************************************************/ +*******************************************************************************/ /****************************************************************************/ /** * diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.c b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.c index 3e81e5bb..d063f834 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.c +++ b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.c @@ -1,31 +1,31 @@ /****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* Copyright (C) 2012 - 2014 Xilinx Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. * -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. +* You should have received a copy of the GNU General Public License along +* with this program; if not, see * -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . * ******************************************************************************/ /****************************************************************************/ /** * -* @file ps7_init.c +* @file ps7_init_gpl.c * * This file is automatically generated * *****************************************************************************/ -#include "ps7_init.h" +#include "ps7_init_gpl.h" unsigned long ps7_pll_init_data_3_0[] = { // START: top @@ -3680,8 +3680,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -3774,221 +3772,349 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -7965,8 +8091,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -8065,221 +8189,349 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -12183,8 +12435,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -12283,221 +12533,349 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. DATA_0_LSW = 0x800 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. DIRECTION_0 = 0x2880 - // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_0 = 0x2880 - // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U - // .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.h index 2028e3ec..f936cfff 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.h +++ b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.h @@ -1,21 +1,23 @@ + /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx Inc. +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. * -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. * -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . +* You should have received a copy of the GNU General Public License along +* with this program; if not, see * -******************************************************************************/ +* +*******************************************************************************/ /****************************************************************************/ /** * diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c index d4d2cda3..1d82f789 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c +++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c @@ -1,32 +1,28 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. * ******************************************************************************/ /****************************************************************************/ @@ -3662,8 +3658,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -3756,221 +3750,349 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -7916,8 +8038,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -8016,221 +8136,349 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -12103,8 +12351,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -12203,221 +12449,349 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h index bcce5715..76919d5a 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h +++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h @@ -1,34 +1,31 @@ + /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or * (b) that interact with a Xilinx device through a bus or interconnect. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. * -******************************************************************************/ +*******************************************************************************/ /****************************************************************************/ /** * diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.c b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.c index f5449ed4..d50d25ae 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.c +++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.c @@ -1,31 +1,31 @@ /****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* Copyright (C) 2012 - 2014 Xilinx Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. * -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. +* You should have received a copy of the GNU General Public License along +* with this program; if not, see * -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . * ******************************************************************************/ /****************************************************************************/ /** * -* @file ps7_init.c +* @file ps7_init_gpl.c * * This file is automatically generated * *****************************************************************************/ -#include "ps7_init.h" +#include "ps7_init_gpl.h" unsigned long ps7_pll_init_data_3_0[] = { // START: top @@ -3649,8 +3649,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -3743,221 +3741,349 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -7903,8 +8029,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -8003,221 +8127,349 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -12090,8 +12342,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -12190,221 +12440,349 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. DIRECTION_0 = 0x80 - // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x0 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. DATA_0_LSW = 0x80 - // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. DIRECTION_1 = 0xc000 - // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. OP_ENABLE_1 = 0xc000 - // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U - // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x0000C000U - // .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U), - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x0 - // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h index 78efc198..a0544814 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h +++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h @@ -1,21 +1,23 @@ + /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx Inc. +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. * -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. * -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . +* You should have received a copy of the GNU General Public License along +* with this program; if not, see * -******************************************************************************/ +* +*******************************************************************************/ /****************************************************************************/ /** * diff --git a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c index aaed5c0d..b8fd37e3 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c +++ b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c @@ -1,32 +1,28 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. * ******************************************************************************/ /****************************************************************************/ @@ -2272,9 +2268,9 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. TRI_ENABLE = 0 // .. ==> 0XF8000720[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000720[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U @@ -2297,7 +2293,7 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. ==> 0XF8000720[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000724[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -3654,8 +3650,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -3748,119 +3742,247 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -6410,9 +6532,9 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. TRI_ENABLE = 0 // .. ==> 0XF8000720[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000720[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U @@ -6435,7 +6557,7 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. ==> 0XF8000720[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000724[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -7792,8 +7914,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -7892,119 +8012,247 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -10481,9 +10729,9 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. TRI_ENABLE = 0 // .. ==> 0XF8000720[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000720[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U @@ -10506,7 +10754,7 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. ==> 0XF8000720[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000724[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -11863,8 +12111,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -11963,119 +12209,247 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // diff --git a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.h index 245bff63..eaf80c7b 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.h +++ b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.h @@ -1,34 +1,31 @@ + /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or * (b) that interact with a Xilinx device through a bus or interconnect. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. * -******************************************************************************/ +*******************************************************************************/ /****************************************************************************/ /** * diff --git a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c index 8b367be6..678090fa 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c +++ b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c @@ -1,31 +1,31 @@ /****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* Copyright (C) 2012 - 2014 Xilinx Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. * -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. +* You should have received a copy of the GNU General Public License along +* with this program; if not, see * -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . * ******************************************************************************/ /****************************************************************************/ /** * -* @file ps7_init.c +* @file ps7_init_gpl.c * * This file is automatically generated * *****************************************************************************/ -#include "ps7_init.h" +#include "ps7_init_gpl.h" unsigned long ps7_pll_init_data_3_0[] = { // START: top @@ -2259,9 +2259,9 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. TRI_ENABLE = 0 // .. ==> 0XF8000720[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000720[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U @@ -2284,7 +2284,7 @@ unsigned long ps7_mio_init_data_3_0[] = { // .. ==> 0XF8000720[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000724[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -3641,8 +3641,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -3735,119 +3733,247 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -6397,9 +6523,9 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. TRI_ENABLE = 0 // .. ==> 0XF8000720[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000720[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U @@ -6422,7 +6548,7 @@ unsigned long ps7_mio_init_data_2_0[] = { // .. ==> 0XF8000720[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000724[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -7779,8 +7905,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -7879,119 +8003,247 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // @@ -10468,9 +10720,9 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. TRI_ENABLE = 0 // .. ==> 0XF8000720[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000720[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U @@ -10493,7 +10745,7 @@ unsigned long ps7_mio_init_data_1_0[] = { // .. ==> 0XF8000720[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000724[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -11850,8 +12102,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: TRACE CURRENT PORT SIZE - // .. FINISH: TRACE CURRENT PORT SIZE // .. START: UART REGISTERS // .. BDIV = 0x6 // .. ==> 0XE0001034[7:0] = 0x00000006U @@ -11950,119 +12200,247 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: DIR MODE BANK 1 - // .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET - // .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: OUTPUT ENABLE - // .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. START: ADD 1 MS DELAY - // .. .. .. + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. FINISH: I2C RESET + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // diff --git a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.h index 15f8c45e..5777a336 100644 --- a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.h +++ b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.h @@ -1,21 +1,23 @@ + /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx Inc. +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. * -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. * -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . +* You should have received a copy of the GNU General Public License along +* with this program; if not, see * -******************************************************************************/ +* +*******************************************************************************/ /****************************************************************************/ /** *