diff --git a/XilinxProcessorIPLib/drivers/sysmon/data/sysmon.mdd b/XilinxProcessorIPLib/drivers/sysmon/data/sysmon.mdd index cc601833..294a6977 100755 --- a/XilinxProcessorIPLib/drivers/sysmon/data/sysmon.mdd +++ b/XilinxProcessorIPLib/drivers/sysmon/data/sysmon.mdd @@ -40,12 +40,13 @@ # Ver Who Date Changes # -------- ------ -------- -------------------------------------------------- # 6.0 adk 10/12/13 Removed support for xps_sysmon_adc +# 7.0 bss 7/25/14 Added support for Ultrascale. ############################################################################## OPTION psf_version = 2.1; BEGIN driver sysmon - OPTION supported_peripherals = (axi_sysmon_adc axi_xadc xadc_wiz); + OPTION supported_peripherals = (axi_sysmon_adc axi_xadc xadc_wiz system_management_wiz); OPTION copyfiles = all; OPTION driver_state = ACTIVE; OPTION NAME = sysmon; diff --git a/XilinxProcessorIPLib/drivers/sysmon/data/sysmon.tcl b/XilinxProcessorIPLib/drivers/sysmon/data/sysmon.tcl index 817db0b5..ced4789a 100755 --- a/XilinxProcessorIPLib/drivers/sysmon/data/sysmon.tcl +++ b/XilinxProcessorIPLib/drivers/sysmon/data/sysmon.tcl @@ -28,13 +28,155 @@ # in advertising or otherwise to promote the sale, use or other dealings in # this Software without prior written authorization from Xilinx. # +# MODIFICATION HISTORY: +# Ver Who Date Changes +# -------- ------ -------- -------------------------------------------------- +# 7.0 bss 7/25/14 Added support for Ultrascale. ############################################################################## #uses "xillib.tcl" proc generate {drv_handle} { xdefine_include_file $drv_handle "xparameters.h" "XSysMon" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_INCLUDE_INTR" - xdefine_config_file $drv_handle "xsysmon_g.c" "XSysMon" "DEVICE_ID" "C_BASEADDR" "C_INCLUDE_INTR" + xdefine_config_file $drv_handle "xsysmon_g.c" "XSysMon" "DEVICE_ID" "C_BASEADDR" "C_INCLUDE_INTR" "IP_TYPE" xdefine_canonical_xpars $drv_handle "xparameters.h" "SysMon" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_INCLUDE_INTR" } + +proc xdefine_include_file {drv_handle file_name drv_string args} { + set args [::hsm::utils::get_exact_arg_list $args] + # Open include file + set file_handle [::hsm::utils::open_include_file $file_name] + + # Get all peripherals connected to this driver + set periphs [::hsm::utils::get_common_driver_ips $drv_handle] + + # Handle special cases + set arg "NUM_INSTANCES" + set posn [lsearch -exact $args $arg] + if {$posn > -1} { + puts $file_handle "/* Definitions for driver [string toupper [get_property name $drv_handle]] */" + # Define NUM_INSTANCES + puts $file_handle "#define [::hsm::utils::get_driver_param_name $drv_string $arg] [llength $periphs]" + set args [lreplace $args $posn $posn] + } + + # Check if it is a driver parameter + lappend newargs + foreach arg $args { + set value [get_property CONFIG.$arg $drv_handle] + if {[llength $value] == 0} { + lappend newargs $arg + } else { + puts $file_handle "#define [::hsm::utils::get_driver_param_name $drv_string $arg] [get_property $arg $drv_handle]" + } + } + set args $newargs + + # Print all parameters for all peripherals + set device_id 0 + foreach periph $periphs { + puts $file_handle "" + puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */" + + set ipname [string tolower [get_property IP_NAME $periph]] + if {[string compare -nocase "system_management_wiz" $ipname] == 0} { + puts $file_handle "#define [::hsm::utils::get_ip_param_name $periph "IP_TYPE"] 1" + } else { + puts $file_handle "#define [::hsm::utils::get_ip_param_name $periph "IP_TYPE"] 0" + } + + foreach arg $args { + if {[string compare -nocase "DEVICE_ID" $arg] == 0} { + set value $device_id + incr device_id + } else { + set value [get_property CONFIG.$arg $periph] + } + if {[llength $value] == 0} { + set value 0 + } + set value [::hsm::utils::format_addr_string $value $arg] + if {[string compare -nocase "HW_VER" $arg] == 0} { + puts $file_handle "#define [::hsm::utils::get_ip_param_name $periph $arg] \"$value\"" + } else { + puts $file_handle "#define [::hsm::utils::get_ip_param_name $periph $arg] $value" + } + } + puts $file_handle "" + } + puts $file_handle "\n/******************************************************************/\n" + close $file_handle +} + +proc xdefine_canonical_xpars {drv_handle file_name drv_string args} { + set args [::hsm::utils::get_exact_arg_list $args] + # Open include file + set file_handle [::hsm::utils::open_include_file $file_name] + + # Get all the peripherals connected to this driver + set periphs [::hsm::utils::get_common_driver_ips $drv_handle] + + # Get the names of all the peripherals connected to this driver + foreach periph $periphs { + set peripheral_name [string toupper [get_property NAME $periph]] + lappend peripherals $peripheral_name + } + + # Get possible canonical names for all the peripherals connected to this + # driver + set device_id 0 + foreach periph $periphs { + set canonical_name [string toupper [format "%s_%s" $drv_string $device_id]] + lappend canonicals $canonical_name + + # Create a list of IDs of the peripherals whose hardware instance name + # doesn't match the canonical name. These IDs can be used later to + # generate canonical definitions + if { [lsearch $peripherals $canonical_name] < 0 } { + lappend indices $device_id + } + incr device_id + } + + set i 0 + foreach periph $periphs { + set periph_name [string toupper [get_property NAME $periph]] + + # Generate canonical definitions only for the peripherals whose + # canonical name is not the same as hardware instance name + if { [lsearch $canonicals $periph_name] < 0 } { + puts $file_handle "/* Canonical definitions for peripheral $periph_name */" + set canonical_name [format "%s_%s" $drv_string [lindex $indices $i]] + + set ipname [string tolower [get_property IP_NAME $periph]] + if {[string compare -nocase "system_management_wiz" $ipname] == 0} { + puts $file_handle "#define [::hsm::utils::get_driver_param_name $canonical_name "IP_TYPE"] 1" + } else { + puts $file_handle "#define [::hsm::utils::get_driver_param_name $canonical_name "IP_TYPE"] 0" + } + + foreach arg $args { + set lvalue [::hsm::utils::get_driver_param_name $canonical_name $arg] + + # The commented out rvalue is the name of the instance-specific constant + # set rvalue [::hsm::utils::get_ip_param_name $periph $arg] + # The rvalue set below is the actual value of the parameter + set rvalue [::hsm::utils::get_param_value $periph $arg] + if {[llength $rvalue] == 0} { + set rvalue 0 + } + set rvalue [::hsm::utils::format_addr_string $rvalue $arg] + + puts $file_handle "#define $lvalue $rvalue" + + } + puts $file_handle "" + incr i + } + } + + puts $file_handle "\n/******************************************************************/\n" + close $file_handle +} + diff --git a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c index c11503c4..60fb2297 100755 --- a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c +++ b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c @@ -63,6 +63,13 @@ * XSysMon_SetSeqAvgEnables, XSysMon_SetSeqInputMode * and XSysMon_SetSeqAcqTime APIs to check for Safe Mode * instead of Single Channel mode. CR #703729 +* 7.0 bss 7/25/14 Modified XSysMon_GetAdcData, +* XSysMon_GetMinMaxMeasurement, +* XSysMon_SetSingleChParams, XSysMon_SetAlarmEnables, +* XSysMon_GetAlarmEnables,XSysMon_SetSeqChEnables, +* XSysMon_GetSeqChEnables,XSysMon_SetSeqAvgEnables, +* XSysMon_GetSeqAvgEnables,XSysMon_SetAlarmThreshold +* and XSysMon_GetAlarmThreshold to support Ultrascale * * *****************************************************************************/ @@ -322,8 +329,8 @@ void XSysMon_ResetAdc(XSysMon *InstancePtr) * the file xsysmon.h. * The valid channels are 0 to 5 and 16 to 31 for all the device * families. Channel 6 is valid for 7 Series and Zynq. -* Channel 13, 14, 15 are valid for Zynq. -* . +* Channel 13, 14, 15 are valid for Zynq. 32 to 35 are valid for +* Ultrascale. * * @return A 16-bit value representing the ADC converted data for the * specified channel. The System Monitor/ADC device guarantees @@ -345,14 +352,23 @@ u16 XSysMon_GetAdcData(XSysMon *InstancePtr, u8 Channel) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid((Channel <= XSM_CH_VBRAM) || ((Channel >= XSM_CH_VCCPINT) && - (Channel <= XSM_CH_AUX_MAX))); + (Channel <= XSM_CH_AUX_MAX)) || + ((Channel >= XSM_CH_VUSR0) && + (Channel <= XSM_CH_VUSR3))); /* * Read the selected ADC converted data for the specified channel * and return the value. */ - AdcData = (u16) (XSysMon_ReadReg(InstancePtr->Config.BaseAddress, - XSM_TEMP_OFFSET + (Channel << 2))); + if (Channel <= XSM_CH_AUX_MAX) { + AdcData = (u16) (XSysMon_ReadReg(InstancePtr-> + Config.BaseAddress, XSM_TEMP_OFFSET + + (Channel << 2))); + } else { + AdcData = (u16) (XSysMon_ReadReg(InstancePtr-> + Config.BaseAddress, XSM_VUSR0_OFFSET + + ((Channel - XSM_CH_VUSR0) << 2))); + } return AdcData; } @@ -401,12 +417,12 @@ u16 XSysMon_GetCalibCoefficient(XSysMon *InstancePtr, u8 CoeffType) * * This function reads the Minimum/Maximum measurement for one of the * following parameters : -* - Minimum Temperature (XSM_MIN_TEMP) -* - Minimum VCCINT (XSM_MIN_VCCINT) -* - Minimum VCCAUX (XSM_MIN_VCCAUX) -* - Maximum Temperature (XSM_MAX_TEMP) -* - Maximum VCCINT (XSM_MAX_VCCINT) -* - Maximum VCCAUX (XSM_MAX_VCCAUX) +* - Minimum Temperature (XSM_MIN_TEMP) - All families +* - Minimum VCCINT (XSM_MIN_VCCINT) - All families +* - Minimum VCCAUX (XSM_MIN_VCCAUX) - All families +* - Maximum Temperature (XSM_MAX_TEMP) - All families +* - Maximum VCCINT (XSM_MAX_VCCINT) - All families +* - Maximum VCCAUX (XSM_MAX_VCCAUX) - All families * - Maximum VCCBRAM (XSM_MAX_VCCBRAM) - 7 series and Zynq only * - Minimum VCCBRAM (XSM_MIN_VCCBRAM) - 7 series and Zynq only * - Maximum VCCPINT (XSM_MAX_VCCPINT) - Zynq only @@ -415,6 +431,14 @@ u16 XSysMon_GetCalibCoefficient(XSysMon *InstancePtr, u8 CoeffType) * - Minimum VCCPINT (XSM_MIN_VCCPINT) - Zynq only * - Minimum VCCPAUX (XSM_MIN_VCCPAUX) - Zynq only * - Minimum VCCPDRO (XSM_MIN_VCCPDRO) - Zynq only +* - Maximum VUSER0 (XSM_MAX_VUSR0) - Ultrascale +* - Maximum VUSER1 (XSM_MAX_VUSR1) - Ultrascale +* - Maximum VUSER2 (XSM_MAX_VUSR2) - Ultrascale +* - Maximum VUSER3 (XSM_MAX_VUSR3) - Ultrascale +* - Minimum VUSER0 (XSM_MIN_VUSR0) - Ultrascale +* - Minimum VUSER1 (XSM_MIN_VUSR1) - Ultrascale +* - Minimum VUSER2 (XSM_MIN_VUSR2) - Ultrascale +* - Minimum VUSER3 (XSM_MIN_VUSR3) - Ultrascale * * @param InstancePtr is a pointer to the XSysMon instance. * @param MeasurementType specifies the parameter for which the @@ -428,8 +452,6 @@ u16 XSysMon_GetCalibCoefficient(XSysMon *InstancePtr, u8 CoeffType) * the ADC converted data and data is the 10 MSB bits of 16 bit * data read from the device. * -* @note BRAM VCC is available only in 7 Series and Zynq XADC. -* *****************************************************************************/ u16 XSysMon_GetMinMaxMeasurement(XSysMon *InstancePtr, u8 MeasurementType) { @@ -441,7 +463,11 @@ u16 XSysMon_GetMinMaxMeasurement(XSysMon *InstancePtr, u8 MeasurementType) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid((MeasurementType <= XSM_MAX_VCCPDRO) || ((MeasurementType >= XSM_MIN_VCCPINT) && - (MeasurementType <= XSM_MIN_VCCPDRO))) + (MeasurementType <= XSM_MIN_VCCPDRO)) || + ((MeasurementType >= XSM_MAX_VUSR0) && + (MeasurementType <= XSM_MAX_VUSR3)) || + ((MeasurementType >= XSM_MIN_VUSR0) && + (MeasurementType <= XSM_MIN_VUSR3))) /* @@ -540,9 +566,10 @@ u8 XSysMon_GetAvg(XSysMon *InstancePtr) * the single channel mode. * * @param InstancePtr is a pointer to the XSysMon instance. -* @param Channel is the channel number for which averaging is to be set. -* The valid channels are 0 to 5, 8, and 16 to 31. Channel 6 is -* valid for 7 series and Zynq XADC. +* @param Channel is the channel number for conversion. The valid +* channels are 0 to 5, 8, and 16 to 31. Channel 6 is +* valid for 7 series and Zynq XADC. Channel 32 to 35 are valid +* for Ultrascale. * @param IncreaseAcqCycles is a boolean parameter which specifies whether * the Acquisition time for the external channels has to be * increased to 10 ADCCLK cycles (specify TRUE) or remain at the @@ -584,7 +611,9 @@ int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel, Xil_AssertNonvoid((Channel <= XSM_CH_VREFN) || (Channel == XSM_CH_CALIBRATION) || ((Channel >= XSM_CH_AUX_MIN) && - (Channel <= XSM_CH_AUX_MAX))); + (Channel <= XSM_CH_AUX_MAX)) || + ((Channel >= XSM_CH_VUSR0) && + (Channel <= XSM_CH_VUSR3))); Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) || (IncreaseAcqCycles == FALSE)); Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE)); @@ -652,23 +681,28 @@ int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel, /** * * This function enables the alarm outputs for the specified alarms in the -* Configuration Register 1 : +* Configuration Registers 1 and 3: * -* - OT for Over Temperature (XSM_CFR1_OT_MASK) -* - ALM0 for On board Temperature (XSM_CFR1_ALM_TEMP_MASK) -* - ALM1 for VCCINT (XSM_CFR1_ALM_VCCINT_MASK) -* - ALM2 for VCCAUX (XSM_CFR1_ALM_VCCAUX_MASK) -* - ALM3 for VBRAM (XSM_CFR1_ALM_VBRAM_MASK)for 7 Series and Zynq -* - ALM4 for VCCPINT (XSM_CFR1_ALM_VCCPINT_MASK) for Zynq -* - ALM5 for VCCPAUX (XSM_CFR1_ALM_VCCPAUX_MASK) for Zynq -* - ALM6 for VCCPDRO (XSM_CFR1_ALM_VCCPDRO_MASK) for Zynq +* - OT for Over Temperature (XSM_CFR_OT_MASK) +* - ALM0 for On board Temperature (XSM_CFR_ALM_TEMP_MASK) +* - ALM1 for VCCINT (XSM_CFR_ALM_VCCINT_MASK) +* - ALM2 for VCCAUX (XSM_CFR_ALM_VCCAUX_MASK) +* - ALM3 for VBRAM (XSM_CFR_ALM_VBRAM_MASK)for 7 Series and Zynq +* - ALM4 for VCCPINT (XSM_CFR_ALM_VCCPINT_MASK) for Zynq +* - ALM5 for VCCPAUX (XSM_CFR_ALM_VCCPAUX_MASK) for Zynq +* - ALM6 for VCCPDRO (XSM_CFR_ALM_VCCPDRO_MASK) for Zynq +* - ALM8 for VUSER0 (XSM_CFR_ALM_VUSR0_MASK) for Ultrascale +* - ALM9 for VUSER1 (XSM_CFR_ALM_VUSR1_MASK) for Ultrascale +* - ALM10 for VUSER2 (XSM_CFR_ALM_VUSR2_MASK) for Ultrascale +* - ALM11 for VUSER3 (XSM_CFR_ALM_VUSR3_MASK) for Ultrascale * * @param InstancePtr is a pointer to the XSysMon instance. * @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled * in the Configuration Register 1. * Bit positions of 1 will be enabled. Bit positions of 0 will be -* disabled. This mask is formed by OR'ing XSM_CFR1_ALM_*_MASK and -* XSM_CFR1_OT_MASK masks defined in xsysmon_hw.h. +* disabled. This mask is formed by OR'ing XSM_CFR_ALM_*_MASK, +* XSM_CFR_ALM_*_MASK and XSM_CFR_OT_MASK masks defined in +* xsysmon_hw.h. * * @return None. * @@ -679,7 +713,7 @@ int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel, * before writing to the Configuration Register 1. * *****************************************************************************/ -void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u16 AlmEnableMask) +void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u32 AlmEnableMask) { u32 RegValue; @@ -688,7 +722,7 @@ void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u16 AlmEnableMask) */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(AlmEnableMask <= XSM_CFR1_ALM_ALL_MASK); + Xil_AssertVoid(AlmEnableMask <= XSM_CFR_ALM_ALL_MASK); RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, XSM_CFR1_OFFSET); @@ -701,6 +735,14 @@ void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u16 AlmEnableMask) */ XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR1_OFFSET, RegValue); + + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR3_OFFSET); + RegValue &= (u32)~XSM_CFR3_ALM_ALL_MASK; + RegValue |= (~(AlmEnableMask >> 16) & XSM_CFR3_ALM_ALL_MASK); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR3_OFFSET, + RegValue); } /****************************************************************************/ @@ -712,9 +754,10 @@ void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u16 AlmEnableMask) * @param InstancePtr is a pointer to the XSysMon instance. * * @return This is the bit-mask of the enabled alarm outputs in the -* Configuration Register 1. Use the masks XSM_CFR1_ALM*_* and -* XSM_CFR1_OT_MASK defined in xsysmon_hw.h to interpret the -* returned value. +* Configuration Register 1. Use the masks XSM_CFR_ALM_*, +* XSM_CFR_ALM*_* and XSM_CFR_OT_MASK defined in +* xsysmon_hw.h to interpret the returned value. +* * Bit positions of 1 indicate that the alarm output is enabled. * Bit positions of 0 indicate that the alarm output is disabled. * @@ -727,9 +770,10 @@ void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u16 AlmEnableMask) * Register 1. * *****************************************************************************/ -u16 XSysMon_GetAlarmEnables(XSysMon *InstancePtr) +u32 XSysMon_GetAlarmEnables(XSysMon *InstancePtr) { - u32 RegValue; + u32 RegValue1; + u32 RegValue2; /* * Assert the arguments. @@ -741,9 +785,15 @@ u16 XSysMon_GetAlarmEnables(XSysMon *InstancePtr) * Read the status of alarm output enables from the Configuration * Register 1. */ - RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + RegValue1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, XSM_CFR1_OFFSET) & XSM_CFR1_ALM_ALL_MASK; - return (u16) (~RegValue & XSM_CFR1_ALM_ALL_MASK); + RegValue1 = (~RegValue1 & XSM_CFR1_ALM_ALL_MASK); + + RegValue2 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR3_OFFSET) & XSM_CFR3_ALM_ALL_MASK; + RegValue2 = (~RegValue2 & XSM_CFR3_ALM_ALL_MASK); + + return ((RegValue2 << 16) | RegValue1); } /****************************************************************************/ @@ -1096,7 +1146,7 @@ u8 XSysMon_GetAdcClkDivisor(XSysMon *InstancePtr) * Use XSM_SEQ_CH_* defined in xsysmon_hw.h to specify the Channel * numbers. Bit masks of 1 will be enabled and bit mask of 0 will * be disabled. -* The ChEnableMask is a 32 bit mask that is written to the two +* The ChEnableMask is a 64 bit mask that is written to the three * 16 bit ADC Channel Selection Sequencer Registers. * * @return @@ -1107,7 +1157,7 @@ u8 XSysMon_GetAdcClkDivisor(XSysMon *InstancePtr) * @note None. * *****************************************************************************/ -int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u32 ChEnableMask) +int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u64 ChEnableMask) { /* * Assert the arguments. @@ -1137,6 +1187,11 @@ int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u32 ChEnableMask) (ChEnableMask >> XSM_SEQ_CH_AUX_SHIFT) & XSM_SEQ01_CH_VALID_MASK); + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ08_OFFSET, + (ChEnableMask >> XSM_SEQ_CH_VUSR_SHIFT) & + XSM_SEQ08_CH_VALID_MASK); + return XST_SUCCESS; } @@ -1158,9 +1213,11 @@ int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u32 ChEnableMask) * @note None. * *****************************************************************************/ -u32 XSysMon_GetSeqChEnables(XSysMon *InstancePtr) +u64 XSysMon_GetSeqChEnables(XSysMon *InstancePtr) { u32 RegValEnable; + u32 RegValEnable1; + u64 RetVal = 0x0; /* * Assert the arguments. @@ -1178,7 +1235,14 @@ u32 XSysMon_GetSeqChEnables(XSysMon *InstancePtr) XSM_SEQ01_OFFSET) & XSM_SEQ01_CH_VALID_MASK) << XSM_SEQ_CH_AUX_SHIFT; - return RegValEnable; + RegValEnable1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ08_OFFSET) & XSM_SEQ08_CH_VALID_MASK; + + RetVal = RegValEnable1; + RetVal = (RetVal << XSM_SEQ_CH_VUSR_SHIFT); + RetVal = RetVal | RegValEnable; + + return RetVal; } /****************************************************************************/ @@ -1193,8 +1257,8 @@ u32 XSysMon_GetSeqChEnables(XSysMon *InstancePtr) * averaging is to be enabled. Use XSM_SEQ_CH__* defined in * xsysmon_hw.h to specify the Channel numbers. Averaging will be * enabled for bit masks of 1 and disabled for bit mask of 0. -* The AvgEnableChMask is a 32 bit mask that is written to the two -* 16 bit ADC Channel Averaging Enable Sequencer Registers. +* The AvgEnableChMask is a 64 bit mask that is written to the +* three 16 bit ADC Channel Averaging Enable Sequencer Registers. * * @return * - XST_SUCCESS if the given values were written successfully to @@ -1204,7 +1268,7 @@ u32 XSysMon_GetSeqChEnables(XSysMon *InstancePtr) * @note None. * *****************************************************************************/ -int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u32 AvgEnableChMask) +int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u64 AvgEnableChMask) { /* * Assert the arguments. @@ -1233,6 +1297,11 @@ int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u32 AvgEnableChMask) (AvgEnableChMask >> XSM_SEQ_CH_AUX_SHIFT) & XSM_SEQ03_CH_VALID_MASK); + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ09_OFFSET, + (AvgEnableChMask >> XSM_SEQ_CH_VUSR_SHIFT) & + XSM_SEQ09_CH_VALID_MASK); + return XST_SUCCESS; } @@ -1253,9 +1322,11 @@ int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u32 AvgEnableChMask) * @note None. * *****************************************************************************/ -u32 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr) +u64 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr) { u32 RegValAvg; + u32 RegValAvg1; + u64 RetVal = 0x0; /* * Assert the arguments. @@ -1273,7 +1344,14 @@ u32 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr) XSM_SEQ03_OFFSET) & XSM_SEQ03_CH_VALID_MASK) << XSM_SEQ_CH_AUX_SHIFT; - return RegValAvg; + RegValAvg1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ09_OFFSET) & XSM_SEQ09_CH_VALID_MASK; + + RetVal = RegValAvg1; + RetVal = (RetVal << XSM_SEQ_CH_VUSR_SHIFT); + RetVal = RetVal | RegValAvg; + + return RetVal; } /****************************************************************************/ @@ -1484,10 +1562,12 @@ u32 XSysMon_GetSeqAcqTime(XSysMon *InstancePtr) * * @return None. * -* @note Over Temperature upper threshold is programmable only in V6 and -* 7 Series/Zynq XADC. +* @note Over Temperature upper threshold is programmable only in V6, +* 7 Series/Zynq XADC and UltraScale. * BRAM high and low voltage threshold registers are available only -* in 7 Series XADC. +* in 7 Series XADC and UltraScale. +* VUSER0 to VUSER3 threshold registers are available only in +* UltraScale. * All the remaining Alarm Threshold registers specified by the * constants XSM_ATR_*, are available in all the families of the * Sysmon. @@ -1500,8 +1580,9 @@ void XSysMon_SetAlarmThreshold(XSysMon *InstancePtr, u8 AlarmThrReg, u16 Value) */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((AlarmThrReg <= XSM_ATR_VBRAM_UPPER) || - (AlarmThrReg == XSM_ATR_VBRAM_LOWER)); + Xil_AssertVoid((AlarmThrReg <= XSM_ATR_VUSR3_UPPER) || + ((AlarmThrReg >= XSM_ATR_VUSR0_LOWER) && + (AlarmThrReg <= XSM_ATR_VUSR3_LOWER))); /* * Write the value into the specified Alarm Threshold Register. @@ -1542,8 +1623,9 @@ u16 XSysMon_GetAlarmThreshold(XSysMon *InstancePtr, u8 AlarmThrReg) */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((AlarmThrReg <= XSM_ATR_VBRAM_UPPER) || - (AlarmThrReg == XSM_ATR_VBRAM_LOWER)); + Xil_AssertNonvoid((AlarmThrReg <= XSM_ATR_VUSR3_UPPER) || + ((AlarmThrReg >= XSM_ATR_VUSR0_LOWER) && + (AlarmThrReg <= XSM_ATR_VUSR3_LOWER))); /* * Read the specified Alarm Threshold Register and return diff --git a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.h b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.h index 61065a40..88a65143 100755 --- a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.h +++ b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.h @@ -139,11 +139,13 @@ * * Limitations of the driver * -* System Monitor/ADC device can be accessed through the JTAG port and the PLB +* System Monitor/ADC device can be accessed through the JTAG port and the AXI * interface. The driver implementation does not support the simultaneous access * of the device by both these interfaces. The user has to care of this situation * in the user application code. * +* +* *

* *
@@ -178,7 +180,26 @@
 *			xsysmon_polled_printf_example.c to set Sequencer Mode
 *			as Safe mode instead of Single channel mode before
 *			configuring Sequencer registers.
-* 6.0   adk  19/12/13 Updated as per the New Tcl API's
+* 6.0   adk  19/12/13   Updated as per the New Tcl API's
+* 7.0   bss  7/25/14    To support Ultrascale:
+*			Added XSM_CH_VUSR0 - XSMXSM_CH_VUSR3,XSM_MAX_VUSR0 -
+*			XSM_MIN_VUSR3,XSM_ATR_VUSR0_UPPER -
+*			XSM_ATR_VUSR3_LOWER macros.
+*			Added XSM_IP_OFFSET macro(since register
+*			offsets are different for Ultrascale comapared to
+*			earlier familes),Offsets,Masks for VUSER0 to
+*			VUSER3 channels, Configuration Register 3 and
+*			Sequence Registers 8 and 9 in xsysmon_hw.h.
+*			Modified XSysMon_GetAdcData,
+*			XSysMon_GetMinMaxMeasurement,
+*			XSysMon_SetSingleChParams, XSysMon_SetAlarmEnables,
+*			XSysMon_GetAlarmEnables,XSysMon_SetSeqChEnables,
+*			XSysMon_GetSeqChEnables,XSysMon_SetSeqAvgEnables,
+*			XSysMon_GetSeqAvgEnables,XSysMon_SetAlarmThreshold
+*			and XSysMon_GetAlarmThreshold in xsysmon.c.
+*			Modified driver tcl to generate XPAR_SYSMON_0_IP_TYPE
+*			parameter.
+*
 * 
* *****************************************************************************/ @@ -219,6 +240,11 @@ extern "C" { #define XSM_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel, Zynq */ #define XSM_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */ #define XSM_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */ +#define XSM_CH_VUSR0 32 /**< VUSER0 Supply - UltraScale */ +#define XSM_CH_VUSR1 33 /**< VUSER1 Supply - UltraScale */ +#define XSM_CH_VUSR2 34 /**< VUSER2 Supply - UltraScale */ +#define XSM_CH_VUSR3 35 /**< VUSER3 Supply - UltraScale */ + /*@}*/ @@ -246,12 +272,20 @@ extern "C" { #define XSM_MIN_VCCINT 5 /**< Minimum VCCINT Data */ #define XSM_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */ #define XSM_MIN_VCCBRAM 7 /**< Minimum VCCBRAM Data, 7 Series/Zynq */ -#define XSM_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */ -#define XSM_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */ -#define XSM_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */ -#define XSM_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */ -#define XSM_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */ -#define XSM_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */ +#define XSM_MAX_VCCPINT 8 /**< Maximum VCCPINT Data, Zynq */ +#define XSM_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Data, Zynq */ +#define XSM_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Data, Zynq */ +#define XSM_MIN_VCCPINT 0xC /**< Minimum VCCPINT Data, Zynq */ +#define XSM_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Data, Zynq */ +#define XSM_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Data, Zynq */ +#define XSM_MAX_VUSR0 0x80 /**< Maximum VUSR0 Data, Ultrascale */ +#define XSM_MAX_VUSR1 0x81 /**< Maximum VUSR1 Data, Ultrascale */ +#define XSM_MAX_VUSR2 0x82 /**< Maximum VUSR2 Data, Ultrascale */ +#define XSM_MAX_VUSR3 0x83 /**< Maximum VUSR3 Data, Ultrascale */ +#define XSM_MIN_VUSR0 0x88 /**< Minimum VUSR0 Data, Ultrascale */ +#define XSM_MIN_VUSR1 0x89 /**< Minimum VUSR1 Data, Ultrascale */ +#define XSM_MIN_VUSR2 0x8A /**< Minimum VUSR2 Data, Ultrascale */ +#define XSM_MIN_VUSR3 0x8B /**< Minimum VUSR3 Data, Ultrascale */ /*@}*/ @@ -262,21 +296,29 @@ extern "C" { * @{ */ #define XSM_ATR_TEMP_UPPER 0 /**< High user Temperature */ -#define XSM_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */ -#define XSM_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */ +#define XSM_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit */ +#define XSM_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit */ #define XSM_ATR_OT_UPPER 3 /**< Lower Over Temperature limit */ #define XSM_ATR_TEMP_LOWER 4 /**< Low user Temperature */ -#define XSM_ATR_VCCINT_LOWER 5 /**< VCCINT low voltage limit register */ -#define XSM_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */ +#define XSM_ATR_VCCINT_LOWER 5 /**< VCCINT low voltage limit */ +#define XSM_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit */ #define XSM_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */ -#define XSM_ATR_VBRAM_UPPER 8 /**< VBRAM high voltage limit register */ -#define XSM_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */ -#define XSM_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */ -#define XSM_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */ +#define XSM_ATR_VBRAM_UPPER 8 /**< VBRAM high voltage limit */ +#define XSM_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm, Zynq */ +#define XSM_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm, Zynq */ +#define XSM_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm, Zynq */ #define XSM_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm, 7 Series and Zynq*/ -#define XSM_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */ -#define XSM_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */ -#define XSM_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */ +#define XSM_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm, Zynq */ +#define XSM_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm, Zynq */ +#define XSM_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm, Zynq */ +#define XSM_ATR_VUSR0_UPPER 0x10 /**< VUSER0 Upper Alarm, Ultrascale */ +#define XSM_ATR_VUSR1_UPPER 0x11 /**< VUSER1 Upper Alarm, Ultrascale */ +#define XSM_ATR_VUSR2_UPPER 0x12 /**< VUSER2 Upper Alarm, Ultrascale */ +#define XSM_ATR_VUSR3_UPPER 0x13 /**< VUSER3 Upper Alarm, Ultrascale */ +#define XSM_ATR_VUSR0_LOWER 0x18 /**< VUSER0 Lower Alarm, Ultrascale */ +#define XSM_ATR_VUSR1_LOWER 0x19 /**< VUSER1 Lower Alarm, Ultrascale */ +#define XSM_ATR_VUSR2_LOWER 0x1A /**< VUSER2 Lower Alarm, Ultrascale */ +#define XSM_ATR_VUSR3_LOWER 0x1B /**< VUSER3 Lower Alarm, Ultrascale */ /*@}*/ @@ -324,6 +366,8 @@ typedef struct { u16 DeviceId; /**< Unique ID of device */ u32 BaseAddress; /**< Device base address */ int IncludeInterrupt; /**< Supports Interrupt driven mode */ + u8 IpType; /**< 1 - System Management */ + /**< 0 - XADC/System Monoitor */ } XSysMon_Config; @@ -506,8 +550,8 @@ int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel, int IncreaseAcqCycles, int IsEventMode, int IsDifferentialMode); -void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u16 AlmEnableMask); -u16 XSysMon_GetAlarmEnables(XSysMon *InstancePtr); +void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u32 AlmEnableMask); +u32 XSysMon_GetAlarmEnables(XSysMon *InstancePtr); void XSysMon_SetCalibEnables(XSysMon *InstancePtr, u16 Calibration); u16 XSysMon_GetCalibEnables(XSysMon *InstancePtr); @@ -521,11 +565,11 @@ void XSysMon_SetExtenalMux(XSysMon *InstancePtr, u8 Channel); void XSysMon_SetAdcClkDivisor(XSysMon *InstancePtr, u8 Divisor); u8 XSysMon_GetAdcClkDivisor(XSysMon *InstancePtr); -int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u32 ChEnableMask); -u32 XSysMon_GetSeqChEnables(XSysMon *InstancePtr); +int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u64 ChEnableMask); +u64 XSysMon_GetSeqChEnables(XSysMon *InstancePtr); -int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u32 AvgEnableChMask); -u32 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr); +int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u64 AvgEnableChMask); +u64 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr); int XSysMon_SetSeqInputMode(XSysMon *InstancePtr, u32 InputModeChMask); u32 XSysMon_GetSeqInputMode(XSysMon *InstancePtr); diff --git a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_hw.h b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_hw.h index 78d5baed..9a8a7310 100755 --- a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_hw.h +++ b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_hw.h @@ -58,6 +58,11 @@ * 5.02a bss 11/23/12 Added macros XSM_CONVST_TEMPUPDT_MASK, * XSM_CONVST_WAITCYCLES_MASK and * XSM_CONVST_WAITCYCLES_SHIFT (CR #679872) +* 7.0 bss 7/25/14 To support Ultrascale: +* Added XSM_IP_OFFSET macro. +* Added Offsets and Masks for VUSER0 to VUSER3 channels. +* Added Configuration Register 3 and Sequence Registers +* 8 and 9. * * * @@ -75,9 +80,21 @@ extern "C" { #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" +#include "xparameters.h" /************************** Constant Definitions ****************************/ +#define SYSTEM_MANAGEMENT 1 /* Ultrascale */ +#define XADC 0 /* 7 Series, Zynq */ + + +#if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT +#define XSM_IP_OFFSET 0x200 +#else +#define XSM_IP_OFFSET 0x00 +#endif + + /**@name Register offsets * * The following constants provide access to each of the registers of the @@ -104,99 +121,216 @@ extern "C" { /* * System Monitor/ADC Internal Channel Registers */ -#define XSM_TEMP_OFFSET 0x200 /**< On-chip Temperature Reg */ -#define XSM_VCCINT_OFFSET 0x204 /**< On-chip VCCINT Data Reg */ -#define XSM_VCCAUX_OFFSET 0x208 /**< On-chip VCCAUX Data Reg */ -#define XSM_VPVN_OFFSET 0x20C /**< ADC out of VP/VN */ -#define XSM_VREFP_OFFSET 0x210 /**< On-chip VREFP Data Reg */ -#define XSM_VREFN_OFFSET 0x214 /**< On-chip VREFN Data Reg */ -#define XSM_VBRAM_OFFSET 0x218 /**< On-chip VBRAM Data, 7 series/Zynq */ -#define XSM_SUPPLY_CALIB_OFFSET 0x220 /**< Supply Offset Data Reg */ -#define XSM_ADC_CALIB_OFFSET 0x224 /**< ADC Offset Data Reg */ -#define XSM_GAINERR_CALIB_OFFSET 0x228 /**< Gain Error Data Reg */ -#define XSM_VCCPINT_OFFSET 0x22C /**< PS VCCPINT Data Reg - Zynq */ -#define XSM_VCCPAUX_OFFSET 0x230 /**< PS VCCPAUX Data Reg - Zynq */ -#define XSM_VCCPDRO_OFFSET 0x234 /**< PS VCCPDRO Data Reg - Zynq */ +#define XSM_TEMP_OFFSET (XSM_IP_OFFSET + 0x200) + /**< On-chip Temperature Reg */ +#define XSM_VCCINT_OFFSET (XSM_IP_OFFSET + 0x204) + /**< On-chip VCCINT Data Reg */ +#define XSM_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x208) + /**< On-chip VCCAUX Data Reg */ +#define XSM_VPVN_OFFSET (XSM_IP_OFFSET + 0x20C) + /**< ADC out of VP/VN */ +#define XSM_VREFP_OFFSET (XSM_IP_OFFSET + 0x210) + /**< On-chip VREFP Data Reg */ +#define XSM_VREFN_OFFSET (XSM_IP_OFFSET + 0x214) + /**< On-chip VREFN Data Reg */ +#define XSM_VBRAM_OFFSET (XSM_IP_OFFSET + 0x218) + /**< On-chip VBRAM Data,7-series/Zynq */ +#define XSM_SUPPLY_CALIB_OFFSET (XSM_IP_OFFSET + 0x220) + /**< Supply Offset Data Reg */ +#define XSM_ADC_CALIB_OFFSET (XSM_IP_OFFSET + 0x224) + /**< ADC Offset Data Reg */ +#define XSM_GAINERR_CALIB_OFFSET (XSM_IP_OFFSET + 0x228) + /**< Gain Error Data Reg */ +#define XSM_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x22C) + /**< PS VCCPINT Data Reg - Zynq */ +#define XSM_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x230) + /**< PS VCCPAUX Data Reg - Zynq */ +#define XSM_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x234) + /**< PS VCCPDRO Data Reg - Zynq */ +#define XSM_VUSR0_OFFSET (XSM_IP_OFFSET + 0x400) + /**< VUSER0 Supply - Ultrascale */ +#define XSM_VUSR1_OFFSET (XSM_IP_OFFSET + 0x404) + /**< VUSER0 Supply - Ultrascale */ +#define XSM_VUSR2_OFFSET (XSM_IP_OFFSET + 0x408) + /**< VUSER0 Supply - Ultrascale */ +#define XSM_VUSR3_OFFSET (XSM_IP_OFFSET + 0x40C) + /**< VUSER0 Supply - Ultrascale */ + /* * System Monitor/ADC External Channel Registers */ -#define XSM_AUX00_OFFSET 0x240 /**< ADC out of VAUXP0/VAUXN0 */ -#define XSM_AUX01_OFFSET 0x244 /**< ADC out of VAUXP1/VAUXN1 */ -#define XSM_AUX02_OFFSET 0x248 /**< ADC out of VAUXP2/VAUXN2 */ -#define XSM_AUX03_OFFSET 0x24C /**< ADC out of VAUXP3/VAUXN3 */ -#define XSM_AUX04_OFFSET 0x250 /**< ADC out of VAUXP4/VAUXN4 */ -#define XSM_AUX05_OFFSET 0x254 /**< ADC out of VAUXP5/VAUXN5 */ -#define XSM_AUX06_OFFSET 0x258 /**< ADC out of VAUXP6/VAUXN6 */ -#define XSM_AUX07_OFFSET 0x25C /**< ADC out of VAUXP7/VAUXN7 */ -#define XSM_AUX08_OFFSET 0x260 /**< ADC out of VAUXP8/VAUXN8 */ -#define XSM_AUX09_OFFSET 0x264 /**< ADC out of VAUXP9/VAUXN9 */ -#define XSM_AUX10_OFFSET 0x268 /**< ADC out of VAUXP10/VAUXN10 */ -#define XSM_AUX11_OFFSET 0x26C /**< ADC out of VAUXP11/VAUXN11 */ -#define XSM_AUX12_OFFSET 0x270 /**< ADC out of VAUXP12/VAUXN12 */ -#define XSM_AUX13_OFFSET 0x274 /**< ADC out of VAUXP13/VAUXN13 */ -#define XSM_AUX14_OFFSET 0x278 /**< ADC out of VAUXP14/VAUXN14 */ -#define XSM_AUX15_OFFSET 0x27C /**< ADC out of VAUXP15/VAUXN15 */ +#define XSM_AUX00_OFFSET (XSM_IP_OFFSET + 0x240) + /**< ADC out of VAUXP0/VAUXN0 */ +#define XSM_AUX01_OFFSET (XSM_IP_OFFSET + 0x244) + /**< ADC out of VAUXP1/VAUXN1 */ +#define XSM_AUX02_OFFSET (XSM_IP_OFFSET + 0x248) + /**< ADC out of VAUXP2/VAUXN2 */ +#define XSM_AUX03_OFFSET (XSM_IP_OFFSET + 0x24C) + /**< ADC out of VAUXP3/VAUXN3 */ +#define XSM_AUX04_OFFSET (XSM_IP_OFFSET + 0x250) + /**< ADC out of VAUXP4/VAUXN4 */ +#define XSM_AUX05_OFFSET (XSM_IP_OFFSET + 0x254) + /**< ADC out of VAUXP5/VAUXN5 */ +#define XSM_AUX06_OFFSET (XSM_IP_OFFSET + 0x258) + /**< ADC out of VAUXP6/VAUXN6 */ +#define XSM_AUX07_OFFSET (XSM_IP_OFFSET + 0x25C) + /**< ADC out of VAUXP7/VAUXN7 */ +#define XSM_AUX08_OFFSET (XSM_IP_OFFSET + 0x260) + /**< ADC out of VAUXP8/VAUXN8 */ +#define XSM_AUX09_OFFSET (XSM_IP_OFFSET + 0x264) + /**< ADC out of VAUXP9/VAUXN9 */ +#define XSM_AUX10_OFFSET (XSM_IP_OFFSET + 0x268) + /**< ADC out of VAUXP10/VAUXN10 */ +#define XSM_AUX11_OFFSET (XSM_IP_OFFSET + 0x26C) + /**< ADC out of VAUXP11/VAUXN11 */ +#define XSM_AUX12_OFFSET (XSM_IP_OFFSET + 0x270) + /**< ADC out of VAUXP12/VAUXN12 */ +#define XSM_AUX13_OFFSET (XSM_IP_OFFSET + 0x274) + /**< ADC out of VAUXP13/VAUXN13 */ +#define XSM_AUX14_OFFSET (XSM_IP_OFFSET + 0x278) + /**< ADC out of VAUXP14/VAUXN14 */ +#define XSM_AUX15_OFFSET (XSM_IP_OFFSET + 0x27C) + /**< ADC out of VAUXP15/VAUXN15 */ /* * System Monitor/ADC Registers for Maximum/Minimum data captured for the * on chip Temperature/VCCINT/VCCAUX data. */ -#define XSM_MAX_TEMP_OFFSET 0x280 /**< Maximum Temperature Reg */ -#define XSM_MAX_VCCINT_OFFSET 0x284 /**< Maximum VCCINT Register */ -#define XSM_MAX_VCCAUX_OFFSET 0x288 /**< Maximum VCCAUX Register */ -#define XSM_MAX_VBRAM_OFFSET 0x28C /**< Maximum VBRAM Reg, 7 Series/Zynq */ -#define XSM_MIN_TEMP_OFFSET 0x290 /**< Minimum Temperature Reg */ -#define XSM_MIN_VCCINT_OFFSET 0x294 /**< Minimum VCCINT Register */ -#define XSM_MIN_VCCAUX_OFFSET 0x298 /**< Minimum VCCAUX Register */ -#define XSM_MIN_VBRAM_OFFSET 0x29C /**< Maximum VBRAM Reg, 7 Series/Zynq */ -#define XSM_MAX_VCCPINT_OFFSET 0x2A0 /**< Max VCCPINT Register, Zynq */ -#define XSM_MAX_VCCPAUX_OFFSET 0x2A4 /**< Max VCCPAUX Register, Zynq */ -#define XSM_MAX_VCCPDRO_OFFSET 0x2A8 /**< Max VCCPDRO Register, Zynq */ -#define XSM_MIN_VCCPINT_OFFSET 0x2AC /**< Min VCCPINT Register, Zynq */ -#define XSM_MIN_VCCPAUX_OFFSET 0x2B0 /**< Min VCCPAUX Register, Zynq */ -#define XSM_MIN_VCCPDRO_OFFSET 0x2B4 /**< Min VCCPDRO Register, Zynq */ +#define XSM_MAX_TEMP_OFFSET (XSM_IP_OFFSET + 0x280) + /**< Maximum Temperature Reg */ +#define XSM_MAX_VCCINT_OFFSET (XSM_IP_OFFSET + 0x284) + /**< Maximum VCCINT Register */ +#define XSM_MAX_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x288) + /**< Maximum VCCAUX Register */ +#define XSM_MAX_VBRAM_OFFSET (XSM_IP_OFFSET + 0x28C) + /**< Maximum VBRAM Reg, 7 Series/Zynq */ +#define XSM_MIN_TEMP_OFFSET (XSM_IP_OFFSET + 0x290) + /**< Minimum Temperature Reg */ +#define XSM_MIN_VCCINT_OFFSET (XSM_IP_OFFSET + 0x294) + /**< Minimum VCCINT Register */ +#define XSM_MIN_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x298) + /**< Minimum VCCAUX Register */ +#define XSM_MIN_VBRAM_OFFSET (XSM_IP_OFFSET + 0x29C) + /**< Maximum VBRAM Reg, 7 Series/Zynq */ +#define XSM_MAX_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2A0) + /**< Max VCCPINT Register, Zynq */ +#define XSM_MAX_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2A4) + /**< Max VCCPAUX Register, Zynq */ +#define XSM_MAX_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2A8) + /**< Max VCCPDRO Register, Zynq */ +#define XSM_MIN_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2AC) + /**< Min VCCPINT Register, Zynq */ +#define XSM_MIN_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2B0) + /**< Min VCCPAUX Register, Zynq */ +#define XSM_MIN_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2B4) + /**< Min VCCPDRO Register, Zynq */ +#define XSM_MAX_VUSR0_OFFSET (XSM_IP_OFFSET + 0x480) + /**< Maximum VUSER0 Supply Reg */ +#define XSM_MAX_VUSR1_OFFSET (XSM_IP_OFFSET + 0x484) + /**< Maximum VUSER1 Supply Reg */ +#define XSM_MAX_VUSR2_OFFSET (XSM_IP_OFFSET + 0x488) + /**< Maximum VUSER2 Supply Reg */ +#define XSM_MAX_VUSR3_OFFSET (XSM_IP_OFFSET + 0x48C) + /**< Maximum VUSER3 Supply Reg */ +#define XSM_MIN_VUSR0_OFFSET (XSM_IP_OFFSET + 0x4A0) + /**< Minimum VUSER0 Supply Reg */ +#define XSM_MIN_VUSR1_OFFSET (XSM_IP_OFFSET + 0x4A4) + /**< Minimum VUSER1 Supply Reg */ +#define XSM_MIN_VUSR2_OFFSET (XSM_IP_OFFSET + 0x4A8) + /**< Minimum VUSER2 Supply Reg */ +#define XSM_MIN_VUSR3_OFFSET (XSM_IP_OFFSET + 0x4AC) + /**< Minimum VUSER3 Supply Reg */ -#define XSM_FLAG_REG_OFFSET 0x2FC /**< General Status */ + +#define XSM_FLAG_REG_OFFSET (XSM_IP_OFFSET + 0x2FC) /**< General Status */ /* * System Monitor/ADC Configuration Registers */ -#define XSM_CFR0_OFFSET 0x300 /**< Configuration Register 0 */ -#define XSM_CFR1_OFFSET 0x304 /**< Configuration Register 1 */ -#define XSM_CFR2_OFFSET 0x308 /**< Configuration Register 2 */ +#define XSM_CFR0_OFFSET (XSM_IP_OFFSET + 0x300) + /**< Configuration Register 0 */ +#define XSM_CFR1_OFFSET (XSM_IP_OFFSET + 0x304) + /**< Configuration Register 1 */ +#define XSM_CFR2_OFFSET (XSM_IP_OFFSET + 0x308) + /**< Configuration Register 2 */ +#define XSM_CFR3_OFFSET (XSM_IP_OFFSET + 0x30C) + /**< Configuration Register 2 */ /* * System Monitor/ADC Sequence Registers */ -#define XSM_SEQ00_OFFSET 0x320 /**< Seq Reg 00 Adc Channel Selection */ -#define XSM_SEQ01_OFFSET 0x324 /**< Seq Reg 01 Adc Channel Selection */ -#define XSM_SEQ02_OFFSET 0x328 /**< Seq Reg 02 Adc Average Enable */ -#define XSM_SEQ03_OFFSET 0x32C /**< Seq Reg 03 Adc Average Enable */ -#define XSM_SEQ04_OFFSET 0x330 /**< Seq Reg 04 Adc Input Mode Select */ -#define XSM_SEQ05_OFFSET 0x334 /**< Seq Reg 05 Adc Input Mode Select */ -#define XSM_SEQ06_OFFSET 0x338 /**< Seq Reg 06 Adc Acquisition Select */ -#define XSM_SEQ07_OFFSET 0x33C /**< Seq Reg 07 Adc Acquisition Select */ +#define XSM_SEQ00_OFFSET (XSM_IP_OFFSET + 0x320) + /**< Seq Reg 00 Adc Channel Selection */ +#define XSM_SEQ01_OFFSET (XSM_IP_OFFSET + 0x324) + /**< Seq Reg 01 Adc Channel Selection */ +#define XSM_SEQ02_OFFSET (XSM_IP_OFFSET + 0x328) + /**< Seq Reg 02 Adc Average Enable */ +#define XSM_SEQ03_OFFSET (XSM_IP_OFFSET + 0x32C) + /**< Seq Reg 03 Adc Average Enable */ +#define XSM_SEQ04_OFFSET (XSM_IP_OFFSET + 0x330) + /**< Seq Reg 04 Adc Input Mode Select */ +#define XSM_SEQ05_OFFSET (XSM_IP_OFFSET + 0x334) + /**< Seq Reg 05 Adc Input Mode Select */ +#define XSM_SEQ06_OFFSET (XSM_IP_OFFSET + 0x338) + /**< Seq Reg 06 Adc Acquisition Select */ +#define XSM_SEQ07_OFFSET (XSM_IP_OFFSET + 0x33C) + /**< Seq Reg 07 Adc Acquisition Select */ +#define XSM_SEQ08_OFFSET (XSM_IP_OFFSET + 0x318) + /**< Seq Reg 08 Adc Channel Selection */ +#define XSM_SEQ09_OFFSET (XSM_IP_OFFSET + 0x31C) + /**< Seq Reg 09 Adc Average Enable */ /* * System Monitor/ADC Alarm Threshold/Limit Registers (ATR) */ -#define XSM_ATR_TEMP_UPPER_OFFSET 0x340 /**< Temp Upper Alarm Register */ -#define XSM_ATR_VCCINT_UPPER_OFFSET 0x344 /**< VCCINT Upper Alarm Reg */ -#define XSM_ATR_VCCAUX_UPPER_OFFSET 0x348 /**< VCCAUX Upper Alarm Reg */ -#define XSM_ATR_OT_UPPER_OFFSET 0x34C /**< Over Temp Upper Alarm Reg */ -#define XSM_ATR_TEMP_LOWER_OFFSET 0x350 /**< Temp Lower Alarm Register */ -#define XSM_ATR_VCCINT_LOWER_OFFSET 0x354 /**< VCCINT Lower Alarm Reg */ -#define XSM_ATR_VCCAUX_LOWER_OFFSET 0x358 /**< VCCAUX Lower Alarm Reg */ -#define XSM_ATR_OT_LOWER_OFFSET 0x35C /**< Over Temp Lower Alarm Reg */ -#define XSM_ATR_VBRAM_UPPER_OFFSET 0x360 /**< VBBAM Upper Alarm,7 Series */ -#define XSM_ATR_VCCPINT_UPPER_OFFSET 0x364 /**< VCCPINT Upper Alarm, Zynq */ -#define XSM_ATR_VCCPAUX_UPPER_OFFSET 0x368 /**< VCCPAUX Upper Alarm, Zynq */ -#define XSM_ATR_VCCPDRO_UPPER_OFFSET 0x36C /**< VCCPDRO Upper Alarm, Zynq */ -#define XSM_ATR_VBRAM_LOWER_OFFSET 0x370 /**< VRBAM Lower Alarm, 7 Series*/ -#define XSM_ATR_VCCPINT_LOWER_OFFSET 0x374 /**< VCCPINT Lower Alarm, Zynq */ -#define XSM_ATR_VCCPAUX_LOWER_OFFSET 0x378 /**< VCCPAUX Lower Alarm, Zynq */ -#define XSM_ATR_VCCPDRO_LOWER_OFFSET 0x37C /**< VCCPDRO Lower Alarm, Zynq */ - +#define XSM_ATR_TEMP_UPPER_OFFSET (XSM_IP_OFFSET + 0x340) + /**< Temp Upper Alarm Register */ +#define XSM_ATR_VCCINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x344) + /**< VCCINT Upper Alarm Reg */ +#define XSM_ATR_VCCAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x348) + /**< VCCAUX Upper Alarm Reg */ +#define XSM_ATR_OT_UPPER_OFFSET (XSM_IP_OFFSET + 0x34C) + /**< Over Temp Upper Alarm Reg */ +#define XSM_ATR_TEMP_LOWER_OFFSET (XSM_IP_OFFSET + 0x350) + /**< Temp Lower Alarm Register */ +#define XSM_ATR_VCCINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x354) + /**< VCCINT Lower Alarm Reg */ +#define XSM_ATR_VCCAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x358) + /**< VCCAUX Lower Alarm Reg */ +#define XSM_ATR_OT_LOWER_OFFSET (XSM_IP_OFFSET + 0x35C) + /**< Over Temp Lower Alarm Reg */ +#define XSM_ATR_VBRAM_UPPER_OFFSET (XSM_IP_OFFSET + 0x360) + /**< VBBAM Upper Alarm,7 Series */ +#define XSM_ATR_VCCPINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x364) + /**< VCCPINT Upper Alarm, Zynq */ +#define XSM_ATR_VCCPAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x368) + /**< VCCPAUX Upper Alarm, Zynq */ +#define XSM_ATR_VCCPDRO_UPPER_OFFSET (XSM_IP_OFFSET + 0x36C) + /**< VCCPDRO Upper Alarm, Zynq */ +#define XSM_ATR_VBRAM_LOWER_OFFSET (XSM_IP_OFFSET + 0x370) + /**< VRBAM Lower Alarm, 7 Series*/ +#define XSM_ATR_VCCPINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x374) + /**< VCCPINT Lower Alarm, Zynq */ +#define XSM_ATR_VCCPAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x378) + /**< VCCPAUX Lower Alarm, Zynq */ +#define XSM_ATR_VCCPDRO_LOWER_OFFSET (XSM_IP_OFFSET + 0x37C) + /**< VCCPDRO Lower Alarm, Zynq */ +#define XSM_ATR_VUSR0_UPPER_OFFSET (XSM_IP_OFFSET + 0x380) + /**< VUSER0 Upper Alarm Reg */ +#define XSM_ATR_VUSR1_UPPER_OFFSET (XSM_IP_OFFSET + 0x384) + /**< VUSER1 Upper Alarm Reg */ +#define XSM_ATR_VUSR2_UPPER_OFFSET (XSM_IP_OFFSET + 0x388) + /**< VUSER2 Upper Alarm Reg */ +#define XSM_ATR_VUSR3_UPPER_OFFSET (XSM_IP_OFFSET + 0x38C) + /**< VUSER3 Upper Alarm Reg */ +#define XSM_ATR_VUSR0_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A0) + /**< VUSER0 Lower Alarm Reg */ +#define XSM_ATR_VUSR1_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A4) + /**< VUSER1 Lower Alarm Reg */ +#define XSM_ATR_VUSR2_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A8) + /**< VUSER2 Lower Alarm Reg */ +#define XSM_ATR_VUSR3_LOWER_OFFSET (XSM_IP_OFFSET + 0x3AC) + /**< VUSER3 Lower Alarm Reg */ /*@}*/ @@ -226,8 +360,12 @@ extern "C" { * @name System Monitor/ADC Alarm Output Register (AOR) mask(s) * @{ */ -#define XSM_AOR_ALARM_ALL_MASK 0x000001FF /**< Mask for all Alarms */ -#define XSM_AOR_ALL_MASK 0x00000100 /**< ALM7 - All Alarms */ +#define XSM_AOR_ALARM_ALL_MASK 0x00001FFF /**< Mask for all Alarms */ +#define XSM_AOR_VUSR3_MASK 0x00001000 /**< ALM11 - VUSER3 Alarm Mask */ +#define XSM_AOR_VUSR2_MASK 0x00000800 /**< ALM10 - VUSER2 Alarm Mask */ +#define XSM_AOR_VUSR1_MASK 0x00000400 /**< ALM9 - VUSER1 Alarm Mask */ +#define XSM_AOR_VUSR0_MASK 0x00000200 /**< ALM8 - VUSER0 Alarm Mask */ +#define XSM_AOR_ALL_MASK 0x00000100 /**< ALM7 - All Alarms 0 to 6 */ #define XSM_AOR_VCCPDRO_MASK 0x00000080 /**< ALM6 - VCCPDRO Mask, Zynq */ #define XSM_AOR_VCCPAUX_MASK 0x00000040 /**< ALM5 - VCCPAUX Mask, Zynq */ #define XSM_AOR_VCCPINT_MASK 0x00000020 /**< ALM4 - VCCPINT Mask, Zynq */ @@ -299,7 +437,12 @@ extern "C" { #define XSM_IPIXR_VCCINT_MASK 0x00000004 /**< Alarm 1 - VCCINT */ #define XSM_IPIXR_TEMP_MASK 0x00000002 /**< Alarm 0 - Temp ACTIVE */ #define XSM_IPIXR_OT_MASK 0x00000001 /**< Over Temperature ACTIVE */ -#define XSM_IPIXR_ALL_MASK 0x000003FF /**< Mask of all interrupts */ +#define XSM_IPIXR_VUSR0_MASK 0x00004000 /**< Alarm 8 VUSER0 */ +#define XSM_IPIXR_VUSR1_MASK 0x00008000 /**< Alarm 9 VUSER1 */ +#define XSM_IPIXR_VUSR2_MASK 0x00010000 /**< Alarm 10 VUSER2 */ +#define XSM_IPIXR_VUSR3_MASK 0x00020000 /**< Alarm 11 VUSER3 */ +#define XSM_IPIXR_ALL_MASK 0x0003C7FF /**< Mask of all interrupts */ + /*@}*/ @@ -322,13 +465,13 @@ extern "C" { #define XSM_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */ #define XSM_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */ #define XSM_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */ -#define XSM_CFR0_AVG_SHIFT 12 /**< Shift for the Averaging bits */ +#define XSM_CFR0_AVG_SHIFT 12 /**< Shift for the Averaging bits */ #define XSM_CFR0_MUX_MASK 0x0800 /**< External Mux Mask Enable * - 7 Series and Zynq */ #define XSM_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */ #define XSM_CFR0_EC_MASK 0x0200 /**< Event driven/Continuous mode */ #define XSM_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */ -#define XSM_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */ +#define XSM_CFR0_CHANNEL_MASK 0x003F /**< Channel number bit Mask */ /*@}*/ @@ -385,6 +528,40 @@ extern "C" { /*@}*/ +/** + * @name Configuration Register 3 (CFR3) mask(s) + * @{ + */ + +#define XSM_CFR3_ALM_ALL_MASK 0x000F /**< Mask for all alarms */ +#define XSM_CFR3_ALM_VUSR3_MASK 0x0008 /**< VUSER 0 Supply */ +#define XSM_CFR3_ALM_VUSR2_MASK 0x0004 /**< VUSER 1 Supply */ +#define XSM_CFR3_ALM_VUSR1_MASK 0x0002 /**< VUSER 2 Supply */ +#define XSM_CFR3_ALM_VUSR0_MASK 0x0001 /**< VUSER 3 Supply */ + +/* Mask for all Alarms in CFR1 and CFR3 */ +#define XSM_CFR_ALM_ALL_MASK 0xF0F0F + +/*@}*/ + +/** + * @name Alarm masks for channels in Configuration registers 1 and 3 + * @{ + */ +#define XSM_CFR_ALM_VUSR3_MASK 0x00080000 /**< VUSER 0 Supply */ +#define XSM_CFR_ALM_VUSR2_MASK 0x00040000 /**< VUSER 1 Supply */ +#define XSM_CFR_ALM_VUSR1_MASK 0x00020000 /**< VUSER 2 Supply */ +#define XSM_CFR_ALM_VUSR0_MASK 0x00010000 /**< VUSER 3 Supply */ +#define XSM_CFR_ALM_VCCPDRO_MASK 0x0800 /**< Alarm 6 - VCCPDRO, Zynq */ +#define XSM_CFR_ALM_VCCPAUX_MASK 0x0400 /**< Alarm 5 - VCCPAUX, Zynq */ +#define XSM_CFR_ALM_VCCPINT_MASK 0x0200 /**< Alarm 4 - VCCPINT, Zynq */ +#define XSM_CFR_ALM_VBRAM_MASK 0x0100 /**< Alarm 3 - VBRAM Enable + * 7 Series and Zynq */ +#define XSM_CFR_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */ +#define XSM_CFR_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */ +#define XSM_CFR_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */ +#define XSM_CFR_OT_MASK 0x0001 /**< Over Temperature Enable */ + /** * @name Sequence Register (SEQ) Bit Definitions * @{ @@ -416,6 +593,10 @@ extern "C" { #define XSM_SEQ_CH_AUX13 0x20000000 /**< 14th Aux Channel */ #define XSM_SEQ_CH_AUX14 0x40000000 /**< 15th Aux Channel */ #define XSM_SEQ_CH_AUX15 0x80000000 /**< 16th Aux Channel */ +#define XSM_SEQ_CH_VUSR0 0x100000000 /**< VUSER0 Channel */ +#define XSM_SEQ_CH_VUSR1 0x200000000 /**< VUSER1 Channel */ +#define XSM_SEQ_CH_VUSR2 0x400000000 /**< VUSER2 Channel */ +#define XSM_SEQ_CH_VUSR3 0x800000000 /**< VUSER3 Channel */ #define XSM_SEQ00_CH_VALID_MASK 0x7FE1 /**< Mask for the valid channels */ #define XSM_SEQ01_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ @@ -429,8 +610,13 @@ extern "C" { #define XSM_SEQ06_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */ #define XSM_SEQ07_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ +#define XSM_SEQ08_CH_VALID_MASK 0x000F /**< Mask for the valid channels */ +#define XSM_SEQ09_CH_VALID_MASK 0x000F /**< Mask for the valid channels */ + #define XSM_SEQ_CH_AUX_SHIFT 16 /**< Shift for the Aux Channel */ +#define XSM_SEQ_CH_VUSR_SHIFT 32 /**< Shift for the Aux Channel */ + /*@}*/ /**