diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_hw.h b/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_hw.h
deleted file mode 100644
index 8bee7d87..00000000
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_hw.h
+++ /dev/null
@@ -1,504 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xnandps8_hw.h
-*
-* This file contains identifiers and low-level macros/functions for the Arasan
-* NAND flash controller driver.
-*
-* See xnandps8.h for more information.
-*
-* @note		None
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date        Changes
-* ----- ----   ----------  -----------------------------------------------
-* 1.0   nm     05/06/2014  First Release
-* 2.0   sb     11/04/2014  Changed XNANDPS8_ECC_SLC_MLC_MASK to
-*			   XNANDPS8_ECC_HAMMING_BCH_MASK.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XNANDPS8_HW_H		/* prevent circular inclusions */
-#define XNANDPS8_HW_H		/* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/************************** Register Offset Definitions **********************/
-
-#define XNANDPS8_PKT_OFFSET		0x00U	/**< Packet Register */
-#define XNANDPS8_MEM_ADDR1_OFFSET	0x04U	/**< Memory Address
-						  Register 1 */
-#define XNANDPS8_MEM_ADDR2_OFFSET	0x08U	/**< Memory Address
-						  Register 2 */
-#define XNANDPS8_CMD_OFFSET		0x0CU	/**< Command Register */
-#define XNANDPS8_PROG_OFFSET		0x10U	/**< Program Register */
-#define XNANDPS8_INTR_STS_EN_OFFSET	0x14U	/**< Interrupt Status
-						     Enable Register */
-#define XNANDPS8_INTR_SIG_EN_OFFSET	0x18U	/**< Interrupt Signal
-						     Enable Register */
-#define XNANDPS8_INTR_STS_OFFSET	0x1CU	/**< Interrupt Status
-						  Register */
-#define XNANDPS8_READY_BUSY_OFFSET	0x20U	/**< Ready/Busy status
-						  Register */
-#define XNANDPS8_FLASH_STS_OFFSET	0x28U	/**< Flash Status Register */
-#define XNANDPS8_TIMING_OFFSET		0x2CU	/**< Timing Register */
-#define XNANDPS8_BUF_DATA_PORT_OFFSET	0x30U	/**< Buffer Data Port
-						  Register */
-#define XNANDPS8_ECC_OFFSET		0x34U	/**< ECC Register */
-#define XNANDPS8_ECC_ERR_CNT_OFFSET	0x38U	/**< ECC Error Count
-						  Register */
-#define XNANDPS8_ECC_SPR_CMD_OFFSET	0x3CU	/**< ECC Spare Command
-						     Register */
-#define XNANDPS8_ECC_CNT_1BIT_OFFSET	0x40U	/**< Error Count 1bit
-						  Register */
-#define XNANDPS8_ECC_CNT_2BIT_OFFSET	0x44U	/**< Error Count 2bit
-						  Register */
-#define XNANDPS8_ECC_CNT_3BIT_OFFSET	0x48U	/**< Error Count 3bit
-						  Register */
-#define XNANDPS8_ECC_CNT_4BIT_OFFSET	0x4CU	/**< Error Count 4bit
-						  Register */
-#define XNANDPS8_CPU_REL_OFFSET		0x58U	/**< CPU Release Register */
-#define XNANDPS8_ECC_CNT_5BIT_OFFSET	0x5CU	/**< Error Count 5bit
-						  Register */
-#define XNANDPS8_ECC_CNT_6BIT_OFFSET	0x60U	/**< Error Count 6bit
-						  Register */
-#define XNANDPS8_ECC_CNT_7BIT_OFFSET	0x64U	/**< Error Count 7bit
-						  Register */
-#define XNANDPS8_ECC_CNT_8BIT_OFFSET	0x68U	/**< Error Count 8bit
-						  Register */
-#define XNANDPS8_DATA_INTF_OFFSET	0x6CU	/**< Data Interface Register */
-#define XNANDPS8_DMA_SYS_ADDR0_OFFSET	0x50U	/**< DMA System Address 0
-						  Register */
-#define XNANDPS8_DMA_SYS_ADDR1_OFFSET	0x24U	/**< DMA System Address 1
-						  Register */
-#define XNANDPS8_DMA_BUF_BND_OFFSET	0x54U	/**< DMA Buffer Boundary
-						  Register */
-#define XNANDPS8_SLV_DMA_CONF_OFFSET	0x80U	/**< Slave DMA Configuration
-						  Register */
-
-/** @name Packet Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_PKT_PKT_SIZE_MASK		0x000007FFU /**< Packet Size */
-#define XNANDPS8_PKT_PKT_CNT_MASK		0x00FFF000U /**< Packet Count*/
-#define XNANDPS8_PKT_PKT_CNT_SHIFT		12U /**< Packet Count Shift */
-/* @} */
-
-/** @name Memory Address Register 1 bit definitions and masks
- *  @{
- */
-#define XNANDPS8_MEM_ADDR1_COL_ADDR_MASK	0x0000FFFFU /**< Column Address
-							     Mask */
-#define XNANDPS8_MEM_ADDR1_PG_ADDR_MASK		0xFFFF0000U /**< Page, Block
-							     Address Mask */
-#define XNANDPS8_MEM_ADDR1_PG_ADDR_SHIFT	16U /**< Page Shift */
-/* @} */
-
-/** @name Memory Address Register 2 bit definitions and masks
- *  @{
- */
-#define XNANDPS8_MEM_ADDR2_MEM_ADDR_MASK	0x000000FFU /**< Memory Address
-								*/
-#define XNANDPS8_MEM_ADDR2_BUS_WIDTH_MASK	0x01000000U /**< Bus Width */
-#define XNANDPS8_MEM_ADDR2_NFC_BCH_MODE_MASK	0x0E000000U /**< BCH Mode
-							     Value */
-#define XNANDPS8_MEM_ADDR2_MODE_MASK		0x30000000U /**< Flash
-							     Connection Mode */
-#define XNANDPS8_MEM_ADDR2_CHIP_SEL_MASK	0xC0000000U /**< Chip Select */
-#define XNANDPS8_MEM_ADDR2_CHIP_SEL_SHIFT	30U	/**< Chip select
-							shift */
-#define XNANDPS8_MEM_ADDR2_BUS_WIDTH_SHIFT	24U	/**< Bus width shift */
-#define XNANDPS8_MEM_ADDR2_NFC_BCH_MODE_SHIFT	25U
-/* @} */
-
-/** @name Command Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_CMD_CMD1_MASK			0x000000FFU /**< 1st Cycle
-							     Command */
-#define XNANDPS8_CMD_CMD2_MASK			0x0000FF00U /**< 2nd Cycle
-							     Command */
-#define XNANDPS8_CMD_PG_SIZE_MASK		0x03800000U /**< Page Size */
-#define XNANDPS8_CMD_DMA_EN_MASK		0x0C000000U /**< DMA Enable
-							     Mode */
-#define XNANDPS8_CMD_ADDR_CYCLES_MASK		0x70000000U /**< Number of
-							     Address Cycles */
-#define XNANDPS8_CMD_ECC_ON_MASK		0x80000000U /**< ECC ON/OFF */
-#define XNANDPS8_CMD_CMD2_SHIFT			8U /**< 2nd Cycle Command
-						    Shift */
-#define XNANDPS8_CMD_PG_SIZE_SHIFT		23U /**< Page Size Shift */
-#define XNANDPS8_CMD_DMA_EN_SHIFT		26U /**< DMA Enable Shift */
-#define XNANDPS8_CMD_ADDR_CYCLES_SHIFT		28U /**< Number of Address
-						     Cycles Shift */
-#define XNANDPS8_CMD_ECC_ON_SHIFT		31U /**< ECC ON/OFF */
-/* @} */
-
-/** @name Program Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_PROG_RD_MASK			0x00000001U /**< Read */
-#define XNANDPS8_PROG_MUL_DIE_MASK		0x00000002U /**< Multi Die */
-#define XNANDPS8_PROG_BLK_ERASE_MASK		0x00000004U /**< Block Erase */
-#define XNANDPS8_PROG_RD_STS_MASK		0x00000008U /**< Read Status */
-#define XNANDPS8_PROG_PG_PROG_MASK		0x00000010U /**< Page Program */
-#define XNANDPS8_PROG_MUL_DIE_RD_MASK		0x00000020U /**< Multi Die Rd */
-#define XNANDPS8_PROG_RD_ID_MASK		0x00000040U /**< Read ID */
-#define XNANDPS8_PROG_RD_PRM_PG_MASK		0x00000080U /**< Read Param
-							     Page */
-#define XNANDPS8_PROG_RST_MASK			0x00000100U /**< Reset */
-#define XNANDPS8_PROG_GET_FEATURES_MASK		0x00000200U /**< Get Features */
-#define XNANDPS8_PROG_SET_FEATURES_MASK		0x00000400U /**< Set Features */
-#define XNANDPS8_PROG_RD_UNQ_ID_MASK		0x00000800U /**< Read Unique
-							     ID */
-#define XNANDPS8_PROG_RD_STS_ENH_MASK		0x00001000U /**< Read Status
-							     Enhanced */
-#define XNANDPS8_PROG_RD_INTRLVD_MASK		0x00002000U /**< Read
-							     Interleaved */
-#define XNANDPS8_PROG_CHNG_RD_COL_ENH_MASK	0x00004000U /**< Change Read
-								Column
-								Enhanced */
-#define XNANDPS8_PROG_COPY_BACK_INTRLVD_MASK	0x00008000U /**< Copy Back
-								Interleaved */
-#define XNANDPS8_PROG_RD_CACHE_START_MASK	0x00010000U /**< Read Cache
-							     Start */
-#define XNANDPS8_PROG_RD_CACHE_SEQ_MASK		0x00020000U /**< Read Cache
-							     Sequential */
-#define XNANDPS8_PROG_RD_CACHE_RAND_MASK	0x00040000U /**< Read Cache
-								Random */
-#define XNANDPS8_PROG_RD_CACHE_END_MASK		0x00080000U /**< Read Cache
-							     End */
-#define XNANDPS8_PROG_SMALL_DATA_MOVE_MASK	0x00100000U /**< Small Data
-							     Move */
-#define XNANDPS8_PROG_CHNG_ROW_ADDR_MASK	0x00200000U /**< Change Row
-								Address */
-#define XNANDPS8_PROG_CHNG_ROW_ADDR_END_MASK	0x00400000U /**< Change Row
-								Address End */
-#define XNANDPS8_PROG_RST_LUN_MASK		0x00800000U /**< Reset LUN */
-#define XNANDPS8_PROG_PGM_PG_CLR_MASK		0x01000000U /**< Enhanced
-							     Program Page
-							     Register Clear */
-#define XNANDPS8_PROG_VOL_SEL_MASK		0x02000000U /**< Volume Select */
-#define XNANDPS8_PROG_ODT_CONF_MASK		0x04000000U /**< ODT Configure */
-/* @} */
-
-/** @name Interrupt Status Enable Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
-								     Write Ready
-								     Status
-								     Enable */
-#define XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
-								     Read Ready
-								     Status
-								     Enable */
-#define XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
-								     Complete
-								     Status
-								     Enable */
-#define XNANDPS8_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
-								     Bit Error
-								     Status
-								     Enable */
-#define XNANDPS8_INTR_STS_EN_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single
-								     Bit Error
-								     Status
-								     Enable,
-								     BCH Detect
-								     Error
-								     Status
-								     Enable */
-#define XNANDPS8_INTR_STS_EN_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA
-								     Status
-								     Enable */
-#define XNANDPS8_INTR_STS_EN_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error
-								     AHB Status
-								     Enable */
-/* @} */
-
-/** @name Interrupt Signal Enable Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
-								     Write Ready
-								     Signal
-								     Enable */
-#define XNANDPS8_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
-								     Read Ready
-								     Signal
-								     Enable */
-#define XNANDPS8_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
-								     Complete
-								     Signal
-								     Enable */
-#define XNANDPS8_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
-								     Bit Error
-								     Signal
-								     Enable */
-#define XNANDPS8_INTR_SIG_EN_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single
-								     Bit Error
-								     Signal
-								     Enable,
-								     BCH Detect
-								     Error
-								     Signal
-								     Enable */
-#define XNANDPS8_INTR_SIG_EN_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA
-								     Signal
-								     Enable */
-#define XNANDPS8_INTR_SIG_EN_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error
-								     AHB Signal
-								     Enable */
-/* @} */
-
-/** @name Interrupt Status Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
-								     Write
-								     Ready */
-#define XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
-								     Read
-								     Ready */
-#define XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
-								     Complete */
-#define XNANDPS8_INTR_STS_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
-								    Bit Error */
-#define XNANDPS8_INTR_STS_ERR_INTR_STS_EN_MASK		0x00000010U /**< Single
-								     Bit Error,
-								     BCH Detect
-								     Error */
-#define XNANDPS8_INTR_STS_DMA_INT_STS_EN_MASK		0x00000040U /**< DMA
-								     Interrupt
-								     */
-#define XNANDPS8_INTR_STS_ERR_AHB_STS_EN_MASK		0x00000080U /**< Error
-								     AHB */
-/* @} */
-
-/** @name Interrupt bit definitions and masks
- *  @{
- */
-#define XNANDPS8_INTR_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer Write
-								Ready Status
-								Enable */
-#define XNANDPS8_INTR_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer Read
-								Ready Status
-								Enable */
-#define XNANDPS8_INTR_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
-								Complete Status
-								Enable */
-#define XNANDPS8_INTR_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi Bit Error
-								Status Enable */
-#define XNANDPS8_INTR_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single Bit Error
-								Status Enable,
-								BCH Detect Error
-								Status Enable */
-#define XNANDPS8_INTR_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA Status
-								Enable */
-#define XNANDPS8_INTR_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error AHB Status
-								Enable */
-/* @} */
-
-/** @name ID2 Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_ID2_DEVICE_ID2_MASK		0x000000FFU /**< MSB Device ID */
-/* @} */
-
-/** @name Flash Status Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_FLASH_STS_FLASH_STS_MASK	0x0000FFFFU /**< Flash Status
-							     Value */
-/* @} */
-
-/** @name Timing Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_TIMING_TCCS_TIME_MASK		0x00000003U /**< Change column
-							     setup time */
-#define XNANDPS8_TIMING_SLOW_FAST_TCAD_MASK	0x00000004U /**< Slow/Fast device
-							     */
-#define XNANDPS8_TIMING_DQS_BUFF_SEL_MASK	0x00000078U /**< Write/Read data
-							     transaction value
-							     */
-#define XNANDPS8_TIMING_TADL_TIME_MASK		0x00007F80U /**< Address latch
-							     enable to Data
-							     loading time */
-/* @} */
-
-/** @name ECC Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_ECC_ADDR_MASK			0x0000FFFFU /**< ECC address */
-#define XNANDPS8_ECC_SIZE_MASK			0x01FF0000U /**< ECC size */
-#define XNANDPS8_ECC_HAMMING_BCH_MASK		0x02000000U /**< Hamming/BCH
-							     support */
-/* @} */
-
-/** @name ECC Error Count Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK	0x000000FFU /**< Packet
-								     bound error
-								     count */
-#define XNANDPS8_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK	0x0000FF00U /**< Page
-								     bound error
-								     count */
-/* @} */
-
-/** @name ECC Spare Command Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_ECC_SPR_CMD_SPR_CMD_MASK		0x000000FFU /**< ECC
-								     spare
-								     command */
-#define XNANDPS8_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK	0x70000000U /**< Number
-								     of ECC/
-								     spare
-								     address
-								     cycles */
-/* @} */
-
-/** @name Data Interface Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_DATA_INTF_SDR_MASK		0x00000007U /**< SDR mode */
-#define XNANDPS8_DATA_INTF_NVDDR_MASK		0x00000038U /**< NVDDR mode */
-#define XNANDPS8_DATA_INTF_NVDDR2_MASK		0x000001C0U /**< NVDDR2 mode */
-#define XNANDPS8_DATA_INTF_DATA_INTF_MASK	0x00000600U /**< Data
-							     Interface */
-#define XNANDPS8_DATA_INTF_NVDDR_SHIFT		3U /**< NVDDR mode shift */
-#define XNANDPS8_DATA_INTF_DATA_INTF_SHIFT	9U /**< Data Interface Shift */
-/* @} */
-
-/** @name DMA Buffer Boundary Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_DMA_BUF_BND_BND_MASK		0x00000007U /**< DMA buffer
-							     boundary */
-#define XNANDPS8_DMA_BUF_BND_4K			0x0U
-#define XNANDPS8_DMA_BUF_BND_8K			0x1U
-#define XNANDPS8_DMA_BUF_BND_16K		0x2U
-#define XNANDPS8_DMA_BUF_BND_32K		0x3U
-#define XNANDPS8_DMA_BUF_BND_64K		0x4U
-#define XNANDPS8_DMA_BUF_BND_128K		0x5U
-#define XNANDPS8_DMA_BUF_BND_256K		0x6U
-#define XNANDPS8_DMA_BUF_BND_512K		0x7U
-/* @} */
-
-/** @name Slave DMA Configuration Register bit definitions and masks
- *  @{
- */
-#define XNANDPS8_SLV_DMA_CONF_SDMA_TX_RX_MASK		0x00000001U /**< Slave
-								     DMA
-								     Transfer
-								     Direction
-								     */
-#define XNANDPS8_SLV_DMA_CONF_DMA_TRANS_CNT_MASK	0x001FFFFEU /**< Slave
-								     DMA
-								     Transfer
-								     Count */
-#define XNANDPS8_SLV_DMA_CONF_DMA_BURST_SIZE_MASK	0x00E00000U /**< Slave
-								     DMA
-								     Burst
-								     Size */
-#define XNANDPS8_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK	0x0F000000U /**< DMA
-								     Timeout
-								     Counter
-								     Value */
-#define XNANDPS8_SLV_DMA_CONF_SDMA_EN_MASK		0x10000000U /**< Slave
-								     DMA
-								     Enable */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param	BaseAddress is the base address of controller registers.
-* @param	RegOffset is the register offset to be read.
-*
-* @return	The 32-bit value of the register.
-*
-* @note		C-style signature:
-*		u32 XNandPs8_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XNandPs8_ReadReg(BaseAddress, RegOffset)			\
-			Xil_In32((BaseAddress) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param	BaseAddress is the the base address of controller registers.
-* @param	RegOffset is the register offset to be written.
-* @param	Data is the the 32-bit value to write to the register.
-*
-* @return	None.
-*
-* @note		C-style signature:
-*		void XNandPs8_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-******************************************************************************/
-#define XNandPs8_WriteReg(BaseAddress, RegOffset, Data)			\
-			Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XNANDPS8_HW_H end of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/data/nandps8.mdd b/XilinxProcessorIPLib/drivers/nandpsu/data/nandpsu.mdd
similarity index 92%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/data/nandps8.mdd
rename to XilinxProcessorIPLib/drivers/nandpsu/data/nandpsu.mdd
index ae927b4c..26f4470a 100755
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/data/nandps8.mdd
+++ b/XilinxProcessorIPLib/drivers/nandpsu/data/nandpsu.mdd
@@ -31,12 +31,12 @@
 ###############################################################################
 OPTION psf_version = 2.1;
 
-BEGIN driver nandps8
+BEGIN driver nandpsu
 
-  OPTION supported_peripherals = (ps8_nand pss_nand);
+  OPTION supported_peripherals = (ps8_nand pss_nand psu_nand);
   OPTION driver_state = ACTIVE;
   OPTION copyfiles = all;
-   OPTION VERSION = 2.0;
-  OPTION NAME = nandps8;
+   OPTION VERSION = 1.0;
+  OPTION NAME = nandpsu;
 
 END driver
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/data/nandps8.tcl b/XilinxProcessorIPLib/drivers/nandpsu/data/nandpsu.tcl
similarity index 92%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/data/nandps8.tcl
rename to XilinxProcessorIPLib/drivers/nandpsu/data/nandpsu.tcl
index 21e205af..ccde5981 100755
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/data/nandps8.tcl
+++ b/XilinxProcessorIPLib/drivers/nandpsu/data/nandpsu.tcl
@@ -42,9 +42,9 @@
 #uses "xillib.tcl"
 
 proc generate {drv_handle} {
-    ::hsi::utils::define_zynq_include_file $drv_handle "xparameters.h" "XNandPs8" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
+    ::hsi::utils::define_zynq_include_file $drv_handle "xparameters.h" "XNandPsu" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
 
-    ::hsi::utils::define_zynq_config_file $drv_handle "xnandps_g.c" "XNandPs8" "DEVICE_ID" "C_S_AXI_BASEADDR"
+    ::hsi::utils::define_zynq_config_file $drv_handle "xnandps_g.c" "XNandPsu" "DEVICE_ID" "C_S_AXI_BASEADDR"
 
-    ::hsi::utils::define_zynq_canonical_xpars $drv_handle "xparameters.h" "XNandPs8" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
+    ::hsi::utils::define_zynq_canonical_xpars $drv_handle "xparameters.h" "XNandPsu" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
 }
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/examples/Makefile b/XilinxProcessorIPLib/drivers/nandpsu/examples/Makefile
similarity index 100%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/examples/Makefile
rename to XilinxProcessorIPLib/drivers/nandpsu/examples/Makefile
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/examples/xnandps8_example.c b/XilinxProcessorIPLib/drivers/nandpsu/examples/xnandpsu_example.c
similarity index 93%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/examples/xnandps8_example.c
rename to XilinxProcessorIPLib/drivers/nandpsu/examples/xnandpsu_example.c
index 6149ceac..a8cc3107 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/examples/xnandps8_example.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/examples/xnandpsu_example.c
@@ -43,9 +43,9 @@
 
 /******************************************************************************
 *
-* @file xnandps8_example.c
+* @file xnandpsu_example.c
 *
-* This file contains a design example using the NAND driver (XNandPs8).
+* This file contains a design example using the NAND driver (XNandPsu).
 * This example tests the erase, read and write features of the controller.
 * The flash is erased and written. The data is read back and compared
 * with the data written for correctness.
@@ -70,7 +70,7 @@
 #include <xil_types.h>
 #include <xil_printf.h>
 #include <xparameters.h>
-#include "xnandps8.h"
+#include "xnandpsu.h"
 
 /************************** Constant Definitions *****************************/
 /*
@@ -92,8 +92,8 @@ s32 NandReadWriteExample(u16 NandDeviceId);
 
 /************************** Variable Definitions *****************************/
 
-XNandPs8 NandInstance;			/* XNand Instance */
-XNandPs8 *NandInstPtr = &NandInstance;
+XNandPsu NandInstance;			/* XNand Instance */
+XNandPsu *NandInstPtr = &NandInstance;
 
 /*
  * Buffers used during read and write transactions.
@@ -165,12 +165,12 @@ Out:
 s32 NandReadWriteExample(u16 NandDeviceId)
 {
 	s32 Status = XST_FAILURE;
-	XNandPs8_Config *Config;
+	XNandPsu_Config *Config;
 	u32 Index;
 	u64 Offset;
 	u32 Length;
 
-	Config = XNandPs8_LookupConfig(NandDeviceId);
+	Config = XNandPsu_LookupConfig(NandDeviceId);
 	if (Config == NULL) {
 		Status = XST_FAILURE;
 		goto Out;
@@ -178,13 +178,13 @@ s32 NandReadWriteExample(u16 NandDeviceId)
 	/*
 	 * Initialize the flash driver.
 	 */
-	Status = XNandPs8_CfgInitialize(NandInstPtr, Config,
+	Status = XNandPsu_CfgInitialize(NandInstPtr, Config,
 			Config->BaseAddress);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
 
-	XNandPs8_EnableDmaMode(NandInstPtr);
+	XNandPsu_EnableDmaMode(NandInstPtr);
 
 	Offset = (u64)(TEST_PAGE_START * NandInstPtr->Geometry.BytesPerPage);
 	Length = TEST_BUF_SIZE;
@@ -198,14 +198,14 @@ s32 NandReadWriteExample(u16 NandDeviceId)
 	/*
 	 * Erase the flash
 	 */
-	Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
+	Status = XNandPsu_Erase(NandInstPtr, (u64)Offset, (u64)Length);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
 	/*
 	 * Write to flash
 	 */
-	Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
+	Status = XNandPsu_Write(NandInstPtr, (u64)Offset, (u64)Length,
 						&WriteBuffer[0]);
 	if (Status != XST_SUCCESS) {
 		goto Out;
@@ -213,7 +213,7 @@ s32 NandReadWriteExample(u16 NandDeviceId)
 	/*
 	 * Read the flash after writing
 	 */
-	Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
+	Status = XNandPsu_Read(NandInstPtr, (u64)Offset, (u64)Length,
 						&ReadBuffer[0]);
 	if (Status != XST_SUCCESS) {
 		goto Out;
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/README.txt b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/README.txt
similarity index 90%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/README.txt
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/README.txt
index f4b865be..8f58992e 100755
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/README.txt
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/README.txt
@@ -1,4 +1,4 @@
-NandPs8 Integration test
+NandPsu Integration test
 
 - On R5 processors, you may get compilation error for bsp stating "undefined reference to `end'"
   Add end = .;  at the end of the linker script to remove this error
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/ct.h b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/ct.h
similarity index 100%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/ct.h
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/ct.h
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/ct_standalone.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/ct_standalone.c
similarity index 100%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/ct_standalone.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/ct_standalone.c
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg.c
similarity index 95%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg.c
index a0c8b75a..b2bf56af 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg.c
@@ -45,7 +45,7 @@
 *
 * DESCRIPTION:
 *
-* Provides integration test entry point for the XNandPs8 component.
+* Provides integration test entry point for the XNandPsu component.
 *
 * @note		None
 *
@@ -123,7 +123,7 @@ typedef enum TimingMode {
 	Mode3,
 	Mode4,
 	Mode5
-}NandPs8_TimingMode;
+}NandPsu_TimingMode;
 
 /*
  * Uncomment the following constant definition if UART16550 is standard output
@@ -162,8 +162,8 @@ u8 WriteBuffer[TEST_BUF_SIZE] __attribute__ ((aligned(64)));/**< write buffer */
 /**
  * Nand driver instance for the Nand device.
  */
-XNandPs8 NandInstance;
-XNandPs8 *NandInstPtr = &NandInstance;
+XNandPsu NandInstance;
+XNandPsu *NandInstPtr = &NandInstance;
 /************************** Function Prototypes ******************************/
 
 static unsigned int GetUserInput(char* Prompt, char* Response,
@@ -172,9 +172,9 @@ static unsigned int GetUserInput(char* Prompt, char* Response,
 static int  GetMainMenuCommand(char* CmdLine);
 static void RunTestMenu(char* CmdLine);
 static void RunUtilMenu(char* CmdLine);
-static int ChangeTimingMode(XNandPs8 *NandInstPtr,
-				XNandPs8_DataInterface NewIntf,
-				XNandPs8_TimingMode NewMode);
+static int ChangeTimingMode(XNandPsu *NandInstPtr,
+				XNandPsu_DataInterface NewIntf,
+				XNandPsu_TimingMode NewMode);
 
 extern char inbyte ();		/**< Inbyte returns the byte received by device. */
 s32 FlashInit(u16 NandDeviceId);
@@ -424,9 +424,9 @@ int CodeCoverage_Tests(int TestLoops)
 
 	xil_printf("\tRunning Code Coverage Tests Now\r\n");
 
-	XNandPs8_DisableDmaMode(NandInstPtr);
+	XNandPsu_DisableDmaMode(NandInstPtr);
 	failures += Automode_Tests(TestLoops);
-	XNandPs8_EnableDmaMode(NandInstPtr);
+	XNandPsu_EnableDmaMode(NandInstPtr);
 	failures += Intg_BbtTest(NandInstPtr, TestLoops);
 	failures += Intg_MarkBlockBadTest(NandInstPtr, TestLoops);
 	failures += Intg_CodeCoverageTest(NandInstPtr, TestLoops);
@@ -705,7 +705,7 @@ static void RunUtilMenu(char* CmdLine)
 							GetUserInput(0, CmdLine, 131);
 						}
 						if((u8)atoi(CmdLine) >= 0 && (u8)atoi(CmdLine) <= 5){
-							Status = ChangeTimingMode(NandInstPtr,NVDDR,(XNandPs8_TimingMode)atoi(CmdLine));
+							Status = ChangeTimingMode(NandInstPtr,NVDDR,(XNandPsu_TimingMode)atoi(CmdLine));
 							if (Status != XST_SUCCESS) {
 								printf("Data Interface / Timing Mode Change"
 										" failed\r\n");
@@ -816,9 +816,9 @@ int UART_RecvByte(u8 *Data)
 s32 FlashInit(u16 NandDeviceId){
 
 	s32 Status = XST_FAILURE;
-	XNandPs8_Config *Config;
+	XNandPsu_Config *Config;
 
-	Config = XNandPs8_LookupConfig(NandDeviceId);
+	Config = XNandPsu_LookupConfig(NandDeviceId);
 	if (Config == NULL) {
 		Status = XST_FAILURE;
 		goto Out;
@@ -827,7 +827,7 @@ s32 FlashInit(u16 NandDeviceId){
 	/*
 	 * Initialize the flash driver.
 	 */
-	Status = XNandPs8_CfgInitialize(NandInstPtr, Config,
+	Status = XNandPsu_CfgInitialize(NandInstPtr, Config,
 			Config->BaseAddress);
 	if (Status != XST_SUCCESS) {
 		goto Out;
@@ -843,7 +843,7 @@ Out:
 *
 * This function changes the data interface and timing mode.
 *
-* @param	NandInstPtr is a pointer to the XNandPs8 instance.
+* @param	NandInstPtr is a pointer to the XNandPsu instance.
 * @param	NewIntf is the new data interface.
 * @param	NewMode is the new timing mode.
 *
@@ -854,9 +854,9 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static int ChangeTimingMode(XNandPs8 *NandInstPtr,
-				XNandPs8_DataInterface NewIntf,
-				XNandPs8_TimingMode NewMode){
+static int ChangeTimingMode(XNandPsu *NandInstPtr,
+				XNandPsu_DataInterface NewIntf,
+				XNandPsu_TimingMode NewMode){
 
 	s32 Status = XST_FAILURE;
 	u32 t_mode = NewMode;
@@ -870,7 +870,7 @@ static int ChangeTimingMode(XNandPs8 *NandInstPtr,
 		/*
 		 * Set Timing mode
 		 */
-		Status = XNandPs8_SetFeature(NandInstPtr, 0, 0x1, &t_mode);
+		Status = XNandPsu_SetFeature(NandInstPtr, 0, 0x1, &t_mode);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
@@ -887,7 +887,7 @@ static int ChangeTimingMode(XNandPs8 *NandInstPtr,
 		/*
 		 * Set Timing mode
 		 */
-		Status = XNandPs8_SetFeature(NandInstPtr, 0, 0x1, &ddr_mode[0]);
+		Status = XNandPsu_SetFeature(NandInstPtr, 0, 0x1, &ddr_mode[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
@@ -902,13 +902,13 @@ static int ChangeTimingMode(XNandPs8 *NandInstPtr,
 	 * Setting the Data Interface Register
 	 */
 	RegVal = ((NewMode % 6U) << ((NewIntf == NVDDR) ? 3U : 0U)) |
-			((u32)NewIntf << XNANDPS8_DATA_INTF_DATA_INTF_SHIFT);
-	XNandPs8_WriteReg(NandInstPtr->Config.BaseAddress,
-				XNANDPS8_DATA_INTF_OFFSET, RegVal);
+			((u32)NewIntf << XNANDPSU_DATA_INTF_DATA_INTF_SHIFT);
+	XNandPsu_WriteReg(NandInstPtr->Config.BaseAddress,
+				XNANDPSU_DATA_INTF_OFFSET, RegVal);
 	/*
 	 * Get the Timing mode
 	 */
-	Status = XNandPs8_GetFeature(NandInstPtr, 0, 0x1, &feature);
+	Status = XNandPsu_GetFeature(NandInstPtr, 0, 0x1, &feature);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg.h b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg.h
similarity index 88%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg.h
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg.h
index b466abe0..2fe049df 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg.h
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg.h
@@ -86,7 +86,7 @@
  * @{
  */
 #define INTG_XPAR_INTC_DEVICE_ID	XPAR_SCUGIC_SINGLE_DEVICE_ID
-#define INTG_XPAR_DEVICE_INTR_VEC	XPAR_XNANDPS8_0_INTR
+#define INTG_XPAR_DEVICE_INTR_VEC	XPAR_XNANDPSU_0_INTR
 #define printf xil_printf
 /*@}*/
 #define NAND_DEVICE_ID		0U
@@ -116,8 +116,8 @@ extern u8 WriteBuffer[];	/**< write buffer */
 
 /************************** Variable Definitions ****************************/
 
-/**< XNandPs8 instance used throughout tests */
-extern XNandPs8* NandInstPtr;
+/**< XNandPsu instance used throughout tests */
+extern XNandPsu* NandInstPtr;
 s32 MismatchCounter;
 /************************** Function Prototypes *****************************/
 
@@ -131,46 +131,46 @@ int UART_RecvByte(u8 *Data);
 /*
  * Flash Erase Read test implemented in intg_erase_read.c
  */
-int Intg_EraseReadTest(XNandPs8 * NandInstPtr, int TestLoops);
+int Intg_EraseReadTest(XNandPsu * NandInstPtr, int TestLoops);
 
 /*
  * Flash Read Write test implemented in intg_flash_rw.c
  */
-int Intg_FlashRWTest(XNandPs8 * NandInstPtr, int TestLoops);
+int Intg_FlashRWTest(XNandPsu * NandInstPtr, int TestLoops);
 
 /*
  * Random Block Read Write test implemented in intg_random_rw.c
  */
-int Intg_RandomRWTest(XNandPs8 * NandInstPtr, int TestLoops);
+int Intg_RandomRWTest(XNandPsu * NandInstPtr, int TestLoops);
 
 /*
  * SpareBytes Read Write test implemented in intg_sparebytes_rw.c
  */
-int Intg_SpareBytesRWTest(XNandPs8 * NandInstPtr,int TestLoops);
+int Intg_SpareBytesRWTest(XNandPsu * NandInstPtr,int TestLoops);
 
 /*
  * Partial Page Read Write test implemented in intg_partialpage_rw.c
  */
-int Intg_PartialRWTest(XNandPs8 * NandInstPtr,int TestLoops);
+int Intg_PartialRWTest(XNandPsu * NandInstPtr,int TestLoops);
 
 /*
  * ECC error check tests implemented in intg_ecc_test.c
  */
-int Intg_EccTest(XNandPs8 * NandInstPtr,int TestLoops);
+int Intg_EccTest(XNandPsu * NandInstPtr,int TestLoops);
 
 /*
  * BBT Scan test implemented in intg_bbt_test.c
  */
-int Intg_BbtTest(XNandPs8 * NandInstPtr, int TestLoops);
+int Intg_BbtTest(XNandPsu * NandInstPtr, int TestLoops);
 
 /*
  * Mark Block Bad test implemented in intg_markblockbad_test.c
  */
-int Intg_MarkBlockBadTest(XNandPs8 * NandInstPtr, int TestLoops);
+int Intg_MarkBlockBadTest(XNandPsu * NandInstPtr, int TestLoops);
 
 /*
  * Code Coverage test implemented in intg_codecoverage_test.c
  */
-int Intg_CodeCoverageTest(XNandPs8 * NandInstPtr, int TestLoops);
+int Intg_CodeCoverageTest(XNandPsu * NandInstPtr, int TestLoops);
 
 #endif	/**< End of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_bbt_test.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_bbt_test.c
similarity index 95%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_bbt_test.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_bbt_test.c
index bad3608d..6771e09f 100755
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_bbt_test.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_bbt_test.c
@@ -43,7 +43,7 @@
 *
 * @file intg_bbt_test.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example scans the Bbt on the flash. If found returns success else
 * Creates a new BBT and writes it on the flash.
 *
@@ -76,7 +76,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 Bbt_Test(XNandPs8 * NandInstPtr);
+s32 Bbt_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -92,7 +92,7 @@ s32 Bbt_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_BbtTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_BbtTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -127,19 +127,19 @@ int Intg_BbtTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 Bbt_Test(XNandPs8 * NandInstPtr)
+s32 Bbt_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = XST_FAILURE;
 
 	/*
 	 * Enabling Ecc Mode
 	 */
-	XNandPs8_EnableEccMode(NandInstPtr);
+	XNandPsu_EnableEccMode(NandInstPtr);
 
 	/*
 	 * Scanning for Bbt
 	 */
-	Status = XNandPs8_ScanBbt(NandInstPtr);
+	Status = XNandPsu_ScanBbt(NandInstPtr);
 	if(Status != XST_SUCCESS) {
 		xil_printf("Bad Block table not found "
 				"New Bbt created\r\n");
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_codecoverage_test.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_codecoverage_test.c
similarity index 93%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_codecoverage_test.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_codecoverage_test.c
index c7947e9b..b02f8f84 100755
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_codecoverage_test.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_codecoverage_test.c
@@ -43,7 +43,7 @@
 *
 * @file intg_codecoverage_test.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example scans the Bbt on the flash. If found returns success else
 * Creates a new BBT and writes it on the flash.
 *
@@ -77,7 +77,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 CodeCoverage_Test(XNandPs8 * NandInstPtr);
+s32 CodeCoverage_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -93,7 +93,7 @@ s32 CodeCoverage_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_CodeCoverageTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_CodeCoverageTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -118,8 +118,8 @@ int Intg_CodeCoverageTest(XNandPs8 * NandInstPtr, int TestLoops)
 * functions in polled mode.
 * The function does the following tasks:
 * 	- Performs Code Coverage for
-* 		-XNandPs8_WriteSpareBytes
-* 		-XNandPs8_LookupConfig
+* 		-XNandPsu_WriteSpareBytes
+* 		-XNandPsu_LookupConfig
 *
 * @param	NandInstPtr - Instance to the nand driver.
 *
@@ -129,7 +129,7 @@ int Intg_CodeCoverageTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 CodeCoverage_Test(XNandPs8 * NandInstPtr)
+s32 CodeCoverage_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = XST_FAILURE;
 	u32 Index;
@@ -149,18 +149,18 @@ s32 CodeCoverage_Test(XNandPs8 * NandInstPtr)
 
 	/*
 	 * Altering Ecc Address for covering code in
-	 * XNandPs8_WriteSpareBytes API
+	 * XNandPsu_WriteSpareBytes API
 	 */
 	NandInstPtr->EccCfg.EccAddr -= 8U;
 
 	/*
 	 * Enabling DMA Mode
 	 */
-	XNandPs8_EnableDmaMode(NandInstPtr);
+	XNandPsu_EnableDmaMode(NandInstPtr);
 	/*
 	 * Write to flash Spare Bytes Section
 	 */
-	Status = XNandPs8_WriteSpareBytes(NandInstPtr, (u32)Offset,
+	Status = XNandPsu_WriteSpareBytes(NandInstPtr, (u32)Offset,
 			&WriteBuffer[0]);
 	if (Status != XST_SUCCESS) {
 		Failures++;
@@ -173,7 +173,7 @@ s32 CodeCoverage_Test(XNandPs8 * NandInstPtr)
 	/*
 	 * Code Coverage for LookUp Config API
 	 */
-	Status = XNandPs8_LookupConfig(RANDOM_DEVICEID);
+	Status = XNandPsu_LookupConfig(RANDOM_DEVICEID);
 	if (Status != XST_SUCCESS){
 		Failures++;
 	}
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_ecc_test.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_ecc_test.c
similarity index 92%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_ecc_test.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_ecc_test.c
index 9df7af22..f8a51ff1 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_ecc_test.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_ecc_test.c
@@ -43,7 +43,7 @@
 *
 * @file intg_ecc_test.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example tests the erase, read and write feature of the controller
 * in the spare bytes region.The flash is erased and written. The data is
 * read back and compared with the data written for correctness.
@@ -77,7 +77,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 Ecc_Test(XNandPs8 * NandInstPtr);
+s32 Ecc_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -93,7 +93,7 @@ s32 Ecc_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_EccTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_EccTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -136,7 +136,7 @@ int Intg_EccTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 Ecc_Test(XNandPs8 * NandInstPtr)
+s32 Ecc_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = XST_FAILURE;
 	u32 Index;
@@ -159,12 +159,12 @@ s32 Ecc_Test(XNandPs8 * NandInstPtr)
 	/*
 	 * Enable ECC
 	 */
-	XNandPs8_EnableEccMode(NandInstPtr);
+	XNandPsu_EnableEccMode(NandInstPtr);
 
 	/*
 	 * Erase the flash
 	 */
-	Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
+	Status = XNandPsu_Erase(NandInstPtr, (u64)Offset, (u64)Length);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
@@ -172,7 +172,7 @@ s32 Ecc_Test(XNandPs8 * NandInstPtr)
 	/*
 	 * Write to flash
 	 */
-	Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
+	Status = XNandPsu_Write(NandInstPtr, (u64)Offset, (u64)Length,
 						&WriteBuffer[0]);
 	if (Status != XST_SUCCESS) {
 		goto Out;
@@ -181,7 +181,7 @@ s32 Ecc_Test(XNandPs8 * NandInstPtr)
 	/*
 	 * Read the flash after writing
 	 */
-	Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
+	Status = XNandPsu_Read(NandInstPtr, (u64)Offset, (u64)Length,
 						&ReadBuffer[0]);
 	if (Status != XST_SUCCESS) {
 		goto Out;
@@ -201,7 +201,7 @@ s32 Ecc_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Disable ECC
 		 */
-		XNandPs8_DisableEccMode(NandInstPtr);
+		XNandPsu_DisableEccMode(NandInstPtr);
 
 		/*
 		 * Corrupting data in Write buffer
@@ -211,7 +211,7 @@ s32 Ecc_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Write to flash
 		 */
-		Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
+		Status = XNandPsu_Write(NandInstPtr, (u64)Offset, (u64)Length,
 						&WriteBuffer[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -225,12 +225,12 @@ s32 Ecc_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Enable ECC check
 		 */
-		XNandPs8_EnableEccMode(NandInstPtr);
+		XNandPsu_EnableEccMode(NandInstPtr);
 
 		/*
 		 * Read the flash after writing
 		 */
-		Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
+		Status = XNandPsu_Read(NandInstPtr, (u64)Offset, (u64)Length,
 						&ReadBuffer[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_erase_read.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_erase_read.c
similarity index 93%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_erase_read.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_erase_read.c
index c3c94ffa..e28520b6 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_erase_read.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_erase_read.c
@@ -43,7 +43,7 @@
 *
 * @file intg_erase_read.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example tests the erase and read feature of the controller.
 * The flash is erased. The data is
 * read back and compared with the 0xFF for correctness.
@@ -77,7 +77,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 Erase_Read_Test(XNandPs8 * NandInstPtr);
+s32 Erase_Read_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -93,7 +93,7 @@ s32 Erase_Read_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_EraseReadTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_EraseReadTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -132,7 +132,7 @@ int Intg_EraseReadTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 Erase_Read_Test(XNandPs8 * NandInstPtr)
+s32 Erase_Read_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = XST_FAILURE;
 	s32 i = 0;
@@ -148,7 +148,7 @@ s32 Erase_Read_Test(XNandPs8 * NandInstPtr)
 	/*
 	 * Erasing whole block
 	 */
-	Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)BlockSize);
+	Status = XNandPsu_Erase(NandInstPtr, (u64)Offset, (u64)BlockSize);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
@@ -157,12 +157,12 @@ s32 Erase_Read_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Disbale ECC
 		 */
-		XNandPs8_DisableEccMode(NandInstPtr);
+		XNandPsu_DisableEccMode(NandInstPtr);
 
 		/*
 		 * Read the flash after writing
 		 */
-		Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
+		Status = XNandPsu_Read(NandInstPtr, (u64)Offset, (u64)Length,
 						&ReadBuffer[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -171,7 +171,7 @@ s32 Erase_Read_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Enable ECC
 		 */
-		XNandPs8_EnableEccMode(NandInstPtr);
+		XNandPsu_EnableEccMode(NandInstPtr);
 
 		/*
 		 * Compare the results
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_flash_rw.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_flash_rw.c
similarity index 94%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_flash_rw.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_flash_rw.c
index dacd3f22..3a200aa4 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_flash_rw.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_flash_rw.c
@@ -43,7 +43,7 @@
 *
 * @file intg_flash_rw.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example tests the erase, read and write feature of the controller.
 * The flash is erased and written. The data is
 * read back and compared with the data written for correctness.
@@ -77,7 +77,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 Flash_RW_Test(XNandPs8 * NandInstPtr);
+s32 Flash_RW_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -93,7 +93,7 @@ s32 Flash_RW_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_FlashRWTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_FlashRWTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -135,7 +135,7 @@ int Intg_FlashRWTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 Flash_RW_Test(XNandPs8 * NandInstPtr)
+s32 Flash_RW_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = XST_FAILURE;
 	u32 Index;
@@ -155,14 +155,14 @@ s32 Flash_RW_Test(XNandPs8 * NandInstPtr)
 	/*
 	 * Erase the Block
 	 */
-	Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
+	Status = XNandPsu_Erase(NandInstPtr, (u64)Offset, (u64)Length);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
 	/*
 	 * Write to page offset
 	 */
-	Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
+	Status = XNandPsu_Write(NandInstPtr, (u64)Offset, (u64)Length,
 						&WriteBuffer[0]);
 	if (Status != XST_SUCCESS) {
 		goto Out;
@@ -170,7 +170,7 @@ s32 Flash_RW_Test(XNandPs8 * NandInstPtr)
 	/*
 	 * Read from the page after writing
 	 */
-	Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
+	Status = XNandPsu_Read(NandInstPtr, (u64)Offset, (u64)Length,
 						&ReadBuffer[0]);
 	if (Status != XST_SUCCESS) {
 		goto Out;
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_markblockbad_test.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_markblockbad_test.c
similarity index 93%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_markblockbad_test.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_markblockbad_test.c
index 567f1877..8e7e9a02 100755
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_markblockbad_test.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_markblockbad_test.c
@@ -43,7 +43,7 @@
 *
 * @file intg_markblockbad_test.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example tests the erase, read and write feature of the controller.
 * The flash is erased and written. The data is
 * read back and compared with the data written for correctness.
@@ -77,7 +77,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 Mark_BlockBad_Test(XNandPs8 * NandInstPtr);
+s32 Mark_BlockBad_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -93,7 +93,7 @@ s32 Mark_BlockBad_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_MarkBlockBadTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_MarkBlockBadTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -135,7 +135,7 @@ int Intg_MarkBlockBadTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 Mark_BlockBad_Test(XNandPs8 * NandInstPtr)
+s32 Mark_BlockBad_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = XST_FAILURE;
 	s32 BlockNo;
@@ -164,7 +164,7 @@ s32 Mark_BlockBad_Test(XNandPs8 * NandInstPtr)
 		if(BlockNo%2 == 0){
 			continue;
 		}
-		Status = XNandPs8_MarkBlockBad(NandInstPtr,BlockNo);
+		Status = XNandPsu_MarkBlockBad(NandInstPtr,BlockNo);
 		if(Status != XST_SUCCESS){
 			goto Out;
 		}
@@ -180,7 +180,7 @@ s32 Mark_BlockBad_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Erase the Block 1,2,3
 		 */
-		Status = XNandPs8_Erase(NandInstPtr, (u64)BlockOff, (u64)BlockSize);
+		Status = XNandPsu_Erase(NandInstPtr, (u64)BlockOff, (u64)BlockSize);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
@@ -191,7 +191,7 @@ s32 Mark_BlockBad_Test(XNandPs8 * NandInstPtr)
 			/*
 			 * Write to page offset
 			 */
-			Status = XNandPs8_Write(NandInstPtr, (u64)PageOff, (u64)Length,
+			Status = XNandPsu_Write(NandInstPtr, (u64)PageOff, (u64)Length,
 					&WriteBuffer[0]);
 			if (Status != XST_SUCCESS) {
 				goto Out;
@@ -199,7 +199,7 @@ s32 Mark_BlockBad_Test(XNandPs8 * NandInstPtr)
 			/*
 			 * Read from the page after writing
 			 */
-			Status = XNandPs8_Read(NandInstPtr, (u64)PageOff, (u64)Length,
+			Status = XNandPsu_Read(NandInstPtr, (u64)PageOff, (u64)Length,
 				&ReadBuffer[0]);
 			if (Status != XST_SUCCESS) {
 				goto Out;
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_partialpage_rw.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_partialpage_rw.c
similarity index 94%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_partialpage_rw.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_partialpage_rw.c
index d8c52821..adfa116f 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_partialpage_rw.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_partialpage_rw.c
@@ -43,7 +43,7 @@
 *
 * @file intg_partialpage_rw.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example tests the erase, read and write feature of the controller
 * to the page.The flash is erased and written. The data is
 * read back and compared with the data written for correctness.
@@ -78,7 +78,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 PartialPage_RW_Test(XNandPs8 * NandInstPtr);
+s32 PartialPage_RW_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -94,7 +94,7 @@ s32 PartialPage_RW_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_PartialRWTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_PartialRWTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -135,7 +135,7 @@ int Intg_PartialRWTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 PartialPage_RW_Test(XNandPs8 * NandInstPtr)
+s32 PartialPage_RW_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = (s32)XST_FAILURE;
 	u32 Index;
@@ -159,7 +159,7 @@ s32 PartialPage_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Erase the Block
 		 */
-		Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
+		Status = XNandPsu_Erase(NandInstPtr, (u64)Offset, (u64)Length);
 		if (Status != (s32)XST_SUCCESS) {
 			goto Out;
 		}
@@ -174,7 +174,7 @@ s32 PartialPage_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Write to flash
 		 */
-		Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
+		Status = XNandPsu_Write(NandInstPtr, (u64)Offset, (u64)Length,
 						&WriteBuffer[0]);
 		if (Status != (s32)XST_SUCCESS) {
 			goto Out;
@@ -183,7 +183,7 @@ s32 PartialPage_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Read the flash after writing
 		 */
-		Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
+		Status = XNandPsu_Read(NandInstPtr, (u64)Offset, (u64)Length,
 						&ReadBuffer[0]);
 		if (Status != (s32)XST_SUCCESS) {
 			goto Out;
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_random_rw.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_random_rw.c
similarity index 94%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_random_rw.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_random_rw.c
index 14bd2a7c..7bf43bac 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_random_rw.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_random_rw.c
@@ -43,7 +43,7 @@
 *
 * @file intg_random_rw.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example tests the erase, read and write feature of the controller
 * to a complete block. The block is randomly selected.
 * The flash is erased and written. The data is read back and compared
@@ -78,7 +78,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 Random_Block_RW_Test(XNandPs8 * NandInstPtr);
+s32 Random_Block_RW_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -94,7 +94,7 @@ s32 Random_Block_RW_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_RandomRWTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_RandomRWTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -135,7 +135,7 @@ int Intg_RandomRWTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 Random_Block_RW_Test(XNandPs8 * NandInstPtr)
+s32 Random_Block_RW_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = XST_FAILURE;
 	u32 Index;
@@ -152,7 +152,7 @@ s32 Random_Block_RW_Test(XNandPs8 * NandInstPtr)
 	/*
 	 * Erase the Block
 	 */
-	Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)BlockSize);
+	Status = XNandPsu_Erase(NandInstPtr, (u64)Offset, (u64)BlockSize);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
@@ -174,7 +174,7 @@ s32 Random_Block_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Write to flash
 		 */
-		Status = XNandPs8_Write(NandInstPtr, (u64)Offset, (u64)Length,
+		Status = XNandPsu_Write(NandInstPtr, (u64)Offset, (u64)Length,
 				&WriteBuffer[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -183,7 +183,7 @@ s32 Random_Block_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Read the flash after writing
 		 */
-		Status = XNandPs8_Read(NandInstPtr, (u64)Offset, (u64)Length,
+		Status = XNandPsu_Read(NandInstPtr, (u64)Offset, (u64)Length,
 						&ReadBuffer[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_sparebytes_rw.c b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_sparebytes_rw.c
similarity index 93%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_sparebytes_rw.c
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_sparebytes_rw.c
index 6fa46324..27d8a9ad 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/intg_sparebytes_rw.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/intg_sparebytes_rw.c
@@ -43,7 +43,7 @@
 *
 * @file intg_sparebytes_rw.c
 *
-* This file contains the design example for using NAND driver (XNandPs8).
+* This file contains the design example for using NAND driver (XNandPsu).
 * This example tests the erase, read and write feature of the controller
 * in the spare bytes region.The flash is erased and written. The data is
 * read back and compared with the data written for correctness.
@@ -76,7 +76,7 @@
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
-s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr);
+s32 SpareBytes_RW_Test(XNandPsu * NandInstPtr);
 /************************** Function Definitions ****************************/
 
 /****************************************************************************/
@@ -92,7 +92,7 @@ s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr);
 * @note	 None.
 *
 *****************************************************************************/
-int Intg_SpareBytesRWTest(XNandPs8 * NandInstPtr, int TestLoops)
+int Intg_SpareBytesRWTest(XNandPsu * NandInstPtr, int TestLoops)
 {
 
 	s32 Status = XST_FAILURE;
@@ -132,7 +132,7 @@ int Intg_SpareBytesRWTest(XNandPs8 * NandInstPtr, int TestLoops)
 *		None
 *
 ****************************************************************************/
-s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr)
+s32 SpareBytes_RW_Test(XNandPsu * NandInstPtr)
 {
 	s32 Status = XST_FAILURE;
 	u32 Index;
@@ -158,7 +158,7 @@ s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Erase the flash
 		 */
-		Status = XNandPs8_Erase(NandInstPtr, (u64)Offset, (u64)Length);
+		Status = XNandPsu_Erase(NandInstPtr, (u64)Offset, (u64)Length);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
@@ -178,12 +178,12 @@ s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Disable the ECC mode
 		 */
-		XNandPs8_DisableEccMode(NandInstPtr);
+		XNandPsu_DisableEccMode(NandInstPtr);
 
 		/*
 		 * Write to flash Spare Bytes Section
 		 */
-		Status = XNandPs8_WriteSpareBytes(NandInstPtr, SpareOffset,
+		Status = XNandPsu_WriteSpareBytes(NandInstPtr, SpareOffset,
 				&WriteBuffer[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -192,7 +192,7 @@ s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Read from the flash Spare Bytes after writing
 		 */
-		Status = XNandPs8_ReadSpareBytes(NandInstPtr, SpareOffset,
+		Status = XNandPsu_ReadSpareBytes(NandInstPtr, SpareOffset,
 				&ReadBuffer[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -201,7 +201,7 @@ s32 SpareBytes_RW_Test(XNandPs8 * NandInstPtr)
 		/*
 		 * Enable the ECC mode
 		 */
-		XNandPs8_EnableEccMode(NandInstPtr);
+		XNandPsu_EnableEccMode(NandInstPtr);
 		/*
 		 * Compare the results
 		 */
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/xil_testlib.h b/XilinxProcessorIPLib/drivers/nandpsu/intgTest/xil_testlib.h
similarity index 100%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/intgTest/xil_testlib.h
rename to XilinxProcessorIPLib/drivers/nandpsu/intgTest/xil_testlib.h
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/Makefile b/XilinxProcessorIPLib/drivers/nandpsu/src/Makefile
similarity index 99%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/Makefile
rename to XilinxProcessorIPLib/drivers/nandpsu/src/Makefile
index 2aedc0d3..2e395504 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/Makefile
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/Makefile
@@ -68,7 +68,7 @@ libs: banner xuartps_libs clean
 	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
 
 banner:
-	echo "Compiling nandps8"
+	echo "Compiling nandpsu"
 
 xuartps_libs: ${OBJECTS}
 	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.c b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c
similarity index 64%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.c
rename to XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c
index 5d77ec7a..2ccfe86d 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.c
@@ -32,17 +32,18 @@
 /*****************************************************************************/
 /**
 *
-* @file xnandps8.c
+* @file xnandpsu.c
 *
 * This file contains the implementation of the interface functions for
-* XNandPs8 driver. Refer to the header file xnandps8.h for more detailed
+* XNandPsu driver. Refer to the header file xnandpsu.h for more detailed
 * information.
 *
 * This module supports for NAND flash memory devices that conform to the
 * "Open NAND Flash Interface" (ONFI) 3.0 Specification. This modules
 * implements basic flash operations like read, write and erase.
 *
-* @note		None
+* @note		Driver has been renamed to nandpsu after change in
+*		naming convention.
 *
 * <pre>
 * MODIFICATION HISTORY:
@@ -52,44 +53,44 @@
 * 1.0   nm     05/06/2014  First release
 * 2.0   sb     01/12/2015  Removed Null checks for Buffer passed
 *			   as parameter to Read API's
-*			   - XNandPs8_Read()
-*			   - XNandPs8_ReadPage
+*			   - XNandPsu_Read()
+*			   - XNandPsu_ReadPage
 *			   Modified
-*			   - XNandPs8_SetFeature()
-*			   - XNandPs8_GetFeature()
+*			   - XNandPsu_SetFeature()
+*			   - XNandPsu_GetFeature()
 *			   and made them public.
 *			   Removed Failure Return for BCF Error check in
-*			   XNandPs8_ReadPage() and added BCH_Error counter
+*			   XNandPsu_ReadPage() and added BCH_Error counter
 *			   in the instance pointer structure.
-* 			   Added XNandPs8_Prepare_Cmd API
+* 			   Added XNandPsu_Prepare_Cmd API
 *			   Replaced
-*			   - XNandPs8_IntrStsEnable
-*			   - XNandPs8_IntrStsClear
-*			   - XNandPs8_IntrClear
-*			   - XNandPs8_SetProgramReg
-*			   with XNandPs8_WriteReg call
-*			   Modified xnandps8.c file API's with above changes.
+*			   - XNandPsu_IntrStsEnable
+*			   - XNandPsu_IntrStsClear
+*			   - XNandPsu_IntrClear
+*			   - XNandPsu_SetProgramReg
+*			   with XNandPsu_WriteReg call
+*			   Modified xnandpsu.c file API's with above changes.
 *  			   Corrected the program command for Set Feature API.
 *			   Modified
-*			   - XNandPs8_OnfiReadStatus
-*			   - XNandPs8_GetFeature
-*			   - XNandPs8_SetFeature
+*			   - XNandPsu_OnfiReadStatus
+*			   - XNandPsu_GetFeature
+*			   - XNandPsu_SetFeature
 *			   to add support for DDR mode.
 *			   Changed Convention for SLC/MLC
 *			   SLC --> HAMMING
 *			   MLC --> BCH
 *			   SlcMlc --> IsBCH
 *			   Removed extra DMA mode initialization from
-*			   the XNandPs8_CfgInitialize API.
+*			   the XNandPsu_CfgInitialize API.
 *			   Modified
-*			   - XNandPs8_SetEccAddrSize
+*			   - XNandPsu_SetEccAddrSize
 *			   ECC address now is calculated based upon the
 *			   size of spare area
 *			   Modified Block Erase API, removed clearing of
 *			   packet register before erase.
 *			   Clearing Data Interface Register before
-*			   XNandPs8_OnfiReset call.
-*			   Modified XNandPs8_ChangeTimingMode API supporting
+*			   XNandPsu_OnfiReset call.
+*			   Modified XNandPsu_ChangeTimingMode API supporting
 *			   SDR and NVDDR interface for timing modes 0 to 5.
 *			   Modified Bbt Signature and Version Offset value for
 *			   Oob and No-Oob region.
@@ -98,49 +99,49 @@
 ******************************************************************************/
 
 /***************************** Include Files *********************************/
-#include "xnandps8.h"
-#include "xnandps8_bbm.h"
+#include "xnandpsu.h"
+#include "xnandpsu_bbm.h"
 /************************** Constant Definitions *****************************/
 
-const XNandPs8_EccMatrix EccMatrix[] = {
+const XNandPsu_EccMatrix EccMatrix[] = {
 	/*
 	 * 512 byte page
 	 */
-	{XNANDPS8_PAGE_SIZE_512, 9U, 1U, XNANDPS8_HAMMING, 0x20DU, 0x3U},
-	{XNANDPS8_PAGE_SIZE_512, 9U, 4U, XNANDPS8_BCH, 0x209U, 0x7U},
-	{XNANDPS8_PAGE_SIZE_512, 9U, 8U, XNANDPS8_BCH, 0x203U, 0xDU},
+	{XNANDPSU_PAGE_SIZE_512, 9U, 1U, XNANDPSU_HAMMING, 0x20DU, 0x3U},
+	{XNANDPSU_PAGE_SIZE_512, 9U, 4U, XNANDPSU_BCH, 0x209U, 0x7U},
+	{XNANDPSU_PAGE_SIZE_512, 9U, 8U, XNANDPSU_BCH, 0x203U, 0xDU},
 	/*
 	 * 2K byte page
 	 */
-	{XNANDPS8_PAGE_SIZE_2K, 9U, 1U, XNANDPS8_HAMMING, 0x834U, 0xCU},
-	{XNANDPS8_PAGE_SIZE_2K, 9U, 4U, XNANDPS8_BCH, 0x826U, 0x1AU},
-	{XNANDPS8_PAGE_SIZE_2K, 9U, 8U, XNANDPS8_BCH, 0x80cU, 0x34U},
-	{XNANDPS8_PAGE_SIZE_2K, 9U, 12U, XNANDPS8_BCH, 0x822U, 0x4EU},
-	{XNANDPS8_PAGE_SIZE_2K, 10U, 24U, XNANDPS8_BCH, 0x81cU, 0x54U},
+	{XNANDPSU_PAGE_SIZE_2K, 9U, 1U, XNANDPSU_HAMMING, 0x834U, 0xCU},
+	{XNANDPSU_PAGE_SIZE_2K, 9U, 4U, XNANDPSU_BCH, 0x826U, 0x1AU},
+	{XNANDPSU_PAGE_SIZE_2K, 9U, 8U, XNANDPSU_BCH, 0x80cU, 0x34U},
+	{XNANDPSU_PAGE_SIZE_2K, 9U, 12U, XNANDPSU_BCH, 0x822U, 0x4EU},
+	{XNANDPSU_PAGE_SIZE_2K, 10U, 24U, XNANDPSU_BCH, 0x81cU, 0x54U},
 	/*
 	 * 4K byte page
 	 */
-	{XNANDPS8_PAGE_SIZE_4K, 9U, 1U, XNANDPS8_HAMMING, 0x1068U, 0x18U},
-	{XNANDPS8_PAGE_SIZE_4K, 9U, 4U, XNANDPS8_BCH, 0x104cU, 0x34U},
-	{XNANDPS8_PAGE_SIZE_4K, 9U, 8U, XNANDPS8_BCH, 0x1018U, 0x68U},
-	{XNANDPS8_PAGE_SIZE_4K, 9U, 12U, XNANDPS8_BCH, 0x1044U, 0x9CU},
-	{XNANDPS8_PAGE_SIZE_4K, 10U, 24U, XNANDPS8_BCH, 0x1038U, 0xA8U},
+	{XNANDPSU_PAGE_SIZE_4K, 9U, 1U, XNANDPSU_HAMMING, 0x1068U, 0x18U},
+	{XNANDPSU_PAGE_SIZE_4K, 9U, 4U, XNANDPSU_BCH, 0x104cU, 0x34U},
+	{XNANDPSU_PAGE_SIZE_4K, 9U, 8U, XNANDPSU_BCH, 0x1018U, 0x68U},
+	{XNANDPSU_PAGE_SIZE_4K, 9U, 12U, XNANDPSU_BCH, 0x1044U, 0x9CU},
+	{XNANDPSU_PAGE_SIZE_4K, 10U, 24U, XNANDPSU_BCH, 0x1038U, 0xA8U},
 	/*
 	 * 8K byte page
 	 */
-	{XNANDPS8_PAGE_SIZE_8K, 9U, 1U, XNANDPS8_HAMMING, 0x20d0U, 0x30U},
-	{XNANDPS8_PAGE_SIZE_8K, 9U, 4U, XNANDPS8_BCH, 0x2098U, 0x68U},
-	{XNANDPS8_PAGE_SIZE_8K, 9U, 8U, XNANDPS8_BCH, 0x2030U, 0xD0U},
-	{XNANDPS8_PAGE_SIZE_8K, 9U, 12U, XNANDPS8_BCH, 0x2088U, 0x138U},
-	{XNANDPS8_PAGE_SIZE_8K, 10U, 24U, XNANDPS8_BCH, 0x2070U, 0x150U},
+	{XNANDPSU_PAGE_SIZE_8K, 9U, 1U, XNANDPSU_HAMMING, 0x20d0U, 0x30U},
+	{XNANDPSU_PAGE_SIZE_8K, 9U, 4U, XNANDPSU_BCH, 0x2098U, 0x68U},
+	{XNANDPSU_PAGE_SIZE_8K, 9U, 8U, XNANDPSU_BCH, 0x2030U, 0xD0U},
+	{XNANDPSU_PAGE_SIZE_8K, 9U, 12U, XNANDPSU_BCH, 0x2088U, 0x138U},
+	{XNANDPSU_PAGE_SIZE_8K, 10U, 24U, XNANDPSU_BCH, 0x2070U, 0x150U},
 	/*
 	 * 16K byte page
 	 */
-	{XNANDPS8_PAGE_SIZE_16K, 9U, 1U, XNANDPS8_HAMMING, 0x4460U, 0x60U},
-	{XNANDPS8_PAGE_SIZE_16K, 9U, 4U, XNANDPS8_BCH, 0x43f0U, 0xD0U},
-	{XNANDPS8_PAGE_SIZE_16K, 9U, 8U, XNANDPS8_BCH, 0x4320U, 0x1A0U},
-	{XNANDPS8_PAGE_SIZE_16K, 9U, 12U, XNANDPS8_BCH, 0x4250U, 0x270U},
-	{XNANDPS8_PAGE_SIZE_16K, 10U, 24U, XNANDPS8_BCH, 0x4220U, 0x2A0U}
+	{XNANDPSU_PAGE_SIZE_16K, 9U, 1U, XNANDPSU_HAMMING, 0x4460U, 0x60U},
+	{XNANDPSU_PAGE_SIZE_16K, 9U, 4U, XNANDPSU_BCH, 0x43f0U, 0xD0U},
+	{XNANDPSU_PAGE_SIZE_16K, 9U, 8U, XNANDPSU_BCH, 0x4320U, 0x1A0U},
+	{XNANDPSU_PAGE_SIZE_16K, 9U, 12U, XNANDPSU_BCH, 0x4250U, 0x270U},
+	{XNANDPSU_PAGE_SIZE_16K, 10U, 24U, XNANDPSU_BCH, 0x4220U, 0x2A0U}
 };
 
 /**************************** Type Definitions *******************************/
@@ -149,77 +150,77 @@ static u8 isQemuPlatform = 0U;
 
 /************************** Function Prototypes ******************************/
 
-static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr);
+static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr);
 
-static void XNandPs8_InitGeometry(XNandPs8 *InstancePtr, OnfiParamPage *Param);
+static void XNandPsu_InitGeometry(XNandPsu *InstancePtr, OnfiParamPage *Param);
 
-static void XNandPs8_InitFeatures(XNandPs8 *InstancePtr, OnfiParamPage *Param);
+static void XNandPsu_InitFeatures(XNandPsu *InstancePtr, OnfiParamPage *Param);
 
-static s32 XNandPs8_PollRegTimeout(XNandPs8 *InstancePtr, u32 RegOffset,
+static s32 XNandPsu_PollRegTimeout(XNandPsu *InstancePtr, u32 RegOffset,
 					u32 Mask, u32 Timeout);
 
-static void XNandPs8_SetPktSzCnt(XNandPs8 *InstancePtr, u32 PktSize,
+static void XNandPsu_SetPktSzCnt(XNandPsu *InstancePtr, u32 PktSize,
 						u32 PktCount);
 
-static void XNandPs8_SetPageColAddr(XNandPs8 *InstancePtr, u32 Page, u16 Col);
+static void XNandPsu_SetPageColAddr(XNandPsu *InstancePtr, u32 Page, u16 Col);
 
-static void XNandPs8_SetPageSize(XNandPs8 *InstancePtr);
+static void XNandPsu_SetPageSize(XNandPsu *InstancePtr);
 
-static void XNandPs8_SetBusWidth(XNandPs8 *InstancePtr);
+static void XNandPsu_SetBusWidth(XNandPsu *InstancePtr);
 
-static void XNandPs8_SelectChip(XNandPs8 *InstancePtr, u32 Target);
+static void XNandPsu_SelectChip(XNandPsu *InstancePtr, u32 Target);
 
-static s32 XNandPs8_OnfiReset(XNandPs8 *InstancePtr, u32 Target);
+static s32 XNandPsu_OnfiReset(XNandPsu *InstancePtr, u32 Target);
 
-static s32 XNandPs8_OnfiReadStatus(XNandPs8 *InstancePtr, u32 Target,
+static s32 XNandPsu_OnfiReadStatus(XNandPsu *InstancePtr, u32 Target,
 							u16 *OnfiStatus);
 
-static s32 XNandPs8_OnfiReadId(XNandPs8 *InstancePtr, u32 Target, u8 IdAddr,
+static s32 XNandPsu_OnfiReadId(XNandPsu *InstancePtr, u32 Target, u8 IdAddr,
 							u32 IdLen, u8 *Buf);
 
-static s32 XNandPs8_OnfiReadParamPage(XNandPs8 *InstancePtr, u32 Target,
+static s32 XNandPsu_OnfiReadParamPage(XNandPsu *InstancePtr, u32 Target,
 						u8 *Buf);
 
-static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
+static s32 XNandPsu_ProgramPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 							u32 Col, u8 *Buf);
 
-static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
+static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 							u32 Col, u8 *Buf);
 
-static s32 XNandPs8_CheckOnDie(XNandPs8 *InstancePtr, OnfiParamPage *Param);
+static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param);
 
-static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr);
+static void XNandPsu_SetEccAddrSize(XNandPsu *InstancePtr);
 
-static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
+static s32 XNandPsu_ChangeReadColumn(XNandPsu *InstancePtr, u32 Target,
 					u32 Col, u32 PktSize, u32 PktCount,
 					u8 *Buf);
 
-static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
+static s32 XNandPsu_ChangeWriteColumn(XNandPsu *InstancePtr, u32 Target,
 					u32 Col, u32 PktSize, u32 PktCount,
 					u8 *Buf);
 
-static s32 XNandPs8_InitExtEcc(XNandPs8 *InstancePtr, OnfiExtPrmPage *ExtPrm);
+static s32 XNandPsu_InitExtEcc(XNandPsu *InstancePtr, OnfiExtPrmPage *ExtPrm);
 
 /*****************************************************************************/
 /**
 *
-* This function initializes a specific XNandPs8 instance. This function must
+* This function initializes a specific XNandPsu instance. This function must
 * be called prior to using the NAND flash device to read or write any data.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
-* @param	ConfigPtr points to XNandPs8 device configuration structure.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
+* @param	ConfigPtr points to XNandPsu device configuration structure.
 * @param	EffectiveAddr is the base address of NAND flash controller.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
-* @note		The user needs to first call the XNandPs8_LookupConfig() API
+* @note		The user needs to first call the XNandPsu_LookupConfig() API
 *		which returns the Configuration structure pointer which is
-*		passed as a parameter to the XNandPs8_CfgInitialize() API.
+*		passed as a parameter to the XNandPsu_CfgInitialize() API.
 *
 ******************************************************************************/
-s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
+s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
 				u32 EffectiveAddr)
 {
 	s32 Status = XST_FAILURE;
@@ -238,11 +239,11 @@ s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
 	/*
 	 * Operate in Polling Mode
 	 */
-	InstancePtr->Mode = XNANDPS8_POLLING;
+	InstancePtr->Mode = XNANDPSU_POLLING;
 	/*
 	 * Enable MDMA mode by default
 	 */
-	InstancePtr->DmaMode = XNANDPS8_MDMA;
+	InstancePtr->DmaMode = XNANDPSU_MDMA;
 	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 
 	/*
@@ -259,9 +260,9 @@ s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
 	/*
 	 * Initialize the NAND flash targets
 	 */
-	Status = XNandPs8_FlashInit(InstancePtr);
+	Status = XNandPsu_FlashInit(InstancePtr);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Flash init failed\r\n",__func__);
 #endif
 		goto Out;
@@ -270,15 +271,15 @@ s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
 	 * Set ECC mode
 	 */
 	if (InstancePtr->Features.EzNand != 0U) {
-		InstancePtr->EccMode = XNANDPS8_EZNAND;
+		InstancePtr->EccMode = XNANDPSU_EZNAND;
 	} else if (InstancePtr->Features.OnDie != 0U) {
-		InstancePtr->EccMode = XNANDPS8_ONDIE;
+		InstancePtr->EccMode = XNANDPSU_ONDIE;
 	} else {
-		InstancePtr->EccMode = XNANDPS8_HWECC;
+		InstancePtr->EccMode = XNANDPSU_HWECC;
 	}
 
 	if (isQemuPlatform != 0U) {
-		InstancePtr->EccMode = XNANDPS8_NONE;
+		InstancePtr->EccMode = XNANDPSU_NONE;
 		goto Out;
 	}
 
@@ -293,10 +294,10 @@ s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
 	 * memory(RAM).  If bbt is not found, create bbt by scanning factory
 	 * marked bad blocks and store it in last good blocks of flash.
 	 */
-	XNandPs8_InitBbtDesc(InstancePtr);
-	Status = XNandPs8_ScanBbt(InstancePtr);
+	XNandPsu_InitBbtDesc(InstancePtr);
+	Status = XNandPsu_ScanBbt(InstancePtr);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: BBT scan failed\r\n",__func__);
 #endif
 		goto Out;
@@ -311,7 +312,7 @@ Out:
 *
 * This function initializes the NAND flash and gets the geometry information.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		- XST_SUCCESS if successful.
@@ -320,7 +321,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
+static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr)
 {
 	u32 Target;
 	u8 Id[ONFI_SIG_LEN] = {0U};
@@ -340,21 +341,21 @@ static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
 	/*
 	 * Clear Data Interface Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_DATA_INTF_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_DATA_INTF_OFFSET, 0U);
 
-	for (Target = 0U; Target < XNANDPS8_MAX_TARGETS; Target++) {
+	for (Target = 0U; Target < XNANDPSU_MAX_TARGETS; Target++) {
 		/*
 		 * Reset the Target
 		 */
-		Status = XNandPs8_OnfiReset(InstancePtr, Target);
+		Status = XNandPsu_OnfiReset(InstancePtr, Target);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
 		/*
 		 * Read ONFI ID
 		 */
-		Status = XNandPs8_OnfiReadId(InstancePtr, Target,
+		Status = XNandPsu_OnfiReadId(InstancePtr, Target,
 						ONFI_READ_ID_ADDR,
 						ONFI_SIG_LEN,
 						(u8 *)&Id[0]);
@@ -364,7 +365,7 @@ static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
 
 		if (!IS_ONFI(Id)) {
 			if (Target == 0U) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 				xil_printf("%s: ONFI ID doesn't match\r\n",
 								__func__);
 #endif
@@ -376,12 +377,12 @@ static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
 		/* Read Parameter Page */
 		for(Index = 0U; Index < ONFI_MND_PRM_PGS; Index++) {
 			if (Index == 0U) {
-				Status = XNandPs8_OnfiReadParamPage(InstancePtr,
+				Status = XNandPsu_OnfiReadParamPage(InstancePtr,
 							Target, (u8 *)&Param);
 			} else {
 				PrmPgOff = Index * ONFI_PRM_PG_LEN;
 				PrmPgLen = ONFI_PRM_PG_LEN;
-				Status = XNandPs8_ChangeReadColumn(InstancePtr,
+				Status = XNandPsu_ChangeReadColumn(InstancePtr,
 							Target,PrmPgOff,
 							ONFI_PRM_PG_LEN, 1U,
 							(u8 *) &Param);
@@ -390,10 +391,10 @@ static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
 				goto Out;
 			}
 			/* Check CRC */
-			Crc = XNandPs8_OnfiParamPageCrc((u8*)&Param, 0U,
+			Crc = XNandPsu_OnfiParamPageCrc((u8*)&Param, 0U,
 								ONFI_CRC_LEN);
 			if (Crc != Param.Crc) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 				xil_printf("%s: ONFI parameter page (%d) crc check failed\r\n",
 							__func__, Index);
 #endif
@@ -408,10 +409,10 @@ static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
 		}
 		/* Fill Geometry for the first target */
 		if (Target == 0U) {
-			XNandPs8_InitGeometry(InstancePtr, &Param);
-			XNandPs8_InitFeatures(InstancePtr, &Param);
+			XNandPsu_InitGeometry(InstancePtr, &Param);
+			XNandPsu_InitFeatures(InstancePtr, &Param);
 			if ((!InstancePtr->Features.EzNand) != 0U) {
-				Status =XNandPs8_CheckOnDie(InstancePtr,&Param);
+				Status =XNandPsu_CheckOnDie(InstancePtr,&Param);
 				if (Status != XST_SUCCESS) {
 					InstancePtr->Features.OnDie = 0U;
 				}
@@ -427,7 +428,7 @@ static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
 					PrmPgOff = (u32)((u32)Param.NumOfParamPages *
 							ONFI_PRM_PG_LEN) +
 							(Index * (u32)PrmPgLen);
-					Status = XNandPs8_ChangeReadColumn(
+					Status = XNandPsu_ChangeReadColumn(
 							InstancePtr,
 							Target,
 							PrmPgOff,
@@ -439,12 +440,12 @@ static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
 					/*
 					 * Check CRC
 					 */
-					Crc = XNandPs8_OnfiParamPageCrc(
+					Crc = XNandPsu_OnfiParamPageCrc(
 							(u8 *)&ExtParam,
 							2U,
 							PrmPgLen);
 					if (Crc != ExtParam.Crc) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 	xil_printf("%s: ONFI extended parameter page (%d) crc check failed\r\n",
 							__func__, Index);
 #endif
@@ -454,18 +455,18 @@ static s32 XNandPs8_FlashInit(XNandPs8 *InstancePtr)
 					/*
 					 * Initialize Extended ECC info
 					 */
-					Status = XNandPs8_InitExtEcc(
+					Status = XNandPsu_InitExtEcc(
 							InstancePtr,
 							&ExtParam);
 					if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 	xil_printf("%s: Init extended ecc failed\r\n",__func__);
 #endif
 						goto Out;
 				}
 			}
 			/* Configure ECC settings */
-			XNandPs8_SetEccAddrSize(InstancePtr);
+			XNandPsu_SetEccAddrSize(InstancePtr);
 		}
 		InstancePtr->Geometry.NumTargets++;
 	}
@@ -490,7 +491,7 @@ Out:
 *
 * This function initializes the geometry information from ONFI parameter page.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Param is pointer to the ONFI parameter page.
 *
 * @return
@@ -499,7 +500,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_InitGeometry(XNandPs8 *InstancePtr, OnfiParamPage *Param)
+static void XNandPsu_InitGeometry(XNandPsu *InstancePtr, OnfiParamPage *Param)
 {
 	/*
 	 * Assert the input arguments.
@@ -528,7 +529,7 @@ static void XNandPs8_InitGeometry(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 						(u64)Param->BytesPerPage);
 	InstancePtr->Geometry.EccCodeWordSize = 9U; /* 2 power of 9 = 512 */
 
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 	xil_printf("Manufacturer: %s\r\n", Param->DeviceManufacturer);
 	xil_printf("Device Model: %s\r\n", Param->DeviceModel);
 	xil_printf("Jedec ID: 0x%x\r\n", Param->JedecManufacturerId);
@@ -554,7 +555,7 @@ static void XNandPs8_InitGeometry(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 *
 * This function initializes the feature list from ONFI parameter page.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Param is pointer to ONFI parameter page buffer.
 *
 * @return
@@ -563,7 +564,7 @@ static void XNandPs8_InitGeometry(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_InitFeatures(XNandPs8 *InstancePtr, OnfiParamPage *Param)
+static void XNandPsu_InitFeatures(XNandPsu *InstancePtr, OnfiParamPage *Param)
 {
 	/*
 	 * Assert the input arguments.
@@ -571,8 +572,8 @@ static void XNandPs8_InitFeatures(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 	Xil_AssertVoid(Param != NULL);
 
 	InstancePtr->Features.BusWidth = ((Param->Features & (1U << 0U)) != 0U) ?
-						XNANDPS8_BUS_WIDTH_16 :
-						XNANDPS8_BUS_WIDTH_8;
+						XNANDPSU_BUS_WIDTH_16 :
+						XNANDPSU_BUS_WIDTH_8;
 	InstancePtr->Features.NvDdr = ((Param->Features & (1U << 5)) != 0U) ?
 								1U : 0U;
 	InstancePtr->Features.EzNand = ((Param->Features & (1U << 9)) != 0U) ?
@@ -586,7 +587,7 @@ static void XNandPs8_InitFeatures(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 *
 * This function checks if the flash supports on-die ECC.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Param is pointer to ONFI parameter page.
 *
 * @return
@@ -595,7 +596,7 @@ static void XNandPs8_InitFeatures(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_CheckOnDie(XNandPs8 *InstancePtr, OnfiParamPage *Param)
+static s32 XNandPsu_CheckOnDie(XNandPsu *InstancePtr, OnfiParamPage *Param)
 {
 	s32 Status = XST_FAILURE;
 	u8 JedecId[2] = {0U};
@@ -623,7 +624,7 @@ static s32 XNandPs8_CheckOnDie(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 	/*
 	 * Read JEDEC ID
 	 */
-	Status = XNandPs8_OnfiReadId(InstancePtr, 0U, 0x00U, 2U, &JedecId[0]);
+	Status = XNandPsu_OnfiReadId(InstancePtr, 0U, 0x00U, 2U, &JedecId[0]);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
@@ -656,17 +657,17 @@ static s32 XNandPs8_CheckOnDie(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 	(JedecId[1] == 0xB3U) ||
 	(JedecId[1] == 0xD3U) ||
 	(JedecId[1] == 0xC3U))) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Ondie flash detected, jedec id 0x%x 0x%x\r\n",
 					__func__, JedecId[0], JedecId[1]);
 #endif
 		/*
 		 * On-Die Set Feature
 		 */
-		Status = XNandPs8_SetFeature(InstancePtr, 0U, 0x90U,
+		Status = XNandPsu_SetFeature(InstancePtr, 0U, 0x90U,
 						&EccSetFeature[0]);
 		if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Ondie set_feature failed\r\n",
 								__func__);
 #endif
@@ -675,10 +676,10 @@ static s32 XNandPs8_CheckOnDie(XNandPs8 *InstancePtr, OnfiParamPage *Param)
 		/*
 		 * Check to see if ECC feature is set
 		 */
-		Status = XNandPs8_GetFeature(InstancePtr, 0U, 0x90U,
+		Status = XNandPsu_GetFeature(InstancePtr, 0U, 0x90U,
 						&EccGetFeature[0]);
 		if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Ondie get_feature failed\r\n",
 								__func__);
 #endif
@@ -703,7 +704,7 @@ Out:
 *
 * This function enables DMA mode of controller operation.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		None
@@ -711,7 +712,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-void XNandPs8_EnableDmaMode(XNandPs8 *InstancePtr)
+void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr)
 {
 	/*
 	 * Assert the input arguments.
@@ -719,7 +720,7 @@ void XNandPs8_EnableDmaMode(XNandPs8 *InstancePtr)
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	InstancePtr->DmaMode = XNANDPS8_MDMA;
+	InstancePtr->DmaMode = XNANDPSU_MDMA;
 }
 
 /*****************************************************************************/
@@ -727,7 +728,7 @@ void XNandPs8_EnableDmaMode(XNandPs8 *InstancePtr)
 *
 * This function disables DMA mode of driver/controller operation.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		None
@@ -735,7 +736,7 @@ void XNandPs8_EnableDmaMode(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-void XNandPs8_DisableDmaMode(XNandPs8 *InstancePtr)
+void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr)
 {
 	/*
 	 * Assert the input arguments.
@@ -743,7 +744,7 @@ void XNandPs8_DisableDmaMode(XNandPs8 *InstancePtr)
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	InstancePtr->DmaMode = XNANDPS8_PIO;
+	InstancePtr->DmaMode = XNANDPSU_PIO;
 }
 
 /*****************************************************************************/
@@ -751,7 +752,7 @@ void XNandPs8_DisableDmaMode(XNandPs8 *InstancePtr)
 *
 * This function enables ECC mode of driver/controller operation.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		None
@@ -759,7 +760,7 @@ void XNandPs8_DisableDmaMode(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-void XNandPs8_EnableEccMode(XNandPs8 *InstancePtr)
+void XNandPsu_EnableEccMode(XNandPsu *InstancePtr)
 {
 	/*
 	 * Assert the input arguments.
@@ -767,7 +768,7 @@ void XNandPs8_EnableEccMode(XNandPs8 *InstancePtr)
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	InstancePtr->EccMode = XNANDPS8_HWECC;
+	InstancePtr->EccMode = XNANDPSU_HWECC;
 }
 
 /*****************************************************************************/
@@ -775,7 +776,7 @@ void XNandPs8_EnableEccMode(XNandPs8 *InstancePtr)
 *
 * This function disables ECC mode of driver/controller operation.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		None
@@ -783,7 +784,7 @@ void XNandPs8_EnableEccMode(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-void XNandPs8_DisableEccMode(XNandPs8 *InstancePtr)
+void XNandPsu_DisableEccMode(XNandPsu *InstancePtr)
 {
 	/*
 	 * Assert the input arguments.
@@ -791,7 +792,7 @@ void XNandPs8_DisableEccMode(XNandPs8 *InstancePtr)
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	InstancePtr->EccMode = XNANDPS8_NONE;
+	InstancePtr->EccMode = XNANDPSU_NONE;
 }
 
 /*****************************************************************************/
@@ -799,7 +800,7 @@ void XNandPs8_DisableEccMode(XNandPs8 *InstancePtr)
 *
 * This function enables storing bbt version in oob area.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *			None
@@ -807,22 +808,22 @@ void XNandPs8_DisableEccMode(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-void XNandPs8_EnableBbtOobMode(XNandPs8 *InstancePtr)
+void XNandPsu_EnableBbtOobMode(XNandPsu *InstancePtr)
 {
 	/*
 	 * Assert the input arguments.
 	 */
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	InstancePtr->BbtDesc.Option = XNANDPS8_BBT_OOB;
-	InstancePtr->BbtMirrorDesc.Option = XNANDPS8_BBT_OOB;
+	InstancePtr->BbtDesc.Option = XNANDPSU_BBT_OOB;
+	InstancePtr->BbtMirrorDesc.Option = XNANDPSU_BBT_OOB;
 	/*
 	 * Setting the Signature and Version Offset
 	 */
-	InstancePtr->BbtDesc.SigOffset = XNANDPS8_BBT_DESC_SIG_OFFSET;
-	InstancePtr->BbtMirrorDesc.SigOffset = XNANDPS8_BBT_DESC_SIG_OFFSET;
-	InstancePtr->BbtDesc.VerOffset = XNANDPS8_BBT_DESC_VER_OFFSET;
-	InstancePtr->BbtMirrorDesc.VerOffset = XNANDPS8_BBT_DESC_VER_OFFSET;
+	InstancePtr->BbtDesc.SigOffset = XNANDPSU_BBT_DESC_SIG_OFFSET;
+	InstancePtr->BbtMirrorDesc.SigOffset = XNANDPSU_BBT_DESC_SIG_OFFSET;
+	InstancePtr->BbtDesc.VerOffset = XNANDPSU_BBT_DESC_VER_OFFSET;
+	InstancePtr->BbtMirrorDesc.VerOffset = XNANDPSU_BBT_DESC_VER_OFFSET;
 }
 
 /*****************************************************************************/
@@ -830,7 +831,7 @@ void XNandPs8_EnableBbtOobMode(XNandPs8 *InstancePtr)
 *
 * This function enables storing bbt version in no oob area i.e. page memory.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *			None
@@ -838,24 +839,24 @@ void XNandPs8_EnableBbtOobMode(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-void XNandPs8_DisableBbtOobMode(XNandPs8 *InstancePtr)
+void XNandPsu_DisableBbtOobMode(XNandPsu *InstancePtr)
 {
 	/*
 	 * Assert the input arguments.
 	 */
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	InstancePtr->BbtDesc.Option = XNANDPS8_BBT_NO_OOB;
-	InstancePtr->BbtMirrorDesc.Option = XNANDPS8_BBT_NO_OOB;
+	InstancePtr->BbtDesc.Option = XNANDPSU_BBT_NO_OOB;
+	InstancePtr->BbtMirrorDesc.Option = XNANDPSU_BBT_NO_OOB;
 	/*
 	 * Setting the Signature and Version Offset
 	 */
-	InstancePtr->BbtDesc.SigOffset = XNANDPS8_NO_OOB_BBT_DESC_SIG_OFFSET;
+	InstancePtr->BbtDesc.SigOffset = XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET;
 	InstancePtr->BbtMirrorDesc.SigOffset =
-					XNANDPS8_NO_OOB_BBT_DESC_SIG_OFFSET;
-	InstancePtr->BbtDesc.VerOffset = XNANDPS8_NO_OOB_BBT_DESC_VER_OFFSET;
+					XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET;
+	InstancePtr->BbtDesc.VerOffset = XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET;
 	InstancePtr->BbtMirrorDesc.VerOffset =
-					XNANDPS8_NO_OOB_BBT_DESC_VER_OFFSET;
+					XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET;
 }
 
 /*****************************************************************************/
@@ -863,7 +864,7 @@ void XNandPs8_DisableBbtOobMode(XNandPs8 *InstancePtr)
 *
 * This function polls for a register bit set status till the timeout.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	RegOffset is the offset of register.
 * @param	Mask is the bitmask.
 * @param	Timeout is the timeout value.
@@ -875,7 +876,7 @@ void XNandPs8_DisableBbtOobMode(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_PollRegTimeout(XNandPs8 *InstancePtr, u32 RegOffset,
+static s32 XNandPsu_PollRegTimeout(XNandPsu *InstancePtr, u32 RegOffset,
 					u32 Mask, u32 Timeout)
 {
 	s32 Status = XST_FAILURE;
@@ -883,7 +884,7 @@ static s32 XNandPs8_PollRegTimeout(XNandPs8 *InstancePtr, u32 RegOffset,
 	u32 TimeoutVar = Timeout;
 
 	while (TimeoutVar > 0U) {
-		RegVal = XNandPs8_ReadReg(InstancePtr->Config.BaseAddress,
+		RegVal = XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
 						RegOffset);
 		if ((RegVal & Mask) != 0U) {
 			break;
@@ -905,7 +906,7 @@ static s32 XNandPs8_PollRegTimeout(XNandPs8 *InstancePtr, u32 RegOffset,
 *
 * This function sets packet size and packet count values in packet register.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	PktSize is the packet size.
 * @param	PktCount is the packet count.
 *
@@ -915,24 +916,24 @@ static s32 XNandPs8_PollRegTimeout(XNandPs8 *InstancePtr, u32 RegOffset,
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_SetPktSzCnt(XNandPs8 *InstancePtr, u32 PktSize,
+static void XNandPsu_SetPktSzCnt(XNandPsu *InstancePtr, u32 PktSize,
 						u32 PktCount)
 {
 	/*
 	 * Assert the input arguments.
 	 */
-	Xil_AssertVoid(PktSize <= XNANDPS8_MAX_PKT_SIZE);
-	Xil_AssertVoid(PktCount <= XNANDPS8_MAX_PKT_COUNT);
+	Xil_AssertVoid(PktSize <= XNANDPSU_MAX_PKT_SIZE);
+	Xil_AssertVoid(PktCount <= XNANDPSU_MAX_PKT_COUNT);
 
 	/*
 	 * Update Packet Register with pkt size and count
 	 */
-	XNandPs8_ReadModifyWrite(InstancePtr, XNANDPS8_PKT_OFFSET,
-				((u32)XNANDPS8_PKT_PKT_SIZE_MASK |
-				(u32)XNANDPS8_PKT_PKT_CNT_MASK),
-				((PktSize & XNANDPS8_PKT_PKT_SIZE_MASK) |
-				((PktCount << XNANDPS8_PKT_PKT_CNT_SHIFT) &
-				XNANDPS8_PKT_PKT_CNT_MASK)));
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_PKT_OFFSET,
+				((u32)XNANDPSU_PKT_PKT_SIZE_MASK |
+				(u32)XNANDPSU_PKT_PKT_CNT_MASK),
+				((PktSize & XNANDPSU_PKT_PKT_SIZE_MASK) |
+				((PktCount << XNANDPSU_PKT_PKT_CNT_SHIFT) &
+				XNANDPSU_PKT_PKT_CNT_MASK)));
 }
 
 /*****************************************************************************/
@@ -940,7 +941,7 @@ static void XNandPs8_SetPktSzCnt(XNandPs8 *InstancePtr, u32 PktSize,
 *
 * This function sets Page and Column values in the Memory address registers.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Page is the page value.
 * @param	Col is the column value.
 *
@@ -950,23 +951,23 @@ static void XNandPs8_SetPktSzCnt(XNandPs8 *InstancePtr, u32 PktSize,
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_SetPageColAddr(XNandPs8 *InstancePtr, u32 Page, u16 Col)
+static void XNandPsu_SetPageColAddr(XNandPsu *InstancePtr, u32 Page, u16 Col)
 {
 	/*
 	 * Program Memory Address Register 1
 	 */
-	XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_MEM_ADDR1_OFFSET,
-				((Col & XNANDPS8_MEM_ADDR1_COL_ADDR_MASK) |
-				((Page << (u32)XNANDPS8_MEM_ADDR1_PG_ADDR_SHIFT) &
-				XNANDPS8_MEM_ADDR1_PG_ADDR_MASK)));
+	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_MEM_ADDR1_OFFSET,
+				((Col & XNANDPSU_MEM_ADDR1_COL_ADDR_MASK) |
+				((Page << (u32)XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT) &
+				XNANDPSU_MEM_ADDR1_PG_ADDR_MASK)));
 	/*
 	 * Program Memory Address Register 2
 	 */
-	XNandPs8_ReadModifyWrite(InstancePtr, XNANDPS8_MEM_ADDR2_OFFSET,
-				XNANDPS8_MEM_ADDR2_MEM_ADDR_MASK,
-				((Page >> XNANDPS8_MEM_ADDR1_PG_ADDR_SHIFT) &
-				XNANDPS8_MEM_ADDR2_MEM_ADDR_MASK));
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
+				XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK,
+				((Page >> XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT) &
+				XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK));
 }
 
 /*****************************************************************************/
@@ -974,7 +975,7 @@ static void XNandPs8_SetPageColAddr(XNandPs8 *InstancePtr, u32 Page, u16 Col)
 *
 * This function sets the size of page in Command Register.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		None
@@ -982,7 +983,7 @@ static void XNandPs8_SetPageColAddr(XNandPs8 *InstancePtr, u32 Page, u16 Col)
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_SetPageSize(XNandPs8 *InstancePtr)
+static void XNandPsu_SetPageSize(XNandPsu *InstancePtr)
 {
 	u32 PageSizeMask = 0;
 	u32 PageSize = InstancePtr->Geometry.BytesPerPage;
@@ -991,23 +992,23 @@ static void XNandPs8_SetPageSize(XNandPs8 *InstancePtr)
 	 * Calculate page size mask
 	 */
 	switch(PageSize) {
-		case XNANDPS8_PAGE_SIZE_512:
-			PageSizeMask = (0U << XNANDPS8_CMD_PG_SIZE_SHIFT);
+		case XNANDPSU_PAGE_SIZE_512:
+			PageSizeMask = (0U << XNANDPSU_CMD_PG_SIZE_SHIFT);
 			break;
-		case XNANDPS8_PAGE_SIZE_2K:
-			PageSizeMask = (1U << XNANDPS8_CMD_PG_SIZE_SHIFT);
+		case XNANDPSU_PAGE_SIZE_2K:
+			PageSizeMask = (1U << XNANDPSU_CMD_PG_SIZE_SHIFT);
 			break;
-		case XNANDPS8_PAGE_SIZE_4K:
-			PageSizeMask = (2U << XNANDPS8_CMD_PG_SIZE_SHIFT);
+		case XNANDPSU_PAGE_SIZE_4K:
+			PageSizeMask = (2U << XNANDPSU_CMD_PG_SIZE_SHIFT);
 			break;
-		case XNANDPS8_PAGE_SIZE_8K:
-			PageSizeMask = (3U << XNANDPS8_CMD_PG_SIZE_SHIFT);
+		case XNANDPSU_PAGE_SIZE_8K:
+			PageSizeMask = (3U << XNANDPSU_CMD_PG_SIZE_SHIFT);
 			break;
-		case XNANDPS8_PAGE_SIZE_16K:
-			PageSizeMask = (4U << XNANDPS8_CMD_PG_SIZE_SHIFT);
+		case XNANDPSU_PAGE_SIZE_16K:
+			PageSizeMask = (4U << XNANDPSU_CMD_PG_SIZE_SHIFT);
 			break;
-		case XNANDPS8_PAGE_SIZE_1K_16BIT:
-			PageSizeMask = (5U << XNANDPS8_CMD_PG_SIZE_SHIFT);
+		case XNANDPSU_PAGE_SIZE_1K_16BIT:
+			PageSizeMask = (5U << XNANDPSU_CMD_PG_SIZE_SHIFT);
 			break;
 		default:
 			/*
@@ -1018,8 +1019,8 @@ static void XNandPs8_SetPageSize(XNandPs8 *InstancePtr)
 	/*
 	 * Update Command Register
 	 */
-	XNandPs8_ReadModifyWrite(InstancePtr, XNANDPS8_CMD_OFFSET,
-				XNANDPS8_CMD_PG_SIZE_MASK, PageSizeMask);
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_CMD_OFFSET,
+				XNANDPSU_CMD_PG_SIZE_MASK, PageSizeMask);
 }
 
 /*****************************************************************************/
@@ -1027,7 +1028,7 @@ static void XNandPs8_SetPageSize(XNandPs8 *InstancePtr)
 *
 * This function setup the Ecc Register.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		None
@@ -1035,7 +1036,7 @@ static void XNandPs8_SetPageSize(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr)
+static void XNandPsu_SetEccAddrSize(XNandPsu *InstancePtr)
 {
 	u32 PageSize = InstancePtr->Geometry.BytesPerPage;
 	u32 CodeWordSize = InstancePtr->Geometry.EccCodeWordSize;
@@ -1044,7 +1045,7 @@ static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr)
 	u32 Found = 0U;
 	u8 BchModeVal = 0U;
 
-	for (Index = 0U; Index < (sizeof(EccMatrix)/sizeof(XNandPs8_EccMatrix));
+	for (Index = 0U; Index < (sizeof(EccMatrix)/sizeof(XNandPsu_EccMatrix));
 						Index++) {
 		if ((EccMatrix[Index].PageSize == PageSize) &&
 			(EccMatrix[Index].CodeWordSize >= CodeWordSize)) {
@@ -1059,7 +1060,7 @@ static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr)
 	}
 
 	if (Found != 0U) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("ECC: addr 0x%x size 0x%x numbits %d codesz %d\r\n",
 			PageSize + (InstancePtr->Geometry.SpareBytesPerPage
 						- EccMatrix[Found].EccSize),
@@ -1075,7 +1076,7 @@ static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr)
 		InstancePtr->EccCfg.CodeWordSize =
 						EccMatrix[Found].CodeWordSize;
 
-		if (EccMatrix[Found].IsBCH == XNANDPS8_HAMMING) {
+		if (EccMatrix[Found].IsBCH == XNANDPSU_HAMMING) {
 			InstancePtr->EccCfg.IsBCH = 0U;
 		} else {
 			InstancePtr->EccCfg.IsBCH = 1U;
@@ -1083,13 +1084,13 @@ static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr)
 		/*
 		 * Write ECC register
 		 */
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				(u32)XNANDPS8_ECC_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				(u32)XNANDPSU_ECC_OFFSET,
 				((u32)InstancePtr->EccCfg.EccAddr |
 				((u32)InstancePtr->EccCfg.EccSize << (u32)16) |
 				((u32)InstancePtr->EccCfg.IsBCH << (u32)27)));
 
-		if (EccMatrix[Found].IsBCH == XNANDPS8_BCH) {
+		if (EccMatrix[Found].IsBCH == XNANDPSU_BCH) {
 			/*
 			 * Write memory address register 2
 			 */
@@ -1112,11 +1113,11 @@ static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr)
 				default:
 					BchModeVal = 0x0U;
 			}
-			XNandPs8_ReadModifyWrite(InstancePtr,
-				XNANDPS8_MEM_ADDR2_OFFSET,
-				XNANDPS8_MEM_ADDR2_NFC_BCH_MODE_MASK,
+			XNandPsu_ReadModifyWrite(InstancePtr,
+				XNANDPSU_MEM_ADDR2_OFFSET,
+				XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK,
 				(BchModeVal <<
-				(u32)XNANDPS8_MEM_ADDR2_NFC_BCH_MODE_SHIFT));
+				(u32)XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT));
 		}
 	}
 }
@@ -1126,7 +1127,7 @@ static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr)
 *
 * This function setup the Ecc Spare Command Register.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		None
@@ -1134,11 +1135,11 @@ static void XNandPs8_SetEccAddrSize(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_SetEccSpareCmd(XNandPs8 *InstancePtr, u16 SpareCmd,
+static void XNandPsu_SetEccSpareCmd(XNandPsu *InstancePtr, u16 SpareCmd,
 								u8 AddrCycles)
 {
-	XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				(u32)XNANDPS8_ECC_SPR_CMD_OFFSET,
+	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				(u32)XNANDPSU_ECC_SPR_CMD_OFFSET,
 				(u32)SpareCmd | ((u32)AddrCycles << 28U));
 }
 
@@ -1147,7 +1148,7 @@ static void XNandPs8_SetEccSpareCmd(XNandPs8 *InstancePtr, u16 SpareCmd,
 *
 * This function sets the flash bus width in memory address2 register.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		None
@@ -1155,15 +1156,15 @@ static void XNandPs8_SetEccSpareCmd(XNandPs8 *InstancePtr, u16 SpareCmd,
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_SetBusWidth(XNandPs8 *InstancePtr)
+static void XNandPsu_SetBusWidth(XNandPsu *InstancePtr)
 {
 	/*
 	 * Update Memory Address2 register with bus width
 	 */
-	XNandPs8_ReadModifyWrite(InstancePtr, XNANDPS8_MEM_ADDR2_OFFSET,
-				XNANDPS8_MEM_ADDR2_BUS_WIDTH_MASK,
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
+				XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK,
 				(InstancePtr->Features.BusWidth <<
-				XNANDPS8_MEM_ADDR2_BUS_WIDTH_SHIFT));
+				XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT));
 
 }
 
@@ -1172,7 +1173,7 @@ static void XNandPs8_SetBusWidth(XNandPs8 *InstancePtr)
 *
 * This function sets the chip select value in memory address2 register.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 *
 * @return
@@ -1181,15 +1182,15 @@ static void XNandPs8_SetBusWidth(XNandPs8 *InstancePtr)
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_SelectChip(XNandPs8 *InstancePtr, u32 Target)
+static void XNandPsu_SelectChip(XNandPsu *InstancePtr, u32 Target)
 {
 	/*
 	 * Update Memory Address2 register with chip select
 	 */
-	XNandPs8_ReadModifyWrite(InstancePtr, XNANDPS8_MEM_ADDR2_OFFSET,
-			XNANDPS8_MEM_ADDR2_CHIP_SEL_MASK,
-			((Target << XNANDPS8_MEM_ADDR2_CHIP_SEL_SHIFT) &
-			XNANDPS8_MEM_ADDR2_CHIP_SEL_MASK));
+	XNandPsu_ReadModifyWrite(InstancePtr, XNANDPSU_MEM_ADDR2_OFFSET,
+			XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK,
+			((Target << XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT) &
+			XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK));
 }
 
 /*****************************************************************************/
@@ -1197,7 +1198,7 @@ static void XNandPs8_SelectChip(XNandPs8 *InstancePtr, u32 Target)
 *
 * This function sends ONFI Reset command to the flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 *
 * @return
@@ -1207,46 +1208,46 @@ static void XNandPs8_SelectChip(XNandPs8 *InstancePtr, u32 Target)
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_OnfiReset(XNandPs8 *InstancePtr, u32 Target)
+static s32 XNandPsu_OnfiReset(XNandPsu *InstancePtr, u32 Target)
 {
 	s32 Status = XST_FAILURE;
 
 	/*
 	 * Assert the input arguments.
 	 */
-	Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 
 	/*
 	 * Enable Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET,
-		XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 	/*
 	 * Program Command Register
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_RST, ONFI_CMD_INVALID, 0U,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RST, ONFI_CMD_INVALID, 0U,
 			0U, 0U);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Set Reset in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_PROG_OFFSET, XNANDPS8_PROG_RST_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_PROG_OFFSET, XNANDPSU_PROG_RST_MASK);
 
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -1256,14 +1257,14 @@ static s32 XNandPs8_OnfiReset(XNandPs8 *InstancePtr, u32 Target)
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		(XNANDPS8_INTR_STS_EN_OFFSET), 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		(XNANDPSU_INTR_STS_EN_OFFSET), 0U);
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 Out:
 	return Status;
@@ -1274,7 +1275,7 @@ Out:
 *
 * This function sends ONFI Read Status command to the flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	OnfiStatus is the ONFI status value to return.
 *
@@ -1285,7 +1286,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_OnfiReadStatus(XNandPs8 *InstancePtr, u32 Target,
+static s32 XNandPsu_OnfiReadStatus(XNandPsu *InstancePtr, u32 Target,
 							u16 *OnfiStatus)
 {
 	s32 Status = XST_FAILURE;
@@ -1293,48 +1294,48 @@ static s32 XNandPs8_OnfiReadStatus(XNandPs8 *InstancePtr, u32 Target,
 	/*
 	 * Assert the input arguments.
 	 */
-	Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(OnfiStatus != NULL);
 	/*
 	 * Enable Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET,
-		XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 	/*
 	 * Program Command Register
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_STS, ONFI_CMD_INVALID,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_STS, ONFI_CMD_INVALID,
 				0U, 0U, 0U);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	if(InstancePtr->DataInterface == XNANDPS8_SDR){
-		XNandPs8_SetPktSzCnt(InstancePtr, 1U, 1U);
+	if(InstancePtr->DataInterface == XNANDPSU_SDR){
+		XNandPsu_SetPktSzCnt(InstancePtr, 1U, 1U);
 	}
 	else{
-		XNandPs8_SetPktSzCnt(InstancePtr, 2U, 1U);
+		XNandPsu_SetPktSzCnt(InstancePtr, 2U, 1U);
 	}
 
 	/*
 	 * Set Read Status in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_STS_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_STS_MASK);
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -1344,19 +1345,19 @@ static s32 XNandPs8_OnfiReadStatus(XNandPs8 *InstancePtr, u32 Target,
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 	/*
 	 * Read Flash Status
 	 */
-	*OnfiStatus = (u8) XNandPs8_ReadReg(InstancePtr->Config.BaseAddress,
-						XNANDPS8_FLASH_STS_OFFSET);
+	*OnfiStatus = (u8) XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
+						XNANDPSU_FLASH_STS_OFFSET);
 
 Out:
 
@@ -1368,7 +1369,7 @@ Out:
 *
 * This function sends ONFI Read ID command to the flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Buf is the ONFI ID value to return.
 *
@@ -1379,7 +1380,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_OnfiReadId(XNandPs8 *InstancePtr, u32 Target, u8 IdAddr,
+static s32 XNandPsu_OnfiReadId(XNandPsu *InstancePtr, u32 Target, u8 IdAddr,
 							u32 IdLen, u8 *Buf)
 {
 	s32 Status = XST_FAILURE;
@@ -1392,50 +1393,50 @@ static s32 XNandPs8_OnfiReadId(XNandPs8 *InstancePtr, u32 Target, u8 IdAddr,
 	/*
 	 * Assert the input arguments.
 	 */
-	Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Buf != NULL);
 
 	/*
 	 * Enable Buffer Read Ready Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET,
-		XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 	/*
 	 * Program Command
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_ID, ONFI_CMD_INVALID, 0U,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_ID, ONFI_CMD_INVALID, 0U,
 					0U, ONFI_READ_ID_ADDR_CYCLES);
 
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, 0U, IdAddr);
+	XNandPsu_SetPageColAddr(InstancePtr, 0U, IdAddr);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, IdLen, 1U);
+	XNandPsu_SetPktSzCnt(InstancePtr, IdLen, 1U);
 	/*
 	 * Set Read ID in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_ID_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_ID_MASK);
 
 	/*
 	 * Poll for Buffer Read Ready event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 		InstancePtr,
-		XNANDPS8_INTR_STS_OFFSET,
-		XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
-		XNANDPS8_INTR_POLL_TIMEOUT);
+		XNANDPSU_INTR_STS_OFFSET,
+		XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+		XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for buf read ready timeout\r\n",
 							__func__);
 #endif
@@ -1446,30 +1447,30 @@ static s32 XNandPs8_OnfiReadId(XNandPs8 *InstancePtr, u32 Target, u8 IdAddr,
 	 * Status Enable Register
 	 */
 
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET,
-		XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 
 	/*
 	 * Clear Buffer Read Ready Interrupt in Interrupt Status
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
 	/*
 	 * Read Packet Data from Data Port Register
 	 */
 	for (Index = 0U; Index < (IdLen/4); Index++) {
-		BufPtr[Index] = XNandPs8_ReadReg(
+		BufPtr[Index] = XNandPsu_ReadReg(
 					InstancePtr->Config.BaseAddress,
-					XNANDPS8_BUF_DATA_PORT_OFFSET);
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
 	}
 	Rem = IdLen % 4;
 	if (Rem != 0U) {
-		RegVal = XNandPs8_ReadReg(
+		RegVal = XNandPsu_ReadReg(
 					InstancePtr->Config.BaseAddress,
-					XNANDPS8_BUF_DATA_PORT_OFFSET);
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
 		for (RemIdx = 0U; RemIdx < Rem; RemIdx++) {
 			Buf[(Index * 4U) + RemIdx] = (u8) (RegVal >>
 						(RemIdx * 8U)) & 0xFFU;
@@ -1479,13 +1480,13 @@ static s32 XNandPs8_OnfiReadId(XNandPs8 *InstancePtr, u32 Target, u8 IdAddr,
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -1495,14 +1496,14 @@ static s32 XNandPs8_OnfiReadId(XNandPs8 *InstancePtr, u32 Target, u8 IdAddr,
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET,0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,0U);
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 Out:
 	return Status;
@@ -1513,7 +1514,7 @@ Out:
 *
 * This function sends the ONFI Read Parameter Page command to flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	PrmIndex is the index of parameter page.
 * @param	Buf is the parameter page information to return.
@@ -1525,7 +1526,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_OnfiReadParamPage(XNandPs8 *InstancePtr, u32 Target,
+static s32 XNandPsu_OnfiReadParamPage(XNandPsu *InstancePtr, u32 Target,
 						u8 *Buf)
 {
 	s32 Status = XST_FAILURE;
@@ -1535,49 +1536,49 @@ static s32 XNandPs8_OnfiReadParamPage(XNandPs8 *InstancePtr, u32 Target,
 	/*
 	 * Assert the input arguments.
 	 */
-	Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Buf != NULL);
 
 	/*
 	 * Enable Buffer Read Ready Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET,
-		XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET,
+		XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 	/*
 	 * Program Command
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_PRM_PG, ONFI_CMD_INVALID,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD_PRM_PG, ONFI_CMD_INVALID,
 					0U, 0U, ONFI_PRM_PG_ADDR_CYCLES);
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, 0U, 0U);
+	XNandPsu_SetPageColAddr(InstancePtr, 0U, 0U);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, ONFI_PRM_PG_LEN, 1U);
+	XNandPsu_SetPktSzCnt(InstancePtr, ONFI_PRM_PG_LEN, 1U);
 	/*
 	 * Set Read Parameter Page in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_PRM_PG_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_PRM_PG_MASK);
 
 	/*
 	 * Poll for Buffer Read Ready event
 	 */
-	 Status = XNandPs8_PollRegTimeout(
+	 Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	 if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Poll for buf read ready timeout\r\n",
 							__func__);
 #endif
@@ -1589,35 +1590,35 @@ static s32 XNandPs8_OnfiReadParamPage(XNandPs8 *InstancePtr, u32 Target,
 			 * Enable Transfer Complete Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				(XNANDPS8_INTR_STS_EN_OFFSET),
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				(XNANDPSU_INTR_STS_EN_OFFSET),
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 		/*
 		 * Clear Buffer Read Ready Interrupt in Interrupt Status
 		 * Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
 		/*
 		 * Read Packet Data from Data Port Register
 		 */
 		for (Index = 0U; Index < (ONFI_PRM_PG_LEN/4); Index++) {
-			BufPtr[Index] = XNandPs8_ReadReg(
+			BufPtr[Index] = XNandPsu_ReadReg(
 					InstancePtr->Config.BaseAddress,
-						XNANDPS8_BUF_DATA_PORT_OFFSET);
+						XNANDPSU_BUF_DATA_PORT_OFFSET);
 		}
 
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -1627,14 +1628,14 @@ static s32 XNandPs8_OnfiReadParamPage(XNandPs8 *InstancePtr, u32 Target,
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 Out:
 	return Status;
@@ -1646,7 +1647,7 @@ Out:
 * This function returns the length including bad blocks from a given offset and
 * length.
 *
-* @param	InstancePtr is the pointer to the XNandPs8 instance.
+* @param	InstancePtr is the pointer to the XNandPsu instance.
 * @param	Offset is the flash data address to read from.
 * @param	Length is number of bytes to read.
 *
@@ -1656,7 +1657,7 @@ Out:
 * @note		None.
 *
 ******************************************************************************/
-static s32 XNandPs8_CalculateLength(XNandPs8 *InstancePtr, u64 Offset,
+static s32 XNandPsu_CalculateLength(XNandPsu *InstancePtr, u64 Offset,
 							u64 Length)
 {
 	s32 Status;
@@ -1674,7 +1675,7 @@ static s32 XNandPs8_CalculateLength(XNandPs8 *InstancePtr, u64 Offset,
 		/*
 		 * Check if the block is bad
 		 */
-		Status = XNandPs8_IsBlockBad(InstancePtr, Block);
+		Status = XNandPsu_IsBlockBad(InstancePtr, Block);
 		if (Status != XST_SUCCESS) {
 			/*
 			 * Good block
@@ -1698,7 +1699,7 @@ Out:
 *
 * This function writes to the flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Offset is the starting offset of flash to write.
 * @param	Length is the number of bytes to write.
 * @param	SrcBuf is the source data buffer to write.
@@ -1710,7 +1711,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-s32 XNandPs8_Write(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
+s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 {
 	s32 Status = XST_FAILURE;
 	u32 Page;
@@ -1740,7 +1741,7 @@ s32 XNandPs8_Write(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 	 * Check if write operation exceeds flash size when including
 	 * bad blocks.
 	 */
-	Status = XNandPs8_CalculateLength(InstancePtr, OffsetVar, LengthVar);
+	Status = XNandPsu_CalculateLength(InstancePtr, OffsetVar, LengthVar);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
@@ -1752,7 +1753,7 @@ s32 XNandPs8_Write(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 		 * For better results, always program the flash starting at
 		 * a block boundary.
 		 */
-		if (XNandPs8_IsBlockBad(InstancePtr, Block) == XST_SUCCESS) {
+		if (XNandPsu_IsBlockBad(InstancePtr, Block) == XST_SUCCESS) {
 			OffsetVar += (u64)InstancePtr->Geometry.BlockSize;
 			continue;
 		}
@@ -1799,7 +1800,7 @@ s32 XNandPs8_Write(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 		/*
 		 * Program page
 		 */
-		Status = XNandPs8_ProgramPage(InstancePtr, Target, Page, 0U,
+		Status = XNandPsu_ProgramPage(InstancePtr, Target, Page, 0U,
 								BufPtr);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -1808,7 +1809,7 @@ s32 XNandPs8_Write(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
 		 * ONFI ReadStatus
 		 */
 		do {
-			Status = XNandPs8_OnfiReadStatus(InstancePtr, Target,
+			Status = XNandPsu_OnfiReadStatus(InstancePtr, Target,
 								&OnfiStatus);
 			if (Status != XST_SUCCESS) {
 				goto Out;
@@ -1836,7 +1837,7 @@ Out:
 *
 * This function reads from the flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Offset is the starting offset of flash to read.
 * @param	Length is the number of bytes to read.
 * @param	DestBuf is the destination data buffer to fill in.
@@ -1848,7 +1849,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-s32 XNandPs8_Read(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
+s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
 {
 	s32 Status = XST_FAILURE;
 	u32 Page;
@@ -1876,7 +1877,7 @@ s32 XNandPs8_Read(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
 	 * Check if read operation exceeds flash size when including
 	 * bad blocks.
 	 */
-	Status = XNandPs8_CalculateLength(InstancePtr, OffsetVar, LengthVar);
+	Status = XNandPsu_CalculateLength(InstancePtr, OffsetVar, LengthVar);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
@@ -1888,7 +1889,7 @@ s32 XNandPs8_Read(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
 		 * The flash programming utility must make sure to start
 		 * writing always at a block boundary and skip blocks if any.
 		 */
-		if (XNandPs8_IsBlockBad(InstancePtr, Block) == XST_SUCCESS) {
+		if (XNandPsu_IsBlockBad(InstancePtr, Block) == XST_SUCCESS) {
 			OffsetVar += (u64)InstancePtr->Geometry.BlockSize;
 			continue;
 		}
@@ -1931,7 +1932,7 @@ s32 XNandPs8_Read(XNandPs8 *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
 		 * Read page
 		 */
 		Xil_AssertNonvoid(BufPtr != NULL);
-		Status = XNandPs8_ReadPage(InstancePtr, Target, Page, 0U,
+		Status = XNandPsu_ReadPage(InstancePtr, Target, Page, 0U,
 								BufPtr);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -1954,7 +1955,7 @@ Out:
 *
 * This function erases the flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Offset is the starting offset of flash to erase.
 * @param	Length is the number of bytes to erase.
 *
@@ -1967,7 +1968,7 @@ Out:
 *		to get better results.
 *
 ******************************************************************************/
-s32 XNandPs8_Erase(XNandPs8 *InstancePtr, u64 Offset, u64 Length)
+s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length)
 {
 	s32 Status = XST_FAILURE;
 	u32 Target = 0;
@@ -1994,7 +1995,7 @@ s32 XNandPs8_Erase(XNandPs8 *InstancePtr, u64 Offset, u64 Length)
 	 * Check if erase operation exceeds flash size when including
 	 * bad blocks.
 	 */
-	Status = XNandPs8_CalculateLength(InstancePtr, OffsetVar, LengthVar);
+	Status = XNandPsu_CalculateLength(InstancePtr, OffsetVar, LengthVar);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
@@ -2005,7 +2006,7 @@ s32 XNandPs8_Erase(XNandPs8 *InstancePtr, u64 Offset, u64 Length)
 
 	while (LengthVar > 0U) {
 		Block = (u32) (OffsetVar/InstancePtr->Geometry.BlockSize);
-		if (XNandPs8_IsBlockBad(InstancePtr, Block) ==
+		if (XNandPsu_IsBlockBad(InstancePtr, Block) ==
 							XST_SUCCESS) {
 			OffsetVar += (u64)InstancePtr->Geometry.BlockSize;
 			NumBlocks++;
@@ -2033,7 +2034,7 @@ s32 XNandPs8_Erase(XNandPs8 *InstancePtr, u64 Offset, u64 Length)
 	for (Block = StartBlock; Block < (StartBlock + NumBlocks); Block++) {
 		Target = Block/InstancePtr->Geometry.NumTargetBlocks;
 		Block %= InstancePtr->Geometry.NumTargetBlocks;
-		if (XNandPs8_IsBlockBad(InstancePtr, Block) ==
+		if (XNandPsu_IsBlockBad(InstancePtr, Block) ==
 							XST_SUCCESS) {
 			/*
 			 * Don't erase bad block
@@ -2043,7 +2044,7 @@ s32 XNandPs8_Erase(XNandPs8 *InstancePtr, u64 Offset, u64 Length)
 		/*
 		 * Block Erase
 		 */
-		Status = XNandPs8_EraseBlock(InstancePtr, Target, Block);
+		Status = XNandPsu_EraseBlock(InstancePtr, Target, Block);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
@@ -2051,7 +2052,7 @@ s32 XNandPs8_Erase(XNandPs8 *InstancePtr, u64 Offset, u64 Length)
 		 * ONFI ReadStatus
 		 */
 		do {
-			Status = XNandPs8_OnfiReadStatus(InstancePtr, Target,
+			Status = XNandPsu_OnfiReadStatus(InstancePtr, Target,
 								&OnfiStatus);
 			if (Status != XST_SUCCESS) {
 				goto Out;
@@ -2075,7 +2076,7 @@ Out:
 *
 * This function sends ONFI Program Page command to flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Page is the page address value to program.
 * @param	Col is the column address value to program.
@@ -2088,7 +2089,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
+static s32 XNandPsu_ProgramPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 							u32 Col, u8 *Buf)
 {
 	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles +
@@ -2113,80 +2114,80 @@ static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 	}
 	PktCount = InstancePtr->Geometry.BytesPerPage/PktSize;
 
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_PG_PROG1, ONFI_CMD_PG_PROG2,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_PG_PROG1, ONFI_CMD_PG_PROG2,
 					1U, 1U, (u8)AddrCycles);
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 
 		/*
 		 * Enable DMA boundary Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
-			XNANDPS8_INTR_STS_EN_DMA_INT_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
+			XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK);
 	} else {
 		/*
 		 * Enable Buffer Write Ready Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
 	}
 	/*
 	 * Program Page Size
 	 */
-	XNandPs8_SetPageSize(InstancePtr);
+	XNandPsu_SetPageSize(InstancePtr);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
 	/*
 	 * Program DMA system address and DMA buffer boundary
 	 */
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		/*
 		 * Flush the Data Cache
 		 */
 		Xil_DCacheFlushRange(Buf, (PktSize * PktCount));
 
 #ifdef __aarch64__
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR1_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
 				(u32) (((INTPTR)Buf >> 32) & 0xFFFFFFFFU));
 #endif
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR0_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
 				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
 	}
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, Page, (u16)Col);
+	XNandPsu_SetPageColAddr(InstancePtr, Page, (u16)Col);
 	/*
 	 * Set Bus Width
 	 */
-	XNandPs8_SetBusWidth(InstancePtr);
+	XNandPsu_SetBusWidth(InstancePtr);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Set ECC
 	 */
-	if (InstancePtr->EccMode == XNANDPS8_HWECC) {
-		XNandPs8_SetEccSpareCmd(InstancePtr, ONFI_CMD_CHNG_WR_COL,
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
+		XNandPsu_SetEccSpareCmd(InstancePtr, ONFI_CMD_CHNG_WR_COL,
 					InstancePtr->Geometry.ColAddrCycles);
 	}
 	/*
 	 * Set Page Program in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_PG_PROG_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_PG_PROG_MASK);
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		goto WriteDmaDone;
 	}
 
@@ -2194,13 +2195,13 @@ static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 		/*
 		 * Poll for Buffer Write Ready event
 		 */
-		Status = XNandPs8_PollRegTimeout(
+		Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 		if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Poll for buf write ready timeout\r\n",
 							__func__);
 #endif
@@ -2216,31 +2217,31 @@ static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 			 * Enable Transfer Complete Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 		} else {
 			/*
 			 * Clear Buffer Write Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 		}
 		/*
 		 * Clear Buffer Write Ready Interrupt in Interrupt Status
 		 * Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
 		/*
 		 * Write Packet Data to Data Port Register
 		 */
 		for (Index = 0U; Index < (PktSize/4U); Index++) {
-			XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-						XNANDPS8_BUF_DATA_PORT_OFFSET,
+			XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+						XNANDPSU_BUF_DATA_PORT_OFFSET,
 						BufPtr[Index]);
 		}
 		BufPtr += (PktSize/4U);
@@ -2250,9 +2251,9 @@ static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 			 * Enable Buffer Write Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
 		} else {
 			break;
 		}
@@ -2261,13 +2262,13 @@ WriteDmaDone:
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -2277,15 +2278,15 @@ WriteDmaDone:
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 Out:
 	return Status;
@@ -2296,7 +2297,7 @@ Out:
 *
 * This function sends ONFI Program Page command to flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Page is the page address value to program.
 * @param	Col is the column address value to program.
@@ -2309,7 +2310,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
+s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 {
 	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles +
 				InstancePtr->Geometry.ColAddrCycles;
@@ -2339,7 +2340,7 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 
 	PageVar %= InstancePtr->Geometry.NumTargetPages;
 
-	if (InstancePtr->EccMode == XNANDPS8_HWECC) {
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
 		/*
 		 * Calculate ECC free positions before and after ECC code
 		 */
@@ -2379,23 +2380,23 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 		}
 	}
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		/*
 		 * Enable Transfer Complete Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 
 	} else {
 		/*
 		 * Enable Buffer Write Ready Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
 
 	}
 	/*
@@ -2404,68 +2405,68 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 	if (PostWrite > 0U) {
 		Cmd.Command1 = 0x80U;
 		Cmd.Command2 = 0x00U;
-		XNandPs8_Prepare_Cmd(InstancePtr, Cmd.Command1, Cmd.Command2,
+		XNandPsu_Prepare_Cmd(InstancePtr, Cmd.Command1, Cmd.Command2,
 				0U , 1U, (u8)AddrCycles);
 
 	} else {
-		XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_PG_PROG1,
+		XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_PG_PROG1,
 				ONFI_CMD_PG_PROG2, 0U , 1U, (u8)AddrCycles);
 	}
 	/*
 	 * Program Page Size
 	 */
-	XNandPs8_SetPageSize(InstancePtr);
+	XNandPsu_SetPageSize(InstancePtr);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
 	/*
 	 * Program DMA system address and DMA buffer boundary
 	 */
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		/*
 		 * Flush the Data Cache
 		 */
 		Xil_DCacheFlushRange(BufPtr, (PktSize * PktCount));
 
 #ifdef __aarch64__
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR1_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
 				(u32) (((INTPTR)BufPtr >> 32) & 0xFFFFFFFFU));
 #endif
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR0_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
 				(u32) ((INTPTR)(void *)BufPtr & 0xFFFFFFFFU));
 
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_BUF_BND_OFFSET,
-				XNANDPS8_DMA_BUF_BND_512K);
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_BUF_BND_OFFSET,
+				XNANDPSU_DMA_BUF_BND_512K);
 	}
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
+	XNandPsu_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
 	/*
 	 * Set Bus Width
 	 */
-	XNandPs8_SetBusWidth(InstancePtr);
+	XNandPsu_SetBusWidth(InstancePtr);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Set Page Program in Program Register
 	 */
 	if (PostWrite > 0U) {
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,((u32)XNANDPS8_PROG_PG_PROG_MASK |
-				(u32)XNANDPS8_PROG_CHNG_ROW_ADDR_MASK));
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,((u32)XNANDPSU_PROG_PG_PROG_MASK |
+				(u32)XNANDPSU_PROG_CHNG_ROW_ADDR_MASK));
 	} else {
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_PG_PROG_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_PG_PROG_MASK);
 	}
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		goto WriteDmaDone;
 	}
 
@@ -2473,13 +2474,13 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 		/*
 		 * Poll for Buffer Write Ready event
 		 */
-		Status = XNandPs8_PollRegTimeout(
+		Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 		if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Poll for buf write ready timeout\r\n",
 							__func__);
 #endif
@@ -2495,31 +2496,31 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 			 * Enable Transfer Complete Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 
 		} else {
 			/*
 			 * Clear Buffer Write Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 		}
 		/*
 		 * Clear Buffer Write Ready Interrupt in Interrupt Status
 		 * Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
 		/*
 		 * Write Packet Data to Data Port Register
 		 */
 		for (Index = 0U; Index < (PktSize/4U); Index++) {
-			XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-						XNANDPS8_BUF_DATA_PORT_OFFSET,
+			XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+						XNANDPSU_BUF_DATA_PORT_OFFSET,
 						BufPtr[Index]);
 		}
 		BufPtr += (PktSize/4U);
@@ -2529,9 +2530,9 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 			 * Enable Buffer Write Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
 		} else {
 			break;
 		}
@@ -2540,13 +2541,13 @@ WriteDmaDone:
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -2556,20 +2557,20 @@ WriteDmaDone:
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
-	if (InstancePtr->EccMode == XNANDPS8_HWECC) {
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
 		if (PostWrite > 0U) {
 			BufPtr = (u32 *)(void *)&Buf[PostEccSpareCol];
-			Status = XNandPs8_ChangeWriteColumn(InstancePtr,
+			Status = XNandPsu_ChangeWriteColumn(InstancePtr,
 					Target,
 					PostEccSpareCol, PostEccSpareWrCnt, 1U,
 					(u8 *)(void *)BufPtr);
@@ -2588,7 +2589,7 @@ Out:
 *
 * This function sends ONFI Read Page command to flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Page is the page address value to read.
 * @param	Col is the column address value to read.
@@ -2601,7 +2602,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
+static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
 							u32 Col, u8 *Buf)
 {
 	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles +
@@ -2617,7 +2618,7 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 	 * Assert the input arguments.
 	 */
 	Xil_AssertNonvoid(Page < InstancePtr->Geometry.NumPages);
-	Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 
 	if (InstancePtr->EccCfg.CodeWordSize > 9U) {
 		PktSize = 1024U;
@@ -2626,85 +2627,85 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 	}
 	PktCount = InstancePtr->Geometry.BytesPerPage/PktSize;
 
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_RD1, ONFI_CMD_RD2,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD1, ONFI_CMD_RD2,
 					1U, 1U, (u8)AddrCycles);
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 
 		/*
 		 * Enable DMA boundary Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
-			XNANDPS8_INTR_STS_EN_DMA_INT_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
+			XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK);
 
 	} else {
 		/*
 		 * Enable Buffer Read Ready Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 
 	}
 	/*
 	 * Enable Single bit error and Multi bit error
 	 */
-	if (InstancePtr->EccMode == XNANDPS8_HWECC) {
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
 		/*
 		 * Interrupt Status Enable Register
 		 */
-		XNandPs8_IntrStsEnable(InstancePtr,
-			(XNANDPS8_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK |
-			XNANDPS8_INTR_STS_EN_ERR_INTR_STS_EN_MASK));
+		XNandPsu_IntrStsEnable(InstancePtr,
+			(XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK |
+			XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK));
 	}
 	/*
 	 * Program Page Size
 	 */
-	XNandPs8_SetPageSize(InstancePtr);
+	XNandPsu_SetPageSize(InstancePtr);
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, Page, (u16)Col);
+	XNandPsu_SetPageColAddr(InstancePtr, Page, (u16)Col);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
 	/*
 	 * Program DMA system address and DMA buffer boundary
 	 */
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		/*
 		 * Invalidate the Data Cache
 		 */
 		Xil_DCacheInvalidateRange(Buf, (PktSize * PktCount));
 
 #ifdef __aarch64__
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR1_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
 				(u32) (((INTPTR)(void *)Buf >> 32) &
 				0xFFFFFFFFU));
 #endif
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR0_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
 				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
 	}
 	/*
 	 * Set Bus Width
 	 */
-	XNandPs8_SetBusWidth(InstancePtr);
+	XNandPsu_SetBusWidth(InstancePtr);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Set ECC
 	 */
-	if (InstancePtr->EccMode == XNANDPS8_HWECC) {
-		XNandPs8_SetEccSpareCmd(InstancePtr,
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
+		XNandPsu_SetEccSpareCmd(InstancePtr,
 					(ONFI_CMD_CHNG_RD_COL1 |
 					(ONFI_CMD_CHNG_RD_COL2 << (u8)8U)),
 					InstancePtr->Geometry.ColAddrCycles);
@@ -2713,10 +2714,10 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 	/*
 	 * Set Read command in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		goto ReadDmaDone;
 	}
 
@@ -2724,13 +2725,13 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 		/*
 		 * Poll for Buffer Read Ready event
 		 */
-		Status = XNandPs8_PollRegTimeout(
+		Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 		if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Poll for buf read ready timeout\r\n",
 							__func__);
 #endif
@@ -2746,31 +2747,31 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 			 * Enable Transfer Complete Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 		} else {
 			/*
 			 * Clear Buffer Read Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-					XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 		}
 		/*
 		 * Clear Buffer Read Ready Interrupt in Interrupt Status
 		 * Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
 		/*
 		 * Read Packet Data from Data Port Register
 		 */
 		for (Index = 0U; Index < (PktSize/4); Index++) {
-			BufPtr[Index] = XNandPs8_ReadReg(
+			BufPtr[Index] = XNandPsu_ReadReg(
 					InstancePtr->Config.BaseAddress,
-					XNANDPS8_BUF_DATA_PORT_OFFSET);
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
 		}
 		BufPtr += (PktSize/4);
 
@@ -2779,9 +2780,9 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
 			 * Enable Buffer Read Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 
 		} else {
 			break;
@@ -2791,13 +2792,13 @@ ReadDmaDone:
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -2807,40 +2808,40 @@ ReadDmaDone:
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 CheckEccError:
 	/*
 	 * Check ECC Errors
 	 */
-	if (InstancePtr->EccMode == XNANDPS8_HWECC) {
+	if (InstancePtr->EccMode == XNANDPSU_HWECC) {
 		/*
 		 * Hamming Multi Bit Errors
 		 */
-		if (((u32)XNandPs8_ReadReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET) &
-			(u32)XNANDPS8_INTR_STS_MUL_BIT_ERR_STS_EN_MASK) != 0U) {
+		if (((u32)XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET) &
+			(u32)XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK) != 0U) {
 
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_MUL_BIT_ERR_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK);
 
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: ECC Hamming multi bit error\r\n",
 							__func__);
 #endif
 			InstancePtr->Ecc_Stat_PerPage_flips =
-					((XNandPs8_ReadReg(
+					((XNandPsu_ReadReg(
 					InstancePtr->Config.BaseAddress,
-					XNANDPS8_ECC_ERR_CNT_OFFSET) &
+					XNANDPSU_ECC_ERR_CNT_OFFSET) &
 					0x1FF00U) >> 8U);
 			InstancePtr->Ecc_Stats_total_flips +=
 					InstancePtr->Ecc_Stat_PerPage_flips;
@@ -2849,19 +2850,19 @@ CheckEccError:
 		/*
 		 * Hamming Single Bit or BCH Errors
 		 */
-		if (((u32)XNandPs8_ReadReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET) &
-			(u32)XNANDPS8_INTR_STS_ERR_INTR_STS_EN_MASK) != 0U) {
+		if (((u32)XNandPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET) &
+			(u32)XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK) != 0U) {
 
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-					XNANDPS8_INTR_STS_OFFSET,
-					XNANDPS8_INTR_STS_ERR_INTR_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_OFFSET,
+					XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK);
 
 			if (InstancePtr->EccCfg.IsBCH == 1U) {
 				InstancePtr->Ecc_Stat_PerPage_flips =
-						((XNandPs8_ReadReg(
+						((XNandPsu_ReadReg(
 						InstancePtr->Config.BaseAddress,
-						XNANDPS8_ECC_ERR_CNT_OFFSET)&
+						XNANDPSU_ECC_ERR_CNT_OFFSET)&
 						0x1FF00U) >> 8U);
 				InstancePtr->Ecc_Stats_total_flips +=
 					InstancePtr->Ecc_Stat_PerPage_flips;
@@ -2878,7 +2879,7 @@ Out:
 *
 * This function reads spare bytes from flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Page is the page address value to read.
 * @param	Buf is the data buffer to fill in.
@@ -2890,7 +2891,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
+s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
 {
 	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles +
 				InstancePtr->Geometry.ColAddrCycles;
@@ -2914,74 +2915,74 @@ s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 
 	PageVar %= InstancePtr->Geometry.NumTargetPages;
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		/*
 		 * Enable Transfer Complete Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 	} else {
 		/*
 		 * Enable Buffer Read Ready Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 	}
 	/*
 	 * Program Command
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_RD1, ONFI_CMD_RD2, 0U,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_RD1, ONFI_CMD_RD2, 0U,
 						1U, (u8)AddrCycles);
 	/*
 	 * Program Page Size
 	 */
-	XNandPs8_SetPageSize(InstancePtr);
+	XNandPsu_SetPageSize(InstancePtr);
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
+	XNandPsu_SetPageColAddr(InstancePtr, PageVar, (u16)Col);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
 	/*
 	 * Program DMA system address and DMA buffer boundary
 	 */
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 
 		/*
 		 * Invalidate the Data Cache
 		 */
 		Xil_DCacheInvalidateRange(Buf, (PktSize * PktCount));
 #ifdef __aarch64__
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR1_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
 				(u32) (((INTPTR)(void *)Buf >> 32) &
 				0xFFFFFFFFU));
 #endif
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR0_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
 				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
 	}
 	/*
 	 * Set Bus Width
 	 */
-	XNandPs8_SetBusWidth(InstancePtr);
+	XNandPsu_SetBusWidth(InstancePtr);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Set Read command in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		goto ReadDmaDone;
 	}
 
@@ -2989,13 +2990,13 @@ s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 		/*
 		 * Poll for Buffer Read Ready event
 		 */
-		Status = XNandPs8_PollRegTimeout(
+		Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 		if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Poll for buf read ready timeout\r\n",
 							__func__);
 #endif
@@ -3011,33 +3012,33 @@ s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 			 * Enable Transfer Complete Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 
 		} else {
 			/*
 			 * Clear Buffer Read Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-					XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+					XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 		}
 		/*
 		 * Clear Buffer Read Ready Interrupt in Interrupt Status
 		 * Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
 		/*
 		 * Read Packet Data from Data Port Register
 		 */
 		for (Index = 0U; Index < (PktSize/4); Index++) {
-			BufPtr[Index] = XNandPs8_ReadReg(
+			BufPtr[Index] = XNandPsu_ReadReg(
 					InstancePtr->Config.BaseAddress,
-					XNANDPS8_BUF_DATA_PORT_OFFSET);
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
 		}
 		BufPtr += (PktSize/4);
 
@@ -3046,9 +3047,9 @@ s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
 			 * Enable Buffer Read Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 		} else {
 			break;
 		}
@@ -3057,13 +3058,13 @@ ReadDmaDone:
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -3073,15 +3074,15 @@ ReadDmaDone:
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 Out:
 
 	return Status;
@@ -3092,7 +3093,7 @@ Out:
 *
 * This function sends ONFI block erase command to the flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Block is the block to erase.
 *
@@ -3103,7 +3104,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-s32 XNandPs8_EraseBlock(XNandPs8 *InstancePtr, u32 Target, u32 Block)
+s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block)
 {
 	s32 Status = XST_FAILURE;
 	u32 AddrCycles = InstancePtr->Geometry.RowAddrCycles;
@@ -3116,7 +3117,7 @@ s32 XNandPs8_EraseBlock(XNandPs8 *InstancePtr, u32 Target, u32 Block)
 	 */
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Block < InstancePtr->Geometry.NumBlocks);
 
 	Page = Block * InstancePtr->Geometry.PagesPerBlock;
@@ -3127,38 +3128,38 @@ s32 XNandPs8_EraseBlock(XNandPs8 *InstancePtr, u32 Target, u32 Block)
 	 * Enable Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 
 	/*
 	 * Program Command
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_BLK_ERASE1,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_BLK_ERASE1,
 			ONFI_CMD_BLK_ERASE2, 0U , 0U, (u8)AddrCycles);
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, ErasePage, (u16)EraseCol);
+	XNandPsu_SetPageColAddr(InstancePtr, ErasePage, (u16)EraseCol);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Set Block Erase in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_BLK_ERASE_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_BLK_ERASE_MASK);
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -3168,15 +3169,15 @@ s32 XNandPs8_EraseBlock(XNandPs8 *InstancePtr, u32 Target, u32 Block)
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 Out:
 	return Status;
@@ -3187,7 +3188,7 @@ Out:
 *
 * This function sends ONFI Get Feature command to flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Feature is the feature selector.
 * @param	Buf is the buffer to fill feature value.
@@ -3199,7 +3200,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-s32 XNandPs8_GetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
+s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 								u8 *Buf)
 {
 	s32 Status;
@@ -3213,7 +3214,7 @@ s32 XNandPs8_GetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
 	 */
 	Xil_AssertNonvoid(Buf != NULL);
 
-	if (InstancePtr->DataInterface == XNANDPS8_NVDDR) {
+	if (InstancePtr->DataInterface == XNANDPSU_NVDDR) {
 		PktSize = 8U;
 	}
 
@@ -3221,41 +3222,41 @@ s32 XNandPs8_GetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
 	 * Enable Buffer Read Ready Interrupt in Interrupt Status
 	 * Enable Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 	/*
 	 * Program Command
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_GET_FEATURES,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_GET_FEATURES,
 				ONFI_CMD_INVALID, 0U, 0U, 1U);
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, 0x0U, Feature);
+	XNandPsu_SetPageColAddr(InstancePtr, 0x0U, Feature);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
 	/*
 	 * Set Read Parameter Page in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_GET_FEATURES_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_GET_FEATURES_MASK);
 	/*
 	 * Poll for Buffer Read Ready event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 		InstancePtr,
-		XNANDPS8_INTR_STS_OFFSET,
-		XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
-		XNANDPS8_INTR_POLL_TIMEOUT);
+		XNANDPSU_INTR_STS_OFFSET,
+		XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+		XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for buf read ready timeout\r\n",
 							__func__);
 #endif
@@ -3265,41 +3266,41 @@ s32 XNandPs8_GetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
 	 * Clear Buffer Read Ready Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Buffer Read Ready Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
 	/*
 	 * Enable Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 
 	/*
 	 * Read Data from Data Port Register
 	 */
 	for (Index = 0U; Index < (PktSize/4U); Index++) {
-		BufPtr[Index] = XNandPs8_ReadReg(
+		BufPtr[Index] = XNandPsu_ReadReg(
 					InstancePtr->Config.BaseAddress,
-					XNANDPS8_BUF_DATA_PORT_OFFSET);
+					XNANDPSU_BUF_DATA_PORT_OFFSET);
 	}
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -3309,15 +3310,15 @@ s32 XNandPs8_GetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 Out:
 	return Status;
@@ -3328,7 +3329,7 @@ Out:
 *
 * This function sends ONFI Set Feature command to flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Feature is the feature selector.
 * @param	Buf is the feature value to send.
@@ -3340,7 +3341,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-s32 XNandPs8_SetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
+s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 								u8 *Buf)
 {
 	s32 Status;
@@ -3353,53 +3354,53 @@ s32 XNandPs8_SetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
 	 * Assert the input arguments.
 	 */
 	Xil_AssertNonvoid(Buf != NULL);
-	if (InstancePtr->DataInterface == XNANDPS8_NVDDR) {
+	if (InstancePtr->DataInterface == XNANDPSU_NVDDR) {
 		PktSize = 8U;
 	}
 
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Enable Buffer Write Ready Interrupt in Interrupt Status
 	 * Enable Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET,
-			XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET,
+			XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
 
 	/*
 	 * Program Command
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_SET_FEATURES,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_SET_FEATURES,
 				ONFI_CMD_INVALID, 0U , 0U, 1U);
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, 0x0U, Feature);
+	XNandPsu_SetPageColAddr(InstancePtr, 0x0U, Feature);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
 	/*
 	 * Set Read Parameter Page in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_SET_FEATURES_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_SET_FEATURES_MASK);
 	/*
 	 * Poll for Buffer Write Ready event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 		InstancePtr,
-		XNANDPS8_INTR_STS_OFFSET,
-		XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
-		XNANDPS8_INTR_POLL_TIMEOUT);
+		XNANDPSU_INTR_STS_OFFSET,
+		XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
+		XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for buf write ready timeout\r\n",
 							__func__);
 #endif
@@ -3409,40 +3410,40 @@ s32 XNandPs8_SetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
 	 * Clear Buffer Write Ready Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Buffer Write Ready Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
 	/*
 	 * Enable Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			(XNANDPS8_INTR_STS_EN_OFFSET),
-			XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			(XNANDPSU_INTR_STS_EN_OFFSET),
+			XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 	/*
 	 * Write Data to Data Port Register
 	 */
 	for (Index = 0U; Index < (PktSize/4U); Index++) {
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-					XNANDPS8_BUF_DATA_PORT_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+					XNANDPSU_BUF_DATA_PORT_OFFSET,
 					BufPtr[Index]);
 	}
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -3452,15 +3453,15 @@ s32 XNandPs8_SetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 Out:
 	return Status;
@@ -3471,7 +3472,7 @@ Out:
 *
 * This function changes clock frequency of flash controller.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	ClockFreq is the clock frequency to change.
 *
 * @return
@@ -3480,7 +3481,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static void XNandPs8_ChangeClockFreq(XNandPs8 *InstancePtr, u32 ClockFreq)
+static void XNandPsu_ChangeClockFreq(XNandPsu *InstancePtr, u32 ClockFreq)
 {
 	/*
 	 * Not implemented
@@ -3491,7 +3492,7 @@ static void XNandPs8_ChangeClockFreq(XNandPs8 *InstancePtr, u32 ClockFreq)
 *
 * This function changes the data interface and timing mode.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	NewIntf is the new data interface.
 * @param	NewMode is the new timing mode.
 *
@@ -3502,9 +3503,9 @@ static void XNandPs8_ChangeClockFreq(XNandPs8 *InstancePtr, u32 ClockFreq)
 * @note		None
 *
 ******************************************************************************/
-s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
-				XNandPs8_DataInterface NewIntf,
-				XNandPs8_TimingMode NewMode)
+s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
+				XNandPsu_DataInterface NewIntf,
+				XNandPsu_TimingMode NewMode)
 {
 	s32 Status;
 	u32 Target;
@@ -3525,20 +3526,20 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
 	/*
 	 * Check for valid input arguments
 	 */
-	if((NewIntf != XNANDPS8_SDR && NewIntf != XNANDPS8_NVDDR) ||
+	if((NewIntf != XNANDPSU_SDR && NewIntf != XNANDPSU_NVDDR) ||
 			(NewModeVar > 5U)){
 		Status = XST_FAILURE;
 		goto Out;
 	}
 
-	if(NewIntf == XNANDPS8_NVDDR){
+	if(NewIntf == XNANDPSU_NVDDR){
 		NewModeVar = NewModeVar | 0x10U;
 	}
 	/*
 	 * Get current data interface type and timing mode
 	 */
-	XNandPs8_DataInterface CurIntf = InstancePtr->DataInterface;
-	XNandPs8_TimingMode CurMode = InstancePtr->TimingMode;
+	XNandPsu_DataInterface CurIntf = InstancePtr->DataInterface;
+	XNandPsu_TimingMode CurMode = InstancePtr->TimingMode;
 
 	/*
 	 * Check if the flash is in same mode
@@ -3548,26 +3549,26 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
 		goto Out;
 	}
 
-	if ((CurIntf == XNANDPS8_NVDDR) && (NewIntf == XNANDPS8_SDR)) {
+	if ((CurIntf == XNANDPSU_NVDDR) && (NewIntf == XNANDPSU_SDR)) {
 
-		NewModeVar = XNANDPS8_SDR0;
+		NewModeVar = XNANDPSU_SDR0;
 
 		/*
 		 * Change the clock frequency
 		 */
-		XNandPs8_ChangeClockFreq(InstancePtr, XNANDPS8_SDR_CLK);
+		XNandPsu_ChangeClockFreq(InstancePtr, XNANDPSU_SDR_CLK);
 
 		/*
 		 * Update Data Interface Register
 		 */
-		RegVal = ((NewModeVar % 6U) << ((NewIntf == XNANDPS8_NVDDR) ? 3U : 0U)) |
-				((u32)NewIntf << XNANDPS8_DATA_INTF_DATA_INTF_SHIFT);
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-					XNANDPS8_DATA_INTF_OFFSET, RegVal);
+		RegVal = ((NewModeVar % 6U) << ((NewIntf == XNANDPSU_NVDDR) ? 3U : 0U)) |
+				((u32)NewIntf << XNANDPSU_DATA_INTF_DATA_INTF_SHIFT);
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+					XNANDPSU_DATA_INTF_OFFSET, RegVal);
 
 		for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
 							Target++) {
-			Status = XNandPs8_OnfiReset(InstancePtr, Target);
+			Status = XNandPsu_OnfiReset(InstancePtr, Target);
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
@@ -3578,7 +3579,7 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
 		 */
 		for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
 								Target++) {
-			Status = XNandPs8_SetFeature(InstancePtr, Target, 0x01U,
+			Status = XNandPsu_SetFeature(InstancePtr, Target, 0x01U,
 							(u8 *)&NewModeVar);
 			if (Status != XST_SUCCESS) {
 				goto Out;
@@ -3590,7 +3591,7 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
 
 		for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
 								Target++) {
-			Status = XNandPs8_GetFeature(InstancePtr, Target, 0x01U,
+			Status = XNandPsu_GetFeature(InstancePtr, Target, 0x01U,
 								&Buf[0]);
 			if (Status != XST_SUCCESS) {
 				goto Out;
@@ -3608,7 +3609,7 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
 	}
 
 	SetFeature = NewModeVar;
-	if(CurIntf == XNANDPS8_NVDDR && NewIntf == XNANDPS8_NVDDR){
+	if(CurIntf == XNANDPSU_NVDDR && NewIntf == XNANDPSU_NVDDR){
 		SetFeature |= SetFeature << 8U;
 	}
 	/*
@@ -3616,7 +3617,7 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
 	 */
 	for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
 							Target++) {
-		Status = XNandPs8_SetFeature(InstancePtr, Target, 0x01U,
+		Status = XNandPsu_SetFeature(InstancePtr, Target, 0x01U,
 						(u8 *)&SetFeature);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -3628,17 +3629,17 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
 	/*
 	 * Update Data Interface Register
 	 */
-	RegVal = ((NewMode % 6U) << ((NewIntf == XNANDPS8_NVDDR) ? 3U : 0U)) |
-			((u32)NewIntf << XNANDPS8_DATA_INTF_DATA_INTF_SHIFT);
-	XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DATA_INTF_OFFSET, RegVal);
+	RegVal = ((NewMode % 6U) << ((NewIntf == XNANDPSU_NVDDR) ? 3U : 0U)) |
+			((u32)NewIntf << XNANDPSU_DATA_INTF_DATA_INTF_SHIFT);
+	XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DATA_INTF_OFFSET, RegVal);
 
 	/*
 	 * Get Feature
 	 */
 	for (Target = 0U; Target < InstancePtr->Geometry.NumTargets;
 							Target++) {
-		Status = XNandPs8_GetFeature(InstancePtr, Target, 0x01U,
+		Status = XNandPsu_GetFeature(InstancePtr, Target, 0x01U,
 							&Buf[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -3664,7 +3665,7 @@ Out:
 * This function issues change read column and reads the data into buffer
 * specified by user.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Col is the coulmn address.
 * @param	PktSize is the number of bytes to read.
@@ -3678,7 +3679,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
+static s32 XNandPsu_ChangeReadColumn(XNandPsu *InstancePtr, u32 Target,
 					u32 Col, u32 PktSize, u32 PktCount,
 					u8 *Buf)
 {
@@ -3691,76 +3692,76 @@ static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
 	/*
 	 * Assert the input arguments.
 	 */
-	Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Buf != NULL);
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		/*
 		 * Enable DMA boundary Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
-				XNANDPS8_INTR_STS_EN_DMA_INT_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
+				XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK);
 	} else {
 		/*
 		 * Enable Buffer Read Ready Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 	}
 	/*
 	 * Program Command
 	 */
-	XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_CHNG_RD_COL1,
+	XNandPsu_Prepare_Cmd(InstancePtr, ONFI_CMD_CHNG_RD_COL1,
 			ONFI_CMD_CHNG_RD_COL2, 0U , 1U, (u8)AddrCycles);
 	/*
 	 * Program Page Size
 	 */
-	XNandPs8_SetPageSize(InstancePtr);
+	XNandPsu_SetPageSize(InstancePtr);
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, 0U, (u16)Col);
+	XNandPsu_SetPageColAddr(InstancePtr, 0U, (u16)Col);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
 	/*
 	 * Program DMA system address and DMA buffer boundary
 	 */
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		/*
 		 * Invalidate the Data Cache
 		 */
 		Xil_DCacheInvalidateRange(Buf, (PktSize * PktCount));
 #ifdef __aarch64__
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR1_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
 				(u32) (((INTPTR)Buf >> 32) & 0xFFFFFFFFU));
 #endif
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR0_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
 				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
 	}
 	/*
 	 * Set Bus Width
 	 */
-	XNandPs8_SetBusWidth(InstancePtr);
+	XNandPsu_SetBusWidth(InstancePtr);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Set Read command in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_RD_MASK);
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		goto ReadDmaDone;
 	}
 
@@ -3768,13 +3769,13 @@ static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
 		/*
 		 * Poll for Buffer Read Ready event
 		 */
-		Status = XNandPs8_PollRegTimeout(
+		Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 		if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Poll for buf read ready timeout\r\n",
 							__func__);
 #endif
@@ -3790,32 +3791,32 @@ static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
 			 * Enable Transfer Complete Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 		} else {
 			/*
 			 * Clear Buffer Read Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 		}
 		/*
 		 * Clear Buffer Read Ready Interrupt in Interrupt Status
 		 * Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK);
 		/*
 		 * Read Packet Data from Data Port Register
 		 */
 		for (Index = 0U; Index < (PktSize/4); Index++) {
-			BufPtr[Index] = XNandPs8_ReadReg(
+			BufPtr[Index] = XNandPsu_ReadReg(
 						InstancePtr->Config.BaseAddress,
-						XNANDPS8_BUF_DATA_PORT_OFFSET);
+						XNANDPSU_BUF_DATA_PORT_OFFSET);
 		}
 		BufPtr += (PktSize/4U);
 
@@ -3824,9 +3825,9 @@ static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
 			 * Enable Buffer Read Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK);
 		} else {
 			break;
 		}
@@ -3835,13 +3836,13 @@ ReadDmaDone:
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -3851,15 +3852,15 @@ ReadDmaDone:
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 Out:
 	return Status;
 }
@@ -3870,7 +3871,7 @@ Out:
 * This function issues change read column and reads the data into buffer
 * specified by user.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Target is the chip select value.
 * @param	Col is the coulmn address.
 * @param	PktSize is the number of bytes to read.
@@ -3884,7 +3885,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
+static s32 XNandPsu_ChangeWriteColumn(XNandPsu *InstancePtr, u32 Target,
 					u32 Col, u32 PktSize, u32 PktCount,
 					u8 *Buf)
 {
@@ -3898,79 +3899,79 @@ static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
 	/*
 	 * Assert the input arguments.
 	 */
-	Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
+	Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
 	Xil_AssertNonvoid(Buf != NULL);
 
 	if (PktCount == 0U) {
 		return XST_SUCCESS;
 	}
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		/*
 		 * Enable DMA boundary Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
-				XNANDPS8_INTR_STS_EN_DMA_INT_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
+				XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK);
 	} else {
 		/*
 		 * Enable Buffer Write Ready Interrupt in Interrupt Status
 		 * Enable Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
 	}
 	/*
 	 * Change write column hack
 	 */
 	OnfiCommand.Command1 = 0x85U;
 	OnfiCommand.Command2 = 0x10U;
-	XNandPs8_Prepare_Cmd(InstancePtr, OnfiCommand.Command1,
+	XNandPsu_Prepare_Cmd(InstancePtr, OnfiCommand.Command1,
 				OnfiCommand.Command2, 0U , 0U, (u8)AddrCycles);
 
 	/*
 	 * Program Page Size
 	 */
-	XNandPs8_SetPageSize(InstancePtr);
+	XNandPsu_SetPageSize(InstancePtr);
 	/*
 	 * Program Column, Page, Block address
 	 */
-	XNandPs8_SetPageColAddr(InstancePtr, 0U, (u16)Col);
+	XNandPsu_SetPageColAddr(InstancePtr, 0U, (u16)Col);
 	/*
 	 * Program Packet Size and Packet Count
 	 */
-	XNandPs8_SetPktSzCnt(InstancePtr, PktSize, PktCount);
+	XNandPsu_SetPktSzCnt(InstancePtr, PktSize, PktCount);
 	/*
 	 * Program DMA system address and DMA buffer boundary
 	 */
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 #ifdef __aarch64__
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR1_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR1_OFFSET,
 				(u32) (((INTPTR)Buf >> 32U) & 0xFFFFFFFFU));
 #endif
-		XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-				XNANDPS8_DMA_SYS_ADDR0_OFFSET,
+		XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XNANDPSU_DMA_SYS_ADDR0_OFFSET,
 				(u32) ((INTPTR)(void *)Buf & 0xFFFFFFFFU));
 	}
 	/*
 	 * Set Bus Width
 	 */
-	XNandPs8_SetBusWidth(InstancePtr);
+	XNandPsu_SetBusWidth(InstancePtr);
 	/*
 	 * Program Memory Address Register2 for chip select
 	 */
-	XNandPs8_SelectChip(InstancePtr, Target);
+	XNandPsu_SelectChip(InstancePtr, Target);
 	/*
 	 * Set Page Program in Program Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_CHNG_ROW_ADDR_END_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_PROG_OFFSET,XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK);
 
-	if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
+	if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
 		goto WriteDmaDone;
 	}
 
@@ -3978,13 +3979,13 @@ static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
 		/*
 		 * Poll for Buffer Write Ready event
 		 */
-		Status = XNandPs8_PollRegTimeout(
+		Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 		if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 			xil_printf("%s: Poll for buf write ready timeout\r\n",
 							__func__);
 #endif
@@ -4000,30 +4001,30 @@ static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
 			 * Enable Transfer Complete Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK);
 		} else {
 			/*
 			 * Clear Buffer Write Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 		}
 		/*
 		 * Clear Buffer Write Ready Interrupt in Interrupt Status
 		 * Register
 		 */
-		XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_OFFSET,
-				XNANDPS8_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
+		XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_OFFSET,
+				XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK);
 		/*
 		 * Write Packet Data to Data Port Register
 		 */
 		for (Index = 0U; Index < (PktSize/4U); Index++) {
-			XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
-						XNANDPS8_BUF_DATA_PORT_OFFSET,
+			XNandPsu_WriteReg(InstancePtr->Config.BaseAddress,
+						XNANDPSU_BUF_DATA_PORT_OFFSET,
 						BufPtr[Index]);
 		}
 		BufPtr += (PktSize/4U);
@@ -4033,9 +4034,9 @@ static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
 			 * Enable Buffer Write Ready Interrupt in Interrupt
 			 * Status Enable Register
 			 */
-			XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-				XNANDPS8_INTR_STS_EN_OFFSET,
-				XNANDPS8_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
+			XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+				XNANDPSU_INTR_STS_EN_OFFSET,
+				XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK);
 		} else {
 			break;
 		}
@@ -4044,13 +4045,13 @@ WriteDmaDone:
 	/*
 	 * Poll for Transfer Complete event
 	 */
-	Status = XNandPs8_PollRegTimeout(
+	Status = XNandPsu_PollRegTimeout(
 			InstancePtr,
-			XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK,
-			XNANDPS8_INTR_POLL_TIMEOUT);
+			XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK,
+			XNANDPSU_INTR_POLL_TIMEOUT);
 	if (Status != XST_SUCCESS) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Poll for xfer complete timeout\r\n",
 							__func__);
 #endif
@@ -4060,15 +4061,15 @@ WriteDmaDone:
 	 * Clear Transfer Complete Interrupt in Interrupt Status Enable
 	 * Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_EN_OFFSET, 0U);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_EN_OFFSET, 0U);
 
 	/*
 	 * Clear Transfer Complete Interrupt in Interrupt Status Register
 	 */
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-		XNANDPS8_INTR_STS_OFFSET,
-			XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+		XNANDPSU_INTR_STS_OFFSET,
+			XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK);
 
 Out:
 	return Status;
@@ -4079,7 +4080,7 @@ Out:
 *
 * This function initializes extended parameter page ECC information.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	ExtPrm is the Extended parameter page buffer.
 *
 * @return
@@ -4089,7 +4090,7 @@ Out:
 * @note		None
 *
 ******************************************************************************/
-static s32 XNandPs8_InitExtEcc(XNandPs8 *InstancePtr, OnfiExtPrmPage *ExtPrm)
+static s32 XNandPsu_InitExtEcc(XNandPsu *InstancePtr, OnfiExtPrmPage *ExtPrm)
 {
 	s32 Status = XST_FAILURE;
 	u32 Index;
@@ -4102,7 +4103,7 @@ static s32 XNandPs8_InitExtEcc(XNandPs8 *InstancePtr, OnfiExtPrmPage *ExtPrm)
 	if (ExtPrm->Section0Type != 0x2U) {
 		Offset += (u32)ExtPrm->Section0Len;
 		if (ExtPrm->Section1Type != 0x2U) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Extended ECC section not found\r\n",__func__);
 #endif
 			Status = XST_FAILURE;
@@ -4134,7 +4135,7 @@ static s32 XNandPs8_InitExtEcc(XNandPs8 *InstancePtr, OnfiExtPrmPage *ExtPrm)
 *
 * This function prepares command to be written into command register.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Cmd1 is the first Onfi Command.
 * @param	Cmd1 is the second Onfi Command.
 * @param	EccState is the flag to set Ecc State.
@@ -4146,29 +4147,29 @@ static s32 XNandPs8_InitExtEcc(XNandPs8 *InstancePtr, OnfiExtPrmPage *ExtPrm)
 * @note		None
 *
 ******************************************************************************/
-void XNandPs8_Prepare_Cmd(XNandPs8 *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
+void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
 			u8 DmaMode, u8 AddrCycles)
 {
 	u32 RegValue = 0U;
 
 	Xil_AssertVoid(InstancePtr != NULL);
 
-	RegValue = (u32)Cmd1 | (((u32)Cmd2 << (u32)XNANDPS8_CMD_CMD2_SHIFT) &
-			(u32)XNANDPS8_CMD_CMD2_MASK);
+	RegValue = (u32)Cmd1 | (((u32)Cmd2 << (u32)XNANDPSU_CMD_CMD2_SHIFT) &
+			(u32)XNANDPSU_CMD_CMD2_MASK);
 
-	if ((EccState != 0U) && (InstancePtr->EccMode == XNANDPS8_HWECC)) {
-		RegValue |= 1U << XNANDPS8_CMD_ECC_ON_SHIFT;
+	if ((EccState != 0U) && (InstancePtr->EccMode == XNANDPSU_HWECC)) {
+		RegValue |= 1U << XNANDPSU_CMD_ECC_ON_SHIFT;
 	}
 
-	if ((DmaMode != 0U) && (InstancePtr->DmaMode == XNANDPS8_MDMA)) {
-		RegValue |= XNANDPS8_MDMA << XNANDPS8_CMD_DMA_EN_SHIFT;
+	if ((DmaMode != 0U) && (InstancePtr->DmaMode == XNANDPSU_MDMA)) {
+		RegValue |= XNANDPSU_MDMA << XNANDPSU_CMD_DMA_EN_SHIFT;
 	}
 
 	if (AddrCycles != 0U) {
 		RegValue |= (u32)AddrCycles <<
-				(u32)XNANDPS8_CMD_ADDR_CYCLES_SHIFT;
+				(u32)XNANDPSU_CMD_ADDR_CYCLES_SHIFT;
 	}
 
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
-			XNANDPS8_CMD_OFFSET, RegValue);
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,
+			XNANDPSU_CMD_OFFSET, RegValue);
 }
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.h b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h
similarity index 61%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.h
rename to XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h
index eeebddd9..5ed7e617 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8.h
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu.h
@@ -32,17 +32,17 @@
 /*****************************************************************************/
 /**
 *
-* @file xnandps8.h
+* @file xnandpsu.h
 *
 * This file implements a driver to support Arasan NAND controller
 * present in Zynq Ultrascale Mp.
 *
 * <b>Driver Initialization</b>
 *
-* The function call XNandPs8_CfgInitialize() should be called by the application
+* The function call XNandPsu_CfgInitialize() should be called by the application
 * before any other function in the driver. The initialization function takes
 * device specific data (like device id, instance id, and base address) and
-* initializes the XNandPs8 instance with the device specific data.
+* initializes the XNandPsu instance with the device specific data.
 *
 * <b>Device Geometry</b>
 *
@@ -93,7 +93,8 @@
 * only after the erase operation is completed successfully or an error is
 * reported.
 *
-* @note
+* @note		Driver has been renamed to nandpsu after change in
+*		naming convention.
 *
 * This driver is intended to be RTOS and processor independent. It works with
 * physical addresses only. Any needs for dynamic memory management, threads,
@@ -108,46 +109,46 @@
 * 1.0   nm     05/06/2014  First release
 * 2.0   sb     01/12/2015  Removed Null checks for Buffer passed
 *			   as parameter to Read API's
-*			   - XNandPs8_Read()
-*			   - XNandPs8_ReadPage
+*			   - XNandPsu_Read()
+*			   - XNandPsu_ReadPage
 *			   Modified
-*			   - XNandPs8_SetFeature()
-*			   - XNandPs8_GetFeature()
+*			   - XNandPsu_SetFeature()
+*			   - XNandPsu_GetFeature()
 *			   and made them public.
 *			   Removed Failure Return for BCF Error check in
-*			   XNandPs8_ReadPage() and added BCH_Error counter
+*			   XNandPsu_ReadPage() and added BCH_Error counter
 *			   in the instance pointer structure.
-* 			   Added XNandPs8_Prepare_Cmd API
+* 			   Added XNandPsu_Prepare_Cmd API
 *			   Replaced
-*			   - XNandPs8_IntrStsEnable
-*			   - XNandPs8_IntrStsClear
-*			   - XNandPs8_IntrClear
-*			   - XNandPs8_SetProgramReg
-*			   with XNandPs8_WriteReg call
-*			   Modified xnandps8.c file API's with above changes.
+*			   - XNandPsu_IntrStsEnable
+*			   - XNandPsu_IntrStsClear
+*			   - XNandPsu_IntrClear
+*			   - XNandPsu_SetProgramReg
+*			   with XNandPsu_WriteReg call
+*			   Modified xnandpsu.c file API's with above changes.
 * 			   Corrected the program command for Set Feature API.
 *			   Modified
-*			   - XNandPs8_OnfiReadStatus
-*			   - XNandPs8_GetFeature
-*			   - XNandPs8_SetFeature
+*			   - XNandPsu_OnfiReadStatus
+*			   - XNandPsu_GetFeature
+*			   - XNandPsu_SetFeature
 *			   to add support for DDR mode.
 *			   Changed Convention for SLC/MLC
 *			   SLC --> HAMMING
 *			   MLC --> BCH
 *			   SlcMlc --> IsBCH
 *			   Added support for writing BBT signature and version
-*			   in page section by enabling XNANDPS8_BBT_NO_OOB.
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
 *			   Removed extra DMA mode initialization from
-*			   the XNandPs8_CfgInitialize API.
+*			   the XNandPsu_CfgInitialize API.
 *			   Modified
-*			   - XNandPs8_SetEccAddrSize
+*			   - XNandPsu_SetEccAddrSize
 *			   ECC address now is calculated based upon the
 *			   size of spare area
 *			   Modified Block Erase API, removed clearing of
 *			   packet register before erase.
 *			   Clearing Data Interface Register before
-*			   XNandPs8_OnfiReset call.
-*			   Modified XNandPs8_ChangeTimingMode API supporting
+*			   XNandPsu_OnfiReset call.
+*			   Modified XNandPsu_ChangeTimingMode API supporting
 *			   SDR and NVDDR interface for timing modes 0 to 5.
 *			   Modified Bbt Signature and Version Offset value for
 *			   Oob and No-Oob region.
@@ -155,8 +156,8 @@
 *
 ******************************************************************************/
 
-#ifndef XNANDPS8_H		/* prevent circular inclusions */
-#define XNANDPS8_H		/* by using protection macros */
+#ifndef XNANDPSU_H		/* prevent circular inclusions */
+#define XNANDPSU_H		/* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
@@ -167,131 +168,131 @@ extern "C" {
 #include <string.h>
 #include "xstatus.h"
 #include "xil_assert.h"
-#include "xnandps8_hw.h"
-#include "xnandps8_onfi.h"
+#include "xnandpsu_hw.h"
+#include "xnandpsu_onfi.h"
 #include "xil_cache.h"
 /************************** Constant Definitions *****************************/
 
-#define XNANDPS8_DEBUG
+#define XNANDPSU_DEBUG
 
-#define XNANDPS8_MAX_TARGETS		1U	/**< ce_n0, ce_n1 */
-#define XNANDPS8_MAX_PKT_SIZE		0x7FFU	/**< Max packet size */
-#define XNANDPS8_MAX_PKT_COUNT		0xFFFU	/**< Max packet count */
+#define XNANDPSU_MAX_TARGETS		1U	/**< ce_n0, ce_n1 */
+#define XNANDPSU_MAX_PKT_SIZE		0x7FFU	/**< Max packet size */
+#define XNANDPSU_MAX_PKT_COUNT		0xFFFU	/**< Max packet count */
 
-#define XNANDPS8_PAGE_SIZE_512		512U	/**< 512 bytes page */
-#define XNANDPS8_PAGE_SIZE_2K		2048U	/**< 2K bytes page */
-#define XNANDPS8_PAGE_SIZE_4K		4096U	/**< 4K bytes page */
-#define XNANDPS8_PAGE_SIZE_8K		8192U	/**< 8K bytes page */
-#define XNANDPS8_PAGE_SIZE_16K		16384U	/**< 16K bytes page */
-#define XNANDPS8_PAGE_SIZE_1K_16BIT	1024U	/**< 16-bit 2K bytes page */
-#define XNANDPS8_MAX_PAGE_SIZE		16384U	/**< Max page size supported */
+#define XNANDPSU_PAGE_SIZE_512		512U	/**< 512 bytes page */
+#define XNANDPSU_PAGE_SIZE_2K		2048U	/**< 2K bytes page */
+#define XNANDPSU_PAGE_SIZE_4K		4096U	/**< 4K bytes page */
+#define XNANDPSU_PAGE_SIZE_8K		8192U	/**< 8K bytes page */
+#define XNANDPSU_PAGE_SIZE_16K		16384U	/**< 16K bytes page */
+#define XNANDPSU_PAGE_SIZE_1K_16BIT	1024U	/**< 16-bit 2K bytes page */
+#define XNANDPSU_MAX_PAGE_SIZE		16384U	/**< Max page size supported */
 
-#define XNANDPS8_BUS_WIDTH_8		0U	/**< 8-bit bus width */
-#define XNANDPS8_BUS_WIDTH_16		1U	/**< 16-bit bus width */
+#define XNANDPSU_BUS_WIDTH_8		0U	/**< 8-bit bus width */
+#define XNANDPSU_BUS_WIDTH_16		1U	/**< 16-bit bus width */
 
-#define XNANDPS8_HAMMING		0x1U	/**< Hamming Flash */
-#define XNANDPS8_BCH			0x2U	/**< BCH Flash */
+#define XNANDPSU_HAMMING		0x1U	/**< Hamming Flash */
+#define XNANDPSU_BCH			0x2U	/**< BCH Flash */
 
-#define XNANDPS8_MAX_BLOCKS		32768U	/**< Max number of Blocks */
-#define XNANDPS8_MAX_SPARE_SIZE		0x800U	/**< Max spare bytes of a NAND
+#define XNANDPSU_MAX_BLOCKS		32768U	/**< Max number of Blocks */
+#define XNANDPSU_MAX_SPARE_SIZE		0x800U	/**< Max spare bytes of a NAND
 						  flash page of 16K */
 
-#define XNANDPS8_INTR_POLL_TIMEOUT	10000U
+#define XNANDPSU_INTR_POLL_TIMEOUT	10000U
 
-#define XNANDPS8_SDR_CLK		((u16)100U * (u16)1000U * (u16)1000U)
-#define XNANDPS8_NVDDR_CLK_0		((u16)20U * (u16)1000U * (u16)1000U)
-#define XNANDPS8_NVDDR_CLK_1		((u16)33U * (u16)1000U * (u16)1000U)
-#define XNANDPS8_NVDDR_CLK_2		((u16)50U * (u16)1000U * (u16)1000U)
-#define XNANDPS8_NVDDR_CLK_3		((u16)66U * (u16)1000U * (u16)1000U)
-#define XNANDPS8_NVDDR_CLK_4		((u16)83U * (u16)1000U * (u16)1000U)
-#define XNANDPS8_NVDDR_CLK_5		((u16)100U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_SDR_CLK		((u16)100U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_0		((u16)20U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_1		((u16)33U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_2		((u16)50U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_3		((u16)66U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_4		((u16)83U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_5		((u16)100U * (u16)1000U * (u16)1000U)
 
 /**
- * The XNandPs8_Config structure contains configuration information for NAND
+ * The XNandPsu_Config structure contains configuration information for NAND
  * controller.
  */
 typedef struct {
 	u16 DeviceId;		/**< Instance ID of NAND flash controller */
 	u32 BaseAddress;	/**< Base address of NAND flash controller */
-} XNandPs8_Config;
+} XNandPsu_Config;
 
 /**
- * The XNandPs8_DataInterface enum contains flash operating mode.
+ * The XNandPsu_DataInterface enum contains flash operating mode.
  */
 typedef enum {
-	XNANDPS8_SDR = 0U,		/**< Single Data Rate */
-	XNANDPS8_NVDDR			/**< Double Data Rate */
-} XNandPs8_DataInterface;
+	XNANDPSU_SDR = 0U,		/**< Single Data Rate */
+	XNANDPSU_NVDDR			/**< Double Data Rate */
+} XNandPsu_DataInterface;
 
 /**
- * XNandPs8_TimingMode enum contains timing modes.
+ * XNandPsu_TimingMode enum contains timing modes.
  */
 typedef enum {
-	XNANDPS8_SDR0 = 0U,
-	XNANDPS8_SDR1,
-	XNANDPS8_SDR2,
-	XNANDPS8_SDR3,
-	XNANDPS8_SDR4,
-	XNANDPS8_SDR5,
-	XNANDPS8_NVDDR0,
-	XNANDPS8_NVDDR1,
-	XNANDPS8_NVDDR2,
-	XNANDPS8_NVDDR3,
-	XNANDPS8_NVDDR4,
-	XNANDPS8_NVDDR5
-} XNandPs8_TimingMode;
+	XNANDPSU_SDR0 = 0U,
+	XNANDPSU_SDR1,
+	XNANDPSU_SDR2,
+	XNANDPSU_SDR3,
+	XNANDPSU_SDR4,
+	XNANDPSU_SDR5,
+	XNANDPSU_NVDDR0,
+	XNANDPSU_NVDDR1,
+	XNANDPSU_NVDDR2,
+	XNANDPSU_NVDDR3,
+	XNANDPSU_NVDDR4,
+	XNANDPSU_NVDDR5
+} XNandPsu_TimingMode;
 
 /**
- * The XNandPs8_SWMode enum contains the driver operating mode.
+ * The XNandPsu_SWMode enum contains the driver operating mode.
  */
 typedef enum {
-	XNANDPS8_POLLING = 0,		/**< Polling */
-	XNANDPS8_INTERRUPT		/**< Interrupt */
-} XNandPs8_SWMode;
+	XNANDPSU_POLLING = 0,		/**< Polling */
+	XNANDPSU_INTERRUPT		/**< Interrupt */
+} XNandPsu_SWMode;
 
 /**
- * The XNandPs8_DmaMode enum contains the controller MDMA mode.
+ * The XNandPsu_DmaMode enum contains the controller MDMA mode.
  */
 typedef enum {
-	XNANDPS8_PIO = 0,		/**< PIO Mode */
-	XNANDPS8_SDMA,			/**< SDMA Mode */
-	XNANDPS8_MDMA			/**< MDMA Mode */
-} XNandPs8_DmaMode;
+	XNANDPSU_PIO = 0,		/**< PIO Mode */
+	XNANDPSU_SDMA,			/**< SDMA Mode */
+	XNANDPSU_MDMA			/**< MDMA Mode */
+} XNandPsu_DmaMode;
 
 /**
- * The XNandPs8_EccMode enum contains ECC functionality.
+ * The XNandPsu_EccMode enum contains ECC functionality.
  */
 typedef enum {
-	XNANDPS8_NONE = 0,
-	XNANDPS8_HWECC,
-	XNANDPS8_EZNAND,
-	XNANDPS8_ONDIE
-} XNandPs8_EccMode;
+	XNANDPSU_NONE = 0,
+	XNANDPSU_HWECC,
+	XNANDPSU_EZNAND,
+	XNANDPSU_ONDIE
+} XNandPsu_EccMode;
 
 /**
- * The XNandPs8_BbtOption enum contains the BBT storage option.
+ * The XNandPsu_BbtOption enum contains the BBT storage option.
  */
 typedef enum {
-	XNANDPS8_BBT_OOB = 0,		/**< OOB area */
-	XNANDPS8_BBT_NO_OOB,		/**< No OOB i.e page area */
-} XNandPs8_BbtOption;
+	XNANDPSU_BBT_OOB = 0,		/**< OOB area */
+	XNANDPSU_BBT_NO_OOB,		/**< No OOB i.e page area */
+} XNandPsu_BbtOption;
 
 /**
  * Bad block table descriptor
  */
 typedef struct {
-	u32 PageOffset[XNANDPS8_MAX_TARGETS];
+	u32 PageOffset[XNANDPSU_MAX_TARGETS];
 				/**< Page offset where BBT resides */
 	u32 SigOffset;		/**< Signature offset in Spare area */
 	u32 VerOffset;		/**< Offset of BBT version */
 	u32 SigLength;		/**< Length of the signature */
 	u32 MaxBlocks;		/**< Max blocks to search for BBT */
 	char Signature[4];	/**< BBT signature */
-	u8 Version[XNANDPS8_MAX_TARGETS];
+	u8 Version[XNANDPSU_MAX_TARGETS];
 				/**< BBT version */
 	u32 Valid;		/**< BBT descriptor is valid or not */
-	XNandPs8_BbtOption Option;	/**< BBT Oob option enabled/disabled */
-} XNandPs8_BbtDesc;
+	XNandPsu_BbtOption Option;	/**< BBT Oob option enabled/disabled */
+} XNandPsu_BbtDesc;
 
 /**
  * Bad block pattern
@@ -301,10 +302,10 @@ typedef struct {
 	u32 Offset;		/**< Offset to search for specified pattern */
 	u32 Length;		/**< Number of bytes to check the pattern */
 	u8 Pattern[2];		/**< Pattern format to search for */
-} XNandPs8_BadBlockPattern;
+} XNandPsu_BadBlockPattern;
 
 /**
- * The XNandPs8_Geometry structure contains the ONFI geometry information.
+ * The XNandPsu_Geometry structure contains the ONFI geometry information.
  */
 typedef struct {
 	/*
@@ -331,10 +332,10 @@ typedef struct {
 	u32 NumPages;		/**< Total number of pages */
 	u32 NumBlocks;		/**< Total number of blocks */
 	u64 DeviceSize;		/**< Total flash size in bytes */
-} XNandPs8_Geometry;
+} XNandPsu_Geometry;
 
 /**
- * The XNandPs8_Features structure contains the ONFI features information.
+ * The XNandPsu_Features structure contains the ONFI features information.
  */
 typedef struct {
 	u32 BusWidth;
@@ -342,10 +343,10 @@ typedef struct {
 	u32 EzNand;
 	u32 OnDie;
 	u32 ExtPrmPage;
-} XNandPs8_Features;
+} XNandPsu_Features;
 
 /**
- * The XNandPs8_EccMatrix structure contains ECC features information.
+ * The XNandPsu_EccMatrix structure contains ECC features information.
  */
 typedef struct {
 	u16 PageSize;
@@ -354,10 +355,10 @@ typedef struct {
 	u8 IsBCH;
 	u16 EccAddr;
 	u16 EccSize;
-} XNandPs8_EccMatrix;
+} XNandPsu_EccMatrix;
 
 /**
- * The XNandPs8_EccCfg structure contains ECC configuration.
+ * The XNandPsu_EccCfg structure contains ECC configuration.
  */
 typedef struct {
 	u16 EccAddr;
@@ -365,36 +366,36 @@ typedef struct {
 	u16 CodeWordSize;
 	u8 NumEccBits;
 	u8 IsBCH;
-} XNandPs8_EccCfg;
+} XNandPsu_EccCfg;
 
 /**
- * The XNandPs8 structure contains the driver instance data. The user is
+ * The XNandPsu structure contains the driver instance data. The user is
  * required to allocate a variable of this type for the NAND controller.
  * A pointer to a variable of this type is then passed to the driver API
  * functions.
  */
 typedef struct {
 	u32 IsReady;		/**< Device is initialized and ready */
-	XNandPs8_Config Config;
+	XNandPsu_Config Config;
 	u16 Ecc_Stat_PerPage_flips;	/**< Ecc Correctable Error Counter for Current Page */
 	u32 Ecc_Stats_total_flips;     /**< Total Ecc Errors Corrected */
-	XNandPs8_DataInterface DataInterface;
-	XNandPs8_TimingMode TimingMode;
-	XNandPs8_SWMode Mode;		/**< Driver operating mode */
-	XNandPs8_DmaMode DmaMode;	/**< MDMA mode enabled/disabled */
-	XNandPs8_EccMode EccMode;	/**< ECC Mode */
-	XNandPs8_EccCfg EccCfg;		/**< ECC configuration */
-	XNandPs8_Geometry Geometry;	/**< Flash geometry */
-	XNandPs8_Features Features;	/**< ONFI features */
-	u8 PartialDataBuf[XNANDPS8_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
+	XNandPsu_DataInterface DataInterface;
+	XNandPsu_TimingMode TimingMode;
+	XNandPsu_SWMode Mode;		/**< Driver operating mode */
+	XNandPsu_DmaMode DmaMode;	/**< MDMA mode enabled/disabled */
+	XNandPsu_EccMode EccMode;	/**< ECC Mode */
+	XNandPsu_EccCfg EccCfg;		/**< ECC configuration */
+	XNandPsu_Geometry Geometry;	/**< Flash geometry */
+	XNandPsu_Features Features;	/**< ONFI features */
+	u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
 					/**< Partial read/write buffer */
 	/* Bad block table definitions */
-	XNandPs8_BbtDesc BbtDesc;	/**< Bad block table descriptor */
-	XNandPs8_BbtDesc BbtMirrorDesc;	/**< Mirror BBT descriptor */
-	XNandPs8_BadBlockPattern BbPattern;	/**< Bad block pattern to
+	XNandPsu_BbtDesc BbtDesc;	/**< Bad block table descriptor */
+	XNandPsu_BbtDesc BbtMirrorDesc;	/**< Mirror BBT descriptor */
+	XNandPsu_BadBlockPattern BbPattern;	/**< Bad block pattern to
 						  search */
-	u8 Bbt[XNANDPS8_MAX_BLOCKS >> 2];	/**< Bad block table array */
-} XNandPs8;
+	u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2];	/**< Bad block table array */
+} XNandPsu;
 
 /******************* Macro Definitions (Inline Functions) *******************/
 
@@ -402,112 +403,112 @@ typedef struct {
 /**
  * This macro sets the bitmask in the register.
  *
- * @param	InstancePtr is a pointer to the XNandPs8 instance of the
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
  *		controller.
  * @param	RegOffset is the register offset.
  * @param	BitMask is the bitmask.
  *
  * @note	C-style signature:
- *		void XNandPs8_SetBits(XNandPs8 *InstancePtr, u32 RegOffset,
+ *		void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset,
  *							u32 BitMask)
  *
  *****************************************************************************/
-#define XNandPs8_SetBits(InstancePtr, RegOffset, BitMask)		\
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,		\
+#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask)		\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
 		(RegOffset),						\
-	((u32)(XNandPs8_ReadReg((InstancePtr)->Config.BaseAddress,	\
+	((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,	\
 		(RegOffset)) | (BitMask))))
 
 /*****************************************************************************/
 /**
  * This macro clears the bitmask in the register.
  *
- * @param	InstancePtr is a pointer to the XNandPs8 instance of the
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
  *		controller.
  * @param	RegOffset is the register offset.
  * @param	BitMask is the bitmask.
  *
  * @note	C-style signature:
- *		void XNandPs8_ClrBits(XNandPs8 *InstancePtr, u32 RegOffset,
+ *		void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset,
  *							u32 BitMask)
  *
  *****************************************************************************/
-#define XNandPs8_ClrBits(InstancePtr, RegOffset, BitMask)		\
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,		\
+#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask)		\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
 		(RegOffset),						\
-	((u32)(XNandPs8_ReadReg((InstancePtr)->Config.BaseAddress,	\
+	((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,	\
 		(RegOffset)) & ~(BitMask))))
 
 /*****************************************************************************/
 /**
  * This macro clears and updates the bitmask in the register.
  *
- * @param	InstancePtr is a pointer to the XNandPs8 instance of the
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
  *		controller.
  * @param	RegOffset is the register offset.
  * @param	Mask is the bitmask.
  * @param	Value is the register value to write.
  *
  * @note	C-style signature:
- *		void XNandPs8_ReadModifyWrite(XNandPs8 *InstancePtr,
+ *		void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr,
  *					u32 RegOffset, u32 Mask, u32 Val)
  *
  *****************************************************************************/
-#define XNandPs8_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value)	\
-	XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,		\
+#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value)	\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
 		(RegOffset),						\
-	((u32)((u32)(XNandPs8_ReadReg((InstancePtr)->Config.BaseAddress,\
+	((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
 		(u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
 
 /*****************************************************************************/
 /**
  * This macro enables bitmask in Interrupt Signal Enable register.
  *
- * @param	InstancePtr is a pointer to the XNandPs8 instance of the
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
  *		controller.
  * @param	Mask is the bitmask.
  *
  * @note	C-style signature:
- *		void XNandPs8_IntrSigEnable(XNandPs8 *InstancePtr, u32 Mask)
+ *		void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask)
  *
  *****************************************************************************/
-#define XNandPs8_IntrSigEnable(InstancePtr, Mask)			\
-		XNandPs8_SetBits((InstancePtr),				\
-			XNANDPS8_INTR_SIG_EN_OFFSET,			\
+#define XNandPsu_IntrSigEnable(InstancePtr, Mask)			\
+		XNandPsu_SetBits((InstancePtr),				\
+			XNANDPSU_INTR_SIG_EN_OFFSET,			\
 			(Mask))
 
 /*****************************************************************************/
 /**
  * This macro clears bitmask in Interrupt Signal Enable register.
  *
- * @param	InstancePtr is a pointer to the XNandPs8 instance of the
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
  *		controller.
  * @param	Mask is the bitmask.
  *
  * @note	C-style signature:
- *		void XNandPs8_IntrSigClear(XNandPs8 *InstancePtr, u32 Mask)
+ *		void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask)
  *
  *****************************************************************************/
-#define XNandPs8_IntrSigClear(InstancePtr, Mask)			\
-		XNandPs8_ClrBits((InstancePtr),				\
-			XNANDPS8_INTR_SIG_EN_OFFSET,			\
+#define XNandPsu_IntrSigClear(InstancePtr, Mask)			\
+		XNandPsu_ClrBits((InstancePtr),				\
+			XNANDPSU_INTR_SIG_EN_OFFSET,			\
 			(Mask))
 
 /*****************************************************************************/
 /**
  * This macro enables bitmask in Interrupt Status Enable register.
  *
- * @param	InstancePtr is a pointer to the XNandPs8 instance of the
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
  *		controller.
  * @param	Mask is the bitmask.
  *
  * @note	C-style signature:
- *		void XNandPs8_IntrStsEnable(XNandPs8 *InstancePtr, u32 Mask)
+ *		void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask)
  *
  *****************************************************************************/
-#define XNandPs8_IntrStsEnable(InstancePtr, Mask)			\
-		XNandPs8_SetBits((InstancePtr),				\
-			XNANDPS8_INTR_STS_EN_OFFSET,			\
+#define XNandPsu_IntrStsEnable(InstancePtr, Mask)			\
+		XNandPsu_SetBits((InstancePtr),				\
+			XNANDPSU_INTR_STS_EN_OFFSET,			\
 			(Mask))
 
 /*****************************************************************************/
@@ -525,54 +526,54 @@ typedef struct {
 
 /************************** Function Prototypes *****************************/
 
-s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
+s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
 				u32 EffectiveAddr);
 
-s32 XNandPs8_Erase(XNandPs8 *InstancePtr, u64 Offset, u64 Length);
+s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length);
 
-s32 XNandPs8_Write(XNandPs8 *InstancePtr, u64 Offset, u64 Length,
+s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length,
 							u8 *SrcBuf);
 
-s32 XNandPs8_Read(XNandPs8 *InstancePtr, u64 Offset, u64 Length,
+s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length,
 							u8 *DestBuf);
 
-s32 XNandPs8_EraseBlock(XNandPs8 *InstancePtr, u32 Target, u32 Block);
+s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block);
 
-s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf);
+s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
 
-s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf);
+s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
 
-s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
-				XNandPs8_DataInterface NewIntf,
-				XNandPs8_TimingMode NewMode);
+s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
+				XNandPsu_DataInterface NewIntf,
+				XNandPsu_TimingMode NewMode);
 
-s32 XNandPs8_GetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
+s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 								u8 *Buf);
 
-s32 XNandPs8_SetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
+s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
 								u8 *Buf);
-void XNandPs8_EnableDmaMode(XNandPs8 *InstancePtr);
+void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr);
 
-void XNandPs8_DisableDmaMode(XNandPs8 *InstancePtr);
+void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr);
 
-void XNandPs8_EnableEccMode(XNandPs8 *InstancePtr);
+void XNandPsu_EnableEccMode(XNandPsu *InstancePtr);
 
-void XNandPs8_DisableEccMode(XNandPs8 *InstancePtr);
+void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
 
-void XNandPs8_Prepare_Cmd(XNandPs8 *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
+void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
 			u8 DmaMode, u8 AddrCycles);
 
-void XNandPs8_EnableBbtOobMode(XNandPs8 *InstancePtr);
+void XNandPsu_EnableBbtOobMode(XNandPsu *InstancePtr);
 
-void XNandPs8_DisableBbtOobMode(XNandPs8 *InstancePtr);
+void XNandPsu_DisableBbtOobMode(XNandPsu *InstancePtr);
 /*
- * XNandPs8_LookupConfig in xnandps8_sinit.c
+ * XNandPsu_LookupConfig in xnandpsu_sinit.c
  */
-XNandPs8_Config *XNandPs8_LookupConfig(u16 DeviceID);
+XNandPsu_Config *XNandPsu_LookupConfig(u16 DeviceID);
 
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* XNANDPS8_H end of protection macro */
+#endif /* XNANDPSU_H end of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_bbm.c b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.c
similarity index 72%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_bbm.c
rename to XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.c
index 5caa2b65..f01362f2 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_bbm.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.c
@@ -32,10 +32,10 @@
 /*****************************************************************************/
 /**
 *
-* @file xnandps8_bbm.c
+* @file xnandpsu_bbm.c
 *
 * This file implements the Bad Block Management (BBM) functionality.
-* See xnandps8_bbm.h for more details.
+* See xnandpsu_bbm.h for more details.
 *
 * @note		None
 *
@@ -46,7 +46,7 @@
 * ----- ----   ----------  -----------------------------------------------
 * 1.0   nm     05/06/2014  First release
 * 2.0   sb     01/12/2015  Added support for writing BBT signature and version
-*			   in page section by enabling XNANDPS8_BBT_NO_OOB.
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
 *			   Modified Bbt Signature and Version Offset value for
 *			   Oob and No-Oob region.
 * </pre>
@@ -56,8 +56,8 @@
 /***************************** Include Files *********************************/
 #include <string.h>	/**< For memcpy and memset */
 #include "xil_types.h"
-#include "xnandps8.h"
-#include "xnandps8_bbm.h"
+#include "xnandpsu.h"
+#include "xnandpsu_bbm.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -66,22 +66,22 @@
 /***************** Macros (Inline Functions) Definitions *********************/
 
 /************************** Function Prototypes ******************************/
-static s32 XNandPs8_ReadBbt(XNandPs8 *InstancePtr, u32 Target);
+static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target);
 
-static s32 XNandPs8_SearchBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
+static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 							u32 Target);
 
-static void XNandPs8_CreateBbt(XNandPs8 *InstancePtr, u32 Target);
+static void XNandPsu_CreateBbt(XNandPsu *InstancePtr, u32 Target);
 
-static void XNandPs8_ConvertBbt(XNandPs8 *InstancePtr, u8 *Buf, u32 Target);
+static void XNandPsu_ConvertBbt(XNandPsu *InstancePtr, u8 *Buf, u32 Target);
 
-static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
-				XNandPs8_BbtDesc *MirrorDesc, u32 Target);
+static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
+				XNandPsu_BbtDesc *MirrorDesc, u32 Target);
 
-static s32 XNandPs8_MarkBbt(XNandPs8* InstancePtr, XNandPs8_BbtDesc *Desc,
+static s32 XNandPsu_MarkBbt(XNandPsu* InstancePtr, XNandPsu_BbtDesc *Desc,
 							u32 Target);
 
-static s32 XNandPs8_UpdateBbt(XNandPs8 *InstancePtr, u32 Target);
+static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target);
 
 /************************** Variable Definitions *****************************/
 
@@ -90,13 +90,13 @@ static s32 XNandPs8_UpdateBbt(XNandPs8 *InstancePtr, u32 Target);
 * This function initializes the Bad Block Table(BBT) descriptors with a
 * predefined pattern for searching Bad Block Table(BBT) in flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		- NONE
 *
 ******************************************************************************/
-void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr)
+void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr)
 {
 	u32 Index;
 
@@ -106,25 +106,25 @@ void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr)
 	/*
 	 * Initialize primary Bad Block Table(BBT)
 	 */
-	for (Index = 0U; Index < XNANDPS8_MAX_TARGETS; Index++) {
+	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
 		InstancePtr->BbtDesc.PageOffset[Index] =
-						XNANDPS8_BBT_DESC_PAGE_OFFSET;
+						XNANDPSU_BBT_DESC_PAGE_OFFSET;
 	}
-	if (InstancePtr->EccMode == XNANDPS8_ONDIE) {
-		InstancePtr->BbtDesc.SigOffset = XNANDPS8_ONDIE_SIG_OFFSET;
-		InstancePtr->BbtDesc.VerOffset = XNANDPS8_ONDIE_VER_OFFSET;
+	if (InstancePtr->EccMode == XNANDPSU_ONDIE) {
+		InstancePtr->BbtDesc.SigOffset = XNANDPSU_ONDIE_SIG_OFFSET;
+		InstancePtr->BbtDesc.VerOffset = XNANDPSU_ONDIE_VER_OFFSET;
 	} else {
-		InstancePtr->BbtDesc.SigOffset = XNANDPS8_BBT_DESC_SIG_OFFSET;
-		InstancePtr->BbtDesc.VerOffset = XNANDPS8_BBT_DESC_VER_OFFSET;
+		InstancePtr->BbtDesc.SigOffset = XNANDPSU_BBT_DESC_SIG_OFFSET;
+		InstancePtr->BbtDesc.VerOffset = XNANDPSU_BBT_DESC_VER_OFFSET;
 	}
-	InstancePtr->BbtDesc.SigLength = XNANDPS8_BBT_DESC_SIG_LEN;
-	InstancePtr->BbtDesc.MaxBlocks = XNANDPS8_BBT_DESC_MAX_BLOCKS;
+	InstancePtr->BbtDesc.SigLength = XNANDPSU_BBT_DESC_SIG_LEN;
+	InstancePtr->BbtDesc.MaxBlocks = XNANDPSU_BBT_DESC_MAX_BLOCKS;
 	(void)strcpy(&InstancePtr->BbtDesc.Signature[0], "Bbt0");
-	for (Index = 0U; Index < XNANDPS8_MAX_TARGETS; Index++) {
+	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
 		InstancePtr->BbtDesc.Version[Index] = 0U;
 	}
 	InstancePtr->BbtDesc.Valid = 0U;
-	InstancePtr->BbtDesc.Option = XNANDPS8_BBT_OOB;
+	InstancePtr->BbtDesc.Option = XNANDPSU_BBT_OOB;
 
 	/*
 	 * Assuming that the flash device will have at least 4 blocks.
@@ -137,29 +137,29 @@ void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr)
 	/*
 	 * Initialize mirror Bad Block Table(BBT)
 	 */
-	for (Index = 0U; Index < XNANDPS8_MAX_TARGETS; Index++) {
+	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
 		InstancePtr->BbtMirrorDesc.PageOffset[Index] =
-						XNANDPS8_BBT_DESC_PAGE_OFFSET;
+						XNANDPSU_BBT_DESC_PAGE_OFFSET;
 	}
-	if (InstancePtr->EccMode == XNANDPS8_ONDIE) {
+	if (InstancePtr->EccMode == XNANDPSU_ONDIE) {
 		InstancePtr->BbtMirrorDesc.SigOffset =
-						XNANDPS8_ONDIE_SIG_OFFSET;
+						XNANDPSU_ONDIE_SIG_OFFSET;
 		InstancePtr->BbtMirrorDesc.VerOffset =
-						XNANDPS8_ONDIE_VER_OFFSET;
+						XNANDPSU_ONDIE_VER_OFFSET;
 	} else {
 		InstancePtr->BbtMirrorDesc.SigOffset =
-						XNANDPS8_BBT_DESC_SIG_OFFSET;
+						XNANDPSU_BBT_DESC_SIG_OFFSET;
 		InstancePtr->BbtMirrorDesc.VerOffset =
-						XNANDPS8_BBT_DESC_VER_OFFSET;
+						XNANDPSU_BBT_DESC_VER_OFFSET;
 	}
-	InstancePtr->BbtMirrorDesc.SigLength = XNANDPS8_BBT_DESC_SIG_LEN;
-	InstancePtr->BbtMirrorDesc.MaxBlocks = XNANDPS8_BBT_DESC_MAX_BLOCKS;
+	InstancePtr->BbtMirrorDesc.SigLength = XNANDPSU_BBT_DESC_SIG_LEN;
+	InstancePtr->BbtMirrorDesc.MaxBlocks = XNANDPSU_BBT_DESC_MAX_BLOCKS;
 	(void)strcpy(&InstancePtr->BbtMirrorDesc.Signature[0], "1tbB");
-	for (Index = 0U; Index < XNANDPS8_MAX_TARGETS; Index++) {
+	for (Index = 0U; Index < XNANDPSU_MAX_TARGETS; Index++) {
 		InstancePtr->BbtMirrorDesc.Version[Index] = 0U;
 	}
 	InstancePtr->BbtMirrorDesc.Valid = 0U;
-	InstancePtr->BbtMirrorDesc.Option = XNANDPS8_BBT_OOB;
+	InstancePtr->BbtMirrorDesc.Option = XNANDPSU_BBT_OOB;
 
 	/*
 	 * Assuming that the flash device will have at least 4 blocks.
@@ -174,20 +174,20 @@ void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr)
 	 */
 	if (InstancePtr->Geometry.BytesPerPage > 512U) {
 		/* For flash page size > 512 bytes */
-		InstancePtr->BbPattern.Options = XNANDPS8_BBT_SCAN_2ND_PAGE;
+		InstancePtr->BbPattern.Options = XNANDPSU_BBT_SCAN_2ND_PAGE;
 		InstancePtr->BbPattern.Offset =
-			XNANDPS8_BB_PTRN_OFF_LARGE_PAGE;
+			XNANDPSU_BB_PTRN_OFF_LARGE_PAGE;
 		InstancePtr->BbPattern.Length =
-			XNANDPS8_BB_PTRN_LEN_LARGE_PAGE;
+			XNANDPSU_BB_PTRN_LEN_LARGE_PAGE;
 	} else {
-		InstancePtr->BbPattern.Options = XNANDPS8_BBT_SCAN_2ND_PAGE;
+		InstancePtr->BbPattern.Options = XNANDPSU_BBT_SCAN_2ND_PAGE;
 		InstancePtr->BbPattern.Offset =
-			XNANDPS8_BB_PTRN_OFF_SML_PAGE;
+			XNANDPSU_BB_PTRN_OFF_SML_PAGE;
 		InstancePtr->BbPattern.Length =
-			XNANDPS8_BB_PTRN_LEN_SML_PAGE;
+			XNANDPSU_BB_PTRN_LEN_SML_PAGE;
 	}
-	for(Index = 0U; Index < XNANDPS8_BB_PTRN_LEN_LARGE_PAGE; Index++) {
-		InstancePtr->BbPattern.Pattern[Index] = XNANDPS8_BB_PATTERN;
+	for(Index = 0U; Index < XNANDPSU_BB_PTRN_LEN_LARGE_PAGE; Index++) {
+		InstancePtr->BbPattern.Pattern[Index] = XNANDPSU_BB_PATTERN;
 	}
 }
 
@@ -196,13 +196,13 @@ void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr)
 * This function scans the NAND flash for factory marked bad blocks and creates
 * a RAM based Bad Block Table(BBT).
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		- NONE
 *
 ******************************************************************************/
-static void XNandPs8_CreateBbt(XNandPs8 *InstancePtr, u32 Target)
+static void XNandPsu_CreateBbt(XNandPsu *InstancePtr, u32 Target)
 {
 	u32 BlockIndex;
 	u32 PageIndex;
@@ -211,7 +211,7 @@ static void XNandPs8_CreateBbt(XNandPs8 *InstancePtr, u32 Target)
 	u8 BlockShift;
 	u32 NumPages;
 	u32 Page;
-	u8 Buf[XNANDPS8_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
+	u8 Buf[XNANDPSU_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
 	u32 StartBlock = Target * InstancePtr->Geometry.NumTargetBlocks;
 	u32 NumBlocks = InstancePtr->Geometry.NumTargetBlocks;
 	s32 Status;
@@ -219,7 +219,7 @@ static void XNandPs8_CreateBbt(XNandPs8 *InstancePtr, u32 Target)
 	/*
 	 * Number of pages to search for bad block pattern
 	 */
-	if ((InstancePtr->BbPattern.Options & XNANDPS8_BBT_SCAN_2ND_PAGE) != 0U)
+	if ((InstancePtr->BbPattern.Options & XNANDPSU_BBT_SCAN_2ND_PAGE) != 0U)
 	{
 		NumPages = 2U;
 	} else {
@@ -233,23 +233,23 @@ static void XNandPs8_CreateBbt(XNandPs8 *InstancePtr, u32 Target)
 		/*
 		 * Block offset in Bad Block Table(BBT) entry
 		 */
-		BlockOffset = BlockIndex >> XNANDPS8_BBT_BLOCK_SHIFT;
+		BlockOffset = BlockIndex >> XNANDPSU_BBT_BLOCK_SHIFT;
 		/*
 		 * Block shift value in the byte
 		 */
-		BlockShift = XNandPs8_BbtBlockShift(BlockIndex);
+		BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
 		Page = BlockIndex * InstancePtr->Geometry.PagesPerBlock;
 		/*
 		 * Search for the bad block pattern
 		 */
 		for(PageIndex = 0U; PageIndex < NumPages; PageIndex++) {
-			Status = XNandPs8_ReadSpareBytes(InstancePtr,
+			Status = XNandPsu_ReadSpareBytes(InstancePtr,
 					(Page + PageIndex), &Buf[0]);
 
 			if (Status != XST_SUCCESS) {
 				/* Marking as bad block */
 				InstancePtr->Bbt[BlockOffset] |=
-					(u8)(XNANDPS8_BLOCK_FACTORY_BAD <<
+					(u8)(XNANDPSU_BLOCK_FACTORY_BAD <<
 					 BlockShift);
 				break;
 			}
@@ -266,7 +266,7 @@ static void XNandPs8_CreateBbt(XNandPs8 *InstancePtr, u32 Target)
 					/* Bad block found */
 					InstancePtr->Bbt[BlockOffset] |=
 						(u8)
-						(XNANDPS8_BLOCK_FACTORY_BAD <<
+						(XNANDPSU_BLOCK_FACTORY_BAD <<
 						 BlockShift);
 					break;
 				}
@@ -281,14 +281,14 @@ static void XNandPs8_CreateBbt(XNandPs8 *InstancePtr, u32 Target)
 * scans the flash for detecting factory marked bad blocks and creates a bad
 * block table and write the Bad Block Table(BBT) into the flash.
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
 ******************************************************************************/
-s32 XNandPs8_ScanBbt(XNandPs8 *InstancePtr)
+s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr)
 {
 	s32 Status;
 	u32 Index;
@@ -301,20 +301,20 @@ s32 XNandPs8_ScanBbt(XNandPs8 *InstancePtr)
 	 * Zero the RAM based Bad Block Table(BBT) entries
 	 */
 	BbtLen = InstancePtr->Geometry.NumBlocks >>
-					XNANDPS8_BBT_BLOCK_SHIFT;
+					XNANDPSU_BBT_BLOCK_SHIFT;
 	memset(&InstancePtr->Bbt[0], 0, BbtLen);
 
 	for (Index = 0U; Index < InstancePtr->Geometry.NumTargets; Index++) {
 
-		if (XNandPs8_ReadBbt(InstancePtr, Index) != XST_SUCCESS) {
+		if (XNandPsu_ReadBbt(InstancePtr, Index) != XST_SUCCESS) {
 			/*
 			 * Create memory based Bad Block Table(BBT)
 			 */
-			XNandPs8_CreateBbt(InstancePtr, Index);
+			XNandPsu_CreateBbt(InstancePtr, Index);
 			/*
 			 * Write the Bad Block Table(BBT) to the flash
 			 */
-			Status = XNandPs8_WriteBbt(InstancePtr,
+			Status = XNandPsu_WriteBbt(InstancePtr,
 					&InstancePtr->BbtDesc,
 					&InstancePtr->BbtMirrorDesc, Index);
 			if (Status != XST_SUCCESS) {
@@ -323,7 +323,7 @@ s32 XNandPs8_ScanBbt(XNandPs8 *InstancePtr)
 			/*
 			 * Write the Mirror Bad Block Table(BBT) to the flash
 			 */
-			Status = XNandPs8_WriteBbt(InstancePtr,
+			Status = XNandPsu_WriteBbt(InstancePtr,
 					&InstancePtr->BbtMirrorDesc,
 					&InstancePtr->BbtDesc, Index);
 			if (Status != XST_SUCCESS) {
@@ -333,13 +333,13 @@ s32 XNandPs8_ScanBbt(XNandPs8 *InstancePtr)
 			 * Mark the blocks containing Bad Block Table
 			 * (BBT) as Reserved
 			 */
-			Status = XNandPs8_MarkBbt(InstancePtr,
+			Status = XNandPsu_MarkBbt(InstancePtr,
 							&InstancePtr->BbtDesc,
 							Index);
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
-			Status = XNandPs8_MarkBbt(InstancePtr,
+			Status = XNandPsu_MarkBbt(InstancePtr,
 						&InstancePtr->BbtMirrorDesc,
 							Index);
 			if (Status != XST_SUCCESS) {
@@ -358,14 +358,14 @@ Out:
 * This function converts the Bad Block Table(BBT) read from the flash to the
 * RAM based Bad Block Table(BBT).
 *
-* @param	InstancePtr is a pointer to the XNandPs8 instance.
+* @param	InstancePtr is a pointer to the XNandPsu instance.
 * @param	Buf is the buffer which contains BBT read from flash.
 *
 * @return
 *		- NONE.
 *
 ******************************************************************************/
-static void XNandPs8_ConvertBbt(XNandPs8 *InstancePtr, u8 *Buf, u32 Target)
+static void XNandPsu_ConvertBbt(XNandPsu *InstancePtr, u8 *Buf, u32 Target)
 {
 	u32 BlockOffset;
 	u8 BlockShift;
@@ -373,7 +373,7 @@ static void XNandPs8_ConvertBbt(XNandPs8 *InstancePtr, u8 *Buf, u32 Target)
 	u8 BlockType;
 	u32 BlockIndex;
 	u32 BbtLen = InstancePtr->Geometry.NumTargetBlocks >>
-					XNANDPS8_BBT_BLOCK_SHIFT;
+					XNANDPSU_BBT_BLOCK_SHIFT;
 	u32 StartBlock = Target * InstancePtr->Geometry.NumTargetBlocks;
 
 	for(BlockOffset = StartBlock; BlockOffset < (StartBlock + BbtLen);
@@ -386,30 +386,30 @@ static void XNandPs8_ConvertBbt(XNandPs8 *InstancePtr, u8 *Buf, u32 Target)
 		/*
 		 * Loop through the every 4 blocks in the bitmap
 		 */
-		for(BlockIndex = 0U; BlockIndex < XNANDPS8_BBT_ENTRY_NUM_BLOCKS;
+		for(BlockIndex = 0U; BlockIndex < XNANDPSU_BBT_ENTRY_NUM_BLOCKS;
 				BlockIndex++) {
-			BlockShift = XNandPs8_BbtBlockShift(BlockIndex);
+			BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
 			BlockType = (u8) ((Data >> BlockShift) &
-				XNANDPS8_BLOCK_TYPE_MASK);
+				XNANDPSU_BLOCK_TYPE_MASK);
 			switch(BlockType) {
-				case XNANDPS8_FLASH_BLOCK_FAC_BAD:
+				case XNANDPSU_FLASH_BLOCK_FAC_BAD:
 					/* Factory bad block */
 					InstancePtr->Bbt[BlockOffset] |=
 						(u8)
-						(XNANDPS8_BLOCK_FACTORY_BAD <<
+						(XNANDPSU_BLOCK_FACTORY_BAD <<
 						BlockShift);
 					break;
-				case XNANDPS8_FLASH_BLOCK_RESERVED:
+				case XNANDPSU_FLASH_BLOCK_RESERVED:
 					/* Reserved block */
 					InstancePtr->Bbt[BlockOffset] |=
 						(u8)
-						(XNANDPS8_BLOCK_RESERVED <<
+						(XNANDPSU_BLOCK_RESERVED <<
 						BlockShift);
 					break;
-				case XNANDPS8_FLASH_BLOCK_BAD:
+				case XNANDPSU_FLASH_BLOCK_BAD:
 					/* Bad block due to wear */
 					InstancePtr->Bbt[BlockOffset] |=
-						(u8)(XNANDPS8_BLOCK_BAD <<
+						(u8)(XNANDPSU_BLOCK_BAD <<
 						BlockShift);
 					break;
 				default:
@@ -427,16 +427,16 @@ static void XNandPs8_ConvertBbt(XNandPs8 *InstancePtr, u8 *Buf, u32 Target)
 * This function searches the Bad Bloock Table(BBT) in flash and loads into the
 * memory based Bad Block Table(BBT).
 *
-* @param	InstancePtr is the pointer to the XNandPs8 instance.
+* @param	InstancePtr is the pointer to the XNandPsu instance.
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
 ******************************************************************************/
-static s32 XNandPs8_ReadBbt(XNandPs8 *InstancePtr, u32 Target)
+static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target)
 {
 	u64 Offset;
-	u8 Buf[XNANDPS8_BBT_BUF_LENGTH]
+	u8 Buf[XNANDPSU_BBT_BUF_LENGTH]
 					 __attribute__ ((aligned(64))) = {0U};
 	s32 Status1;
 	s32 Status2;
@@ -444,22 +444,22 @@ static s32 XNandPs8_ReadBbt(XNandPs8 *InstancePtr, u32 Target)
 	u32 BufLen;
 	u8 * BufPtr = Buf;
 
-	XNandPs8_BbtDesc *Desc = &InstancePtr->BbtDesc;
-	XNandPs8_BbtDesc *MirrorDesc = &InstancePtr->BbtMirrorDesc;
-	BufLen = XNANDPS8_BBT_BUF_LENGTH;
+	XNandPsu_BbtDesc *Desc = &InstancePtr->BbtDesc;
+	XNandPsu_BbtDesc *MirrorDesc = &InstancePtr->BbtMirrorDesc;
+	BufLen = XNANDPSU_BBT_BUF_LENGTH;
 	/*
 	 * Search the Bad Block Table(BBT) in flash
 	 */
-	Status1 = XNandPs8_SearchBbt(InstancePtr, Desc, Target);
-	Status2 = XNandPs8_SearchBbt(InstancePtr, MirrorDesc, Target);
+	Status1 = XNandPsu_SearchBbt(InstancePtr, Desc, Target);
+	Status2 = XNandPsu_SearchBbt(InstancePtr, MirrorDesc, Target);
 	if ((Status1 != XST_SUCCESS) && (Status2 != XST_SUCCESS)) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Bad block table not found\r\n",__func__);
 #endif
 		Status = XST_FAILURE;
 		goto Out;
 	}
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 	xil_printf("%s: Bad block table found\r\n",__func__);
 #endif
 	/*
@@ -472,26 +472,26 @@ static s32 XNandPs8_ReadBbt(XNandPs8 *InstancePtr, u32 Target)
 		if (Desc->Version[Target] > MirrorDesc->Version[Target]) {
 			Offset = (u64)Desc->PageOffset[Target] *
 				(u64)InstancePtr->Geometry.BytesPerPage;
-			Status = XNandPs8_Read(InstancePtr, Offset, BufLen,
+			Status = XNandPsu_Read(InstancePtr, Offset, BufLen,
 								&BufPtr[0]);
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
 
-			if (Desc->Option == XNANDPS8_BBT_NO_OOB){
+			if (Desc->Option == XNANDPSU_BBT_NO_OOB){
 				BufPtr = BufPtr + Desc->VerOffset +
-						XNANDPS8_BBT_VERSION_LENGTH;
+						XNANDPSU_BBT_VERSION_LENGTH;
 			}
 			/*
 			 * Convert flash BBT to memory based BBT
 			 */
-			XNandPs8_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+			XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
 			MirrorDesc->Version[Target] = Desc->Version[Target];
 
 			/*
 			 * Write the BBT to Mirror BBT location in flash
 			 */
-			Status = XNandPs8_WriteBbt(InstancePtr, MirrorDesc,
+			Status = XNandPsu_WriteBbt(InstancePtr, MirrorDesc,
 							Desc, Target);
 			if (Status != XST_SUCCESS) {
 				goto Out;
@@ -500,25 +500,25 @@ static s32 XNandPs8_ReadBbt(XNandPs8 *InstancePtr, u32 Target)
 						MirrorDesc->Version[Target]) {
 			Offset = (u64)MirrorDesc->PageOffset[Target] *
 				(u64)InstancePtr->Geometry.BytesPerPage;
-			Status = XNandPs8_Read(InstancePtr, Offset, BufLen,
+			Status = XNandPsu_Read(InstancePtr, Offset, BufLen,
 								&BufPtr[0]);
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
-			if(Desc->Option == XNANDPS8_BBT_NO_OOB){
+			if(Desc->Option == XNANDPSU_BBT_NO_OOB){
 				BufPtr = BufPtr + Desc->VerOffset +
-						XNANDPS8_BBT_VERSION_LENGTH;
+						XNANDPSU_BBT_VERSION_LENGTH;
 			}
 			/*
 			 * Convert flash BBT to memory based BBT
 			 */
-			XNandPs8_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+			XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
 			Desc->Version[Target] = MirrorDesc->Version[Target];
 
 			/*
 			 * Write the Mirror BBT to BBT location in flash
 			 */
-			Status = XNandPs8_WriteBbt(InstancePtr, Desc,
+			Status = XNandPsu_WriteBbt(InstancePtr, Desc,
 							MirrorDesc, Target);
 			if (Status != XST_SUCCESS) {
 				goto Out;
@@ -527,21 +527,21 @@ static s32 XNandPs8_ReadBbt(XNandPs8 *InstancePtr, u32 Target)
 			/* Both are up-to-date */
 			Offset = (u64)Desc->PageOffset[Target] *
 				(u64)InstancePtr->Geometry.BytesPerPage;
-			Status = XNandPs8_Read(InstancePtr, Offset, BufLen,
+			Status = XNandPsu_Read(InstancePtr, Offset, BufLen,
 								&BufPtr[0]);
 			if (Status != XST_SUCCESS) {
 				goto Out;
 			}
 
-			if(Desc->Option == XNANDPS8_BBT_NO_OOB){
+			if(Desc->Option == XNANDPSU_BBT_NO_OOB){
 				BufPtr = BufPtr + Desc->VerOffset +
-						XNANDPS8_BBT_VERSION_LENGTH;
+						XNANDPSU_BBT_VERSION_LENGTH;
 			}
 
 			/*
 			 * Convert flash BBT to memory based BBT
 			 */
-			XNandPs8_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+			XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
 		}
 	} else if (Desc->Valid != 0U) {
 		/*
@@ -549,24 +549,24 @@ static s32 XNandPs8_ReadBbt(XNandPs8 *InstancePtr, u32 Target)
 		 */
 		Offset = (u64)Desc->PageOffset[Target] *
 			(u64)InstancePtr->Geometry.BytesPerPage;
-		Status = XNandPs8_Read(InstancePtr, Offset, BufLen, &BufPtr[0]);
+		Status = XNandPsu_Read(InstancePtr, Offset, BufLen, &BufPtr[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
-		if(Desc->Option == XNANDPS8_BBT_NO_OOB){
+		if(Desc->Option == XNANDPSU_BBT_NO_OOB){
 			BufPtr = BufPtr + Desc->VerOffset +
-				XNANDPS8_BBT_VERSION_LENGTH;
+				XNANDPSU_BBT_VERSION_LENGTH;
 		}
 		/*
 		 * Convert flash BBT to memory based BBT
 		 */
-		XNandPs8_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+		XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
 		MirrorDesc->Version[Target] = Desc->Version[Target];
 
 		/*
 		 * Write the BBT to Mirror BBT location in flash
 		 */
-		Status = XNandPs8_WriteBbt(InstancePtr, MirrorDesc, Desc,
+		Status = XNandPsu_WriteBbt(InstancePtr, MirrorDesc, Desc,
 								Target);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -577,25 +577,25 @@ static s32 XNandPs8_ReadBbt(XNandPs8 *InstancePtr, u32 Target)
 		 */
 		Offset = (u64)MirrorDesc->PageOffset[Target] *
 			(u64)InstancePtr->Geometry.BytesPerPage;
-		Status = XNandPs8_Read(InstancePtr, Offset, BufLen, &BufPtr[0]);
+		Status = XNandPsu_Read(InstancePtr, Offset, BufLen, &BufPtr[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
-		if(Desc->Option == XNANDPS8_BBT_NO_OOB){
+		if(Desc->Option == XNANDPSU_BBT_NO_OOB){
 			BufPtr = BufPtr + Desc->VerOffset +
-				XNANDPS8_BBT_VERSION_LENGTH;
+				XNANDPSU_BBT_VERSION_LENGTH;
 		}
 
 		/*
 		 * Convert flash BBT to memory based BBT
 		 */
-		XNandPs8_ConvertBbt(InstancePtr, &BufPtr[0], Target);
+		XNandPsu_ConvertBbt(InstancePtr, &BufPtr[0], Target);
 		Desc->Version[Target] = MirrorDesc->Version[Target];
 
 		/*
 		 * Write the Mirror BBT to BBT location in flash
 		 */
-		Status = XNandPs8_WriteBbt(InstancePtr, Desc, MirrorDesc,
+		Status = XNandPsu_WriteBbt(InstancePtr, Desc, MirrorDesc,
 								Target);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -611,7 +611,7 @@ Out:
 /**
 * This function searches the BBT in flash.
 *
-* @param	InstancePtr is the pointer to the XNandPs8 instance.
+* @param	InstancePtr is the pointer to the XNandPsu instance.
 * @param	Desc is the BBT descriptor pattern to search.
 *
 * @return
@@ -619,7 +619,7 @@ Out:
 *		- XST_FAILURE if fail.
 *
 ******************************************************************************/
-static s32 XNandPs8_SearchBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
+static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
 								u32 Target)
 {
 	u32 StartBlock;
@@ -628,7 +628,7 @@ static s32 XNandPs8_SearchBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 	u32 MaxBlocks;
 	u32 PageOff;
 	u32 SigLength;
-	u8 Buf[XNANDPS8_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
+	u8 Buf[XNANDPSU_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
 	u32 Block;
 	u32 Offset;
 	s32 Status;
@@ -648,12 +648,12 @@ static s32 XNandPs8_SearchBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 		PageOff = (StartBlock - Block) *
 			InstancePtr->Geometry.PagesPerBlock;
 
-		if(Desc->Option == XNANDPS8_BBT_NO_OOB){
+		if(Desc->Option == XNANDPSU_BBT_NO_OOB){
 			BlockOff = (u64)PageOff * (u64)InstancePtr->Geometry.BytesPerPage;
-			Status = XNandPs8_Read(InstancePtr, BlockOff,
+			Status = XNandPsu_Read(InstancePtr, BlockOff,
 				Desc->SigLength + Desc->SigOffset , &Buf[0]);
 		}else{
-			Status = XNandPs8_ReadSpareBytes(InstancePtr, PageOff, &Buf[0]);
+			Status = XNandPsu_ReadSpareBytes(InstancePtr, PageOff, &Buf[0]);
 		}
 		if (Status != XST_SUCCESS) {
 			continue;
@@ -692,7 +692,7 @@ Out:
 /**
 * This function writes Bad Block Table(BBT) from RAM to flash.
 *
-* @param	InstancePtr is the pointer to the XNandPs8 instance.
+* @param	InstancePtr is the pointer to the XNandPsu instance.
 * @param	Desc is the BBT descriptor to be written to flash.
 * @param	MirrorDesc is the mirror BBT descriptor.
 *
@@ -701,17 +701,17 @@ Out:
 *		- XST_FAILURE if fail.
 *
 ******************************************************************************/
-static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
-				XNandPs8_BbtDesc *MirrorDesc, u32 Target)
+static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
+				XNandPsu_BbtDesc *MirrorDesc, u32 Target)
 {
 	u64 Offset;
 	u32 Block = {0U};
 	u32 EndBlock = ((Target + (u32)1) *
 			InstancePtr->Geometry.NumTargetBlocks) - (u32)1;
-	u8 Buf[XNANDPS8_BBT_BUF_LENGTH]
+	u8 Buf[XNANDPSU_BBT_BUF_LENGTH]
 					 __attribute__ ((aligned(64))) = {0U};
-	u32 BufLen = XNANDPS8_BBT_BUF_LENGTH;
-	u8 SpareBuf[XNANDPS8_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
+	u32 BufLen = XNANDPSU_BBT_BUF_LENGTH;
+	u8 SpareBuf[XNANDPSU_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
 	u8 Mask[4] = {0x00U, 0x01U, 0x02U, 0x03U};
 	u8 Data;
 	u32 BlockOffset;
@@ -721,7 +721,7 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 	u32 Index;
 	u8 BlockType;
 	u32 BbtLen = InstancePtr->Geometry.NumBlocks >>
-						XNANDPS8_BBT_BLOCK_SHIFT;
+						XNANDPSU_BBT_BLOCK_SHIFT;
 	u8* BufPtr = Buf;
 	/*
 	 * Find a valid block to write the Bad Block Table(BBT)
@@ -729,14 +729,14 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 	if ((!Desc->Valid) != 0U) {
 		for(Index = 0U; Index < Desc->MaxBlocks; Index++) {
 			Block  = (EndBlock - Index);
-			BlockOffset = Block >> XNANDPS8_BBT_BLOCK_SHIFT;
-			BlockShift = XNandPs8_BbtBlockShift(Block);
+			BlockOffset = Block >> XNANDPSU_BBT_BLOCK_SHIFT;
+			BlockShift = XNandPsu_BbtBlockShift(Block);
 			BlockType = (InstancePtr->Bbt[BlockOffset] >>
-					BlockShift) & XNANDPS8_BLOCK_TYPE_MASK;
+					BlockShift) & XNANDPSU_BLOCK_TYPE_MASK;
 			switch(BlockType)
 			{
-				case XNANDPS8_BLOCK_BAD:
-				case XNANDPS8_BLOCK_FACTORY_BAD:
+				case XNANDPSU_BLOCK_BAD:
+				case XNANDPSU_BLOCK_FACTORY_BAD:
 					continue;
 				default:
 					/* Good Block */
@@ -756,7 +756,7 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 		 * Block not found for writing Bad Block Table(BBT)
 		 */
 		if (Index >= Desc->MaxBlocks) {
-#ifdef XNANDPS8_DEBUG
+#ifdef XNANDPSU_DEBUG
 		xil_printf("%s: Blocks unavailable for writing BBT\r\n",
 								__func__);
 #endif
@@ -772,8 +772,8 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 	 */
 	memset(Buf, 0xff, BufLen);
 
-	if(Desc->Option == XNANDPS8_BBT_NO_OOB){
-		BufPtr = BufPtr + Desc->VerOffset + XNANDPS8_BBT_VERSION_LENGTH;
+	if(Desc->Option == XNANDPSU_BBT_NO_OOB){
+		BufPtr = BufPtr + Desc->VerOffset + XNANDPSU_BBT_VERSION_LENGTH;
 	}
 	/*
 	 * Loop through the number of blocks
@@ -783,24 +783,24 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 		/*
 		 * Calculate the bit mask for 4 blocks at a time in loop
 		 */
-		for(BlockIndex = 0U; BlockIndex < XNANDPS8_BBT_ENTRY_NUM_BLOCKS;
+		for(BlockIndex = 0U; BlockIndex < XNANDPSU_BBT_ENTRY_NUM_BLOCKS;
 				BlockIndex++) {
-			BlockShift = XNandPs8_BbtBlockShift(BlockIndex);
+			BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
 			BufPtr[BlockOffset] &= ~(Mask[Data &
-					XNANDPS8_BLOCK_TYPE_MASK] <<
+					XNANDPSU_BLOCK_TYPE_MASK] <<
 					BlockShift);
-			Data >>= XNANDPS8_BBT_BLOCK_SHIFT;
+			Data >>= XNANDPSU_BBT_BLOCK_SHIFT;
 		}
 	}
 	/*
 	 * Write the Bad Block Table(BBT) to flash
 	 */
-	Status = XNandPs8_EraseBlock(InstancePtr, 0U, Block);
+	Status = XNandPsu_EraseBlock(InstancePtr, 0U, Block);
 	if (Status != XST_SUCCESS) {
 		goto Out;
 	}
 
-	if(Desc->Option == XNANDPS8_BBT_NO_OOB){
+	if(Desc->Option == XNANDPSU_BBT_NO_OOB){
 		/*
 		 * Copy the signature and version to the Buffer
 		 */
@@ -812,7 +812,7 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 		 */
 		Offset = (u64)Desc->PageOffset[Target] *
 				(u64)InstancePtr->Geometry.BytesPerPage;
-		Status = XNandPs8_Write(InstancePtr, Offset, BufLen, &Buf[0]);
+		Status = XNandPsu_Write(InstancePtr, Offset, BufLen, &Buf[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
@@ -822,7 +822,7 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 		 */
 		Offset = (u64)Desc->PageOffset[Target] *
 				(u64)InstancePtr->Geometry.BytesPerPage;
-		Status = XNandPs8_Write(InstancePtr, Offset, BbtLen, &Buf[0]);
+		Status = XNandPsu_Write(InstancePtr, Offset, BbtLen, &Buf[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
@@ -830,7 +830,7 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 		 * Write the signature and version in the spare data area
 		 */
 		memset(SpareBuf, 0xff, InstancePtr->Geometry.SpareBytesPerPage);
-		Status = XNandPs8_ReadSpareBytes(InstancePtr, Desc->PageOffset[Target],
+		Status = XNandPsu_ReadSpareBytes(InstancePtr, Desc->PageOffset[Target],
 				&SpareBuf[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -840,7 +840,7 @@ static s32 XNandPs8_WriteBbt(XNandPs8 *InstancePtr, XNandPs8_BbtDesc *Desc,
 							Desc->SigLength);
 		memcpy(SpareBuf + Desc->VerOffset, &Desc->Version[Target], 1U);
 
-		Status = XNandPs8_WriteSpareBytes(InstancePtr,
+		Status = XNandPsu_WriteSpareBytes(InstancePtr,
 				Desc->PageOffset[Target], &SpareBuf[0]);
 		if (Status != XST_SUCCESS) {
 			goto Out;
@@ -857,13 +857,13 @@ Out:
 * This function updates the primary and mirror Bad Block Table(BBT) in the
 * flash.
 *
-* @param	InstancePtr is the pointer to the XNandPs8 instance.
+* @param	InstancePtr is the pointer to the XNandPsu instance.
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
 ******************************************************************************/
-static s32 XNandPs8_UpdateBbt(XNandPs8 *InstancePtr, u32 Target)
+static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target)
 {
 	s32 Status;
 	u8 Version;
@@ -881,7 +881,7 @@ static s32 XNandPs8_UpdateBbt(XNandPs8 *InstancePtr, u32 Target)
 	/*
 	 * Update the primary Bad Block Table(BBT) in flash
 	 */
-	Status = XNandPs8_WriteBbt(InstancePtr, &InstancePtr->BbtDesc,
+	Status = XNandPsu_WriteBbt(InstancePtr, &InstancePtr->BbtDesc,
 						&InstancePtr->BbtMirrorDesc,
 						Target);
 	if (Status != XST_SUCCESS) {
@@ -891,7 +891,7 @@ static s32 XNandPs8_UpdateBbt(XNandPs8 *InstancePtr, u32 Target)
 	/*
 	 * Update the mirrored Bad Block Table(BBT) in flash
 	 */
-	Status = XNandPs8_WriteBbt(InstancePtr, &InstancePtr->BbtMirrorDesc,
+	Status = XNandPsu_WriteBbt(InstancePtr, &InstancePtr->BbtMirrorDesc,
 						&InstancePtr->BbtDesc,
 						Target);
 	if (Status != XST_SUCCESS) {
@@ -908,14 +908,14 @@ Out:
 * This function marks the block containing Bad Block Table as reserved
 * and updates the BBT.
 *
-* @param	InstancePtr is the pointer to the XNandPs8 instance.
+* @param	InstancePtr is the pointer to the XNandPsu instance.
 * @param	Desc is the BBT descriptor pointer.
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if fail.
 *
 ******************************************************************************/
-static s32 XNandPs8_MarkBbt(XNandPs8* InstancePtr, XNandPs8_BbtDesc *Desc,
+static s32 XNandPsu_MarkBbt(XNandPsu* InstancePtr, XNandPsu_BbtDesc *Desc,
 								u32 Target)
 {
 	u32 BlockIndex;
@@ -935,10 +935,10 @@ static s32 XNandPs8_MarkBbt(XNandPs8* InstancePtr, XNandPs8_BbtDesc *Desc,
 
 	for(Index = 0U; Index < Desc->MaxBlocks; Index++) {
 
-		BlockOffset = BlockIndex >> XNANDPS8_BBT_BLOCK_SHIFT;
-		BlockShift = XNandPs8_BbtBlockShift(BlockIndex);
+		BlockOffset = BlockIndex >> XNANDPSU_BBT_BLOCK_SHIFT;
+		BlockShift = XNandPsu_BbtBlockShift(BlockIndex);
 		OldVal = InstancePtr->Bbt[BlockOffset];
-		NewVal = (u8) (OldVal | (XNANDPS8_BLOCK_RESERVED <<
+		NewVal = (u8) (OldVal | (XNANDPSU_BLOCK_RESERVED <<
 							BlockShift));
 		InstancePtr->Bbt[BlockOffset] = NewVal;
 
@@ -952,7 +952,7 @@ static s32 XNandPs8_MarkBbt(XNandPs8* InstancePtr, XNandPs8_BbtDesc *Desc,
 	 * Update the BBT to flash
 	 */
 	if (UpdateBbt != 0U) {
-		Status = XNandPs8_UpdateBbt(InstancePtr, Target);
+		Status = XNandPsu_UpdateBbt(InstancePtr, Target);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
@@ -968,7 +968,7 @@ Out:
 *
 * This function checks whether a block is bad or not.
 *
-* @param	InstancePtr is the pointer to the XNandPs8 instance.
+* @param	InstancePtr is the pointer to the XNandPsu instance.
 *
 * @param	Block is the block number.
 *
@@ -977,7 +977,7 @@ Out:
 *		- XST_FAILURE if fail.
 *
 ******************************************************************************/
-s32 XNandPs8_IsBlockBad(XNandPs8 *InstancePtr, u32 Block)
+s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block)
 {
 	u8 Data;
 	u8 BlockShift;
@@ -989,13 +989,13 @@ s32 XNandPs8_IsBlockBad(XNandPs8 *InstancePtr, u32 Block)
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(Block < InstancePtr->Geometry.NumBlocks);
 
-	BlockOffset = Block >> XNANDPS8_BBT_BLOCK_SHIFT;
-	BlockShift = XNandPs8_BbtBlockShift(Block);
+	BlockOffset = Block >> XNANDPSU_BBT_BLOCK_SHIFT;
+	BlockShift = XNandPsu_BbtBlockShift(Block);
 	Data = InstancePtr->Bbt[BlockOffset];	/* Block information in BBT */
-	BlockType = (Data >> BlockShift) & XNANDPS8_BLOCK_TYPE_MASK;
+	BlockType = (Data >> BlockShift) & XNANDPSU_BLOCK_TYPE_MASK;
 
-	if ((BlockType != XNANDPS8_BLOCK_GOOD) &&
-		(BlockType != XNANDPS8_BLOCK_RESERVED)) {
+	if ((BlockType != XNANDPSU_BLOCK_GOOD) &&
+		(BlockType != XNANDPSU_BLOCK_RESERVED)) {
 		Status = XST_SUCCESS;
 	}
 	else {
@@ -1009,7 +1009,7 @@ s32 XNandPs8_IsBlockBad(XNandPs8 *InstancePtr, u32 Block)
 * This function marks a block as bad in the RAM based Bad Block Table(BBT). It
 * also updates the Bad Block Table(BBT) in the flash.
 *
-* @param	InstancePtr is the pointer to the XNandPs8 instance.
+* @param	InstancePtr is the pointer to the XNandPsu instance.
 * @param	Block is the block number.
 *
 * @return
@@ -1017,7 +1017,7 @@ s32 XNandPs8_IsBlockBad(XNandPs8 *InstancePtr, u32 Block)
 *		- XST_FAILURE if fail.
 *
 ******************************************************************************/
-s32 XNandPs8_MarkBlockBad(XNandPs8 *InstancePtr, u32 Block)
+s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block)
 {
 	u8 Data;
 	u8 BlockShift;
@@ -1033,16 +1033,16 @@ s32 XNandPs8_MarkBlockBad(XNandPs8 *InstancePtr, u32 Block)
 
 	Target = Block % InstancePtr->Geometry.NumTargetBlocks;
 
-	BlockOffset = Block >> XNANDPS8_BBT_BLOCK_SHIFT;
-	BlockShift = XNandPs8_BbtBlockShift(Block);
+	BlockOffset = Block >> XNANDPSU_BBT_BLOCK_SHIFT;
+	BlockShift = XNandPsu_BbtBlockShift(Block);
 	Data = InstancePtr->Bbt[BlockOffset];	/* Block information in BBT */
 
 	/*
 	 * Mark the block as bad in the RAM based Bad Block Table
 	 */
 	OldVal = Data;
-	Data &= ~(XNANDPS8_BLOCK_TYPE_MASK << BlockShift);
-	Data |= (XNANDPS8_BLOCK_BAD << BlockShift);
+	Data &= ~(XNANDPSU_BLOCK_TYPE_MASK << BlockShift);
+	Data |= (XNANDPSU_BLOCK_BAD << BlockShift);
 	NewVal = Data;
 	InstancePtr->Bbt[BlockOffset] = Data;
 
@@ -1050,7 +1050,7 @@ s32 XNandPs8_MarkBlockBad(XNandPs8 *InstancePtr, u32 Block)
 	 * Update the Bad Block Table(BBT) in flash
 	 */
 	if (OldVal != NewVal) {
-		Status = XNandPs8_UpdateBbt(InstancePtr, Target);
+		Status = XNandPsu_UpdateBbt(InstancePtr, Target);
 		if (Status != XST_SUCCESS) {
 			goto Out;
 		}
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_bbm.h b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.h
similarity index 70%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_bbm.h
rename to XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.h
index 083351fc..4dfbc5c1 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_bbm.h
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_bbm.h
@@ -32,7 +32,7 @@
 /*****************************************************************************/
 /**
 *
-* @file xnandps8_bbm.h
+* @file xnandpsu_bbm.h
 *
 * This file implements the Bad Block Management(BBM) functionality. This is
 * similar to the Bad Block Management which is a part of the MTD subsystem in
@@ -73,8 +73,8 @@
 * 0'b11 -> Good Block
 *
 * The user can check for the validity of the block using the API
-* XNandPs8_IsBlockBad and take the action based on the return value. Also user
-* can update the bad block table using XNandPs8_MarkBlockBad API.
+* XNandPsu_IsBlockBad and take the action based on the return value. Also user
+* can update the bad block table using XNandPsu_MarkBlockBad API.
 *
 * @note		None
 *
@@ -85,94 +85,94 @@
 * ----- ----   ----------  -----------------------------------------------
 * 1.0   nm     05/06/2014  First release
 * 2.0   sb     01/12/2015  Added support for writing BBT signature and version
-*			   in page section by enabling XNANDPS8_BBT_NO_OOB.
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
 *			   Modified Bbt Signature and Version Offset value for
 *			   Oob and No-Oob region.
 * </pre>
 *
 ******************************************************************************/
-#ifndef XNANDPS8_BBM_H		/* prevent circular inclusions */
-#define XNANDPS8_BBM_H		/* by using protection macros */
+#ifndef XNANDPSU_BBM_H		/* prevent circular inclusions */
+#define XNANDPSU_BBM_H		/* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /***************************** Include Files *********************************/
-#include "xnandps8.h"
+#include "xnandpsu.h"
 
 /************************** Constant Definitions *****************************/
 /*
  * Block definitions for RAM based Bad Block Table (BBT)
  */
-#define XNANDPS8_BLOCK_GOOD			0x0U	/**< Block is good */
-#define XNANDPS8_BLOCK_BAD			0x1U	/**< Block is bad */
-#define XNANDPS8_BLOCK_RESERVED			0x2U	/**< Reserved block */
-#define XNANDPS8_BLOCK_FACTORY_BAD		0x3U	/**< Factory marked bad
+#define XNANDPSU_BLOCK_GOOD			0x0U	/**< Block is good */
+#define XNANDPSU_BLOCK_BAD			0x1U	/**< Block is bad */
+#define XNANDPSU_BLOCK_RESERVED			0x2U	/**< Reserved block */
+#define XNANDPSU_BLOCK_FACTORY_BAD		0x3U	/**< Factory marked bad
 							  block */
 /*
  * Block definitions for FLASH based Bad Block Table (BBT)
  */
-#define XNANDPS8_FLASH_BLOCK_GOOD		0x3U	/**< Block is good */
-#define XNANDPS8_FLASH_BLOCK_BAD		0x2U	/**< Block is bad */
-#define XNANDPS8_FLASH_BLOCK_RESERVED		0x1U	/**< Reserved block */
-#define XNANDPS8_FLASH_BLOCK_FAC_BAD	0x0U	/**< Factory marked bad
+#define XNANDPSU_FLASH_BLOCK_GOOD		0x3U	/**< Block is good */
+#define XNANDPSU_FLASH_BLOCK_BAD		0x2U	/**< Block is bad */
+#define XNANDPSU_FLASH_BLOCK_RESERVED		0x1U	/**< Reserved block */
+#define XNANDPSU_FLASH_BLOCK_FAC_BAD	0x0U	/**< Factory marked bad
 							  block */
 
-#define XNANDPS8_BBT_SCAN_2ND_PAGE		0x00000001U	/**< Scan the
+#define XNANDPSU_BBT_SCAN_2ND_PAGE		0x00000001U	/**< Scan the
 								  second page
 								  for bad block
 								  information
 								  */
-#define XNANDPS8_BBT_DESC_PAGE_OFFSET		0U	/**< Page offset of Bad
+#define XNANDPSU_BBT_DESC_PAGE_OFFSET		0U	/**< Page offset of Bad
 							  Block Table Desc */
-#define XNANDPS8_BBT_DESC_SIG_OFFSET		8U	/**< Bad Block Table
+#define XNANDPSU_BBT_DESC_SIG_OFFSET		8U	/**< Bad Block Table
 							  signature offset */
-#define XNANDPS8_BBT_DESC_VER_OFFSET		12U	/**< Bad block Table
+#define XNANDPSU_BBT_DESC_VER_OFFSET		12U	/**< Bad block Table
 							  version offset */
-#define XNANDPS8_NO_OOB_BBT_DESC_SIG_OFFSET	0U	/**< Bad Block Table
+#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET	0U	/**< Bad Block Table
 							  signature offset in
 							  page memory */
-#define XNANDPS8_NO_OOB_BBT_DESC_VER_OFFSET	4U	/**< Bad block Table
+#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET	4U	/**< Bad block Table
 							  version offset in
 							  page memory */
-#define XNANDPS8_BBT_DESC_SIG_LEN		4U	/**< Bad block Table
+#define XNANDPSU_BBT_DESC_SIG_LEN		4U	/**< Bad block Table
 							  signature length */
-#define XNANDPS8_BBT_DESC_MAX_BLOCKS		64U	/**< Bad block Table
+#define XNANDPSU_BBT_DESC_MAX_BLOCKS		64U	/**< Bad block Table
 							  max blocks */
 
-#define XNANDPS8_BBT_BLOCK_SHIFT		2U	/**< Block shift value
+#define XNANDPSU_BBT_BLOCK_SHIFT		2U	/**< Block shift value
 							  for a block in BBT */
-#define XNANDPS8_BBT_ENTRY_NUM_BLOCKS		4U	/**< Num of blocks in
+#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS		4U	/**< Num of blocks in
 							  one BBT entry */
-#define XNANDPS8_BB_PTRN_OFF_SML_PAGE	5U	/**< Bad block pattern
+#define XNANDPSU_BB_PTRN_OFF_SML_PAGE	5U	/**< Bad block pattern
 							  offset in a page */
-#define XNANDPS8_BB_PTRN_LEN_SML_PAGE	1U	/**< Bad block pattern
+#define XNANDPSU_BB_PTRN_LEN_SML_PAGE	1U	/**< Bad block pattern
 							  length */
-#define XNANDPS8_BB_PTRN_OFF_LARGE_PAGE	0U	/**< Bad block pattern
+#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE	0U	/**< Bad block pattern
 							  offset in a large
 							  page */
-#define XNANDPS8_BB_PTRN_LEN_LARGE_PAGE	2U	/**< Bad block pattern
+#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE	2U	/**< Bad block pattern
 							  length */
-#define XNANDPS8_BB_PATTERN			0xFFU	/**< Bad block pattern
+#define XNANDPSU_BB_PATTERN			0xFFU	/**< Bad block pattern
 							  to search in a page
 							  */
-#define XNANDPS8_BLOCK_TYPE_MASK		0x03U	/**< Block type mask */
-#define XNANDPS8_BLOCK_SHIFT_MASK		0x06U	/**< Block shift mask
+#define XNANDPSU_BLOCK_TYPE_MASK		0x03U	/**< Block type mask */
+#define XNANDPSU_BLOCK_SHIFT_MASK		0x06U	/**< Block shift mask
 							  for a Bad Block Table
 							  entry byte */
 
-#define XNANDPS8_ONDIE_SIG_OFFSET		0x4U
-#define XNANDPS8_ONDIE_VER_OFFSET		0x14U
+#define XNANDPSU_ONDIE_SIG_OFFSET		0x4U
+#define XNANDPSU_ONDIE_VER_OFFSET		0x14U
 
-#define XNANDPS8_BBT_VERSION_LENGTH	1U
-#define XNANDPS8_BBT_SIG_LENGTH		4U
+#define XNANDPSU_BBT_VERSION_LENGTH	1U
+#define XNANDPSU_BBT_SIG_LENGTH		4U
 
-#define XNANDPS8_BBT_BUF_LENGTH		((XNANDPS8_MAX_BLOCKS >> 		\
-					 XNANDPS8_BBT_BLOCK_SHIFT) +	\
-					(XNANDPS8_BBT_DESC_SIG_OFFSET +	\
-					 XNANDPS8_BBT_SIG_LENGTH +	\
-					 XNANDPS8_BBT_VERSION_LENGTH))
+#define XNANDPSU_BBT_BUF_LENGTH		((XNANDPSU_MAX_BLOCKS >> 		\
+					 XNANDPSU_BBT_BLOCK_SHIFT) +	\
+					(XNANDPSU_BBT_DESC_SIG_OFFSET +	\
+					 XNANDPSU_BBT_SIG_LENGTH +	\
+					 XNANDPSU_BBT_VERSION_LENGTH))
 /**************************** Type Definitions *******************************/
 
 /***************** Macros (Inline Functions) Definitions *********************/
@@ -189,20 +189,20 @@ extern "C" {
 * @note         None.
 *
 *****************************************************************************/
-#define XNandPs8_BbtBlockShift(Block) \
-			((u8)(((Block) * 2U) & XNANDPS8_BLOCK_SHIFT_MASK))
+#define XNandPsu_BbtBlockShift(Block) \
+			((u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK))
 
 /************************** Variable Definitions *****************************/
 
 /************************** Function Prototypes ******************************/
 
-void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr);
+void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr);
 
-s32 XNandPs8_ScanBbt(XNandPs8 *InstancePtr);
+s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
 
-s32 XNandPs8_IsBlockBad(XNandPs8 *InstancePtr, u32 Block);
+s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block);
 
-s32 XNandPs8_MarkBlockBad(XNandPs8 *InstancePtr, u32 Block);
+s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
 
 #ifdef __cplusplus
 }
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_g.c b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_g.c
similarity index 92%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_g.c
rename to XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_g.c
index 9d321906..e1ae93c1 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_g.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_g.c
@@ -32,10 +32,10 @@
 /*****************************************************************************/
 /**
 *
-* @file xnandps8_g.c
+* @file xnandpsu_g.c
 *
 * This file contains a configuration table where each entry is a configuration
-* structure for an XNandPs8 device in the system.
+* structure for an XNandPsu device in the system.
 *
 * <pre>
 * MODIFICATION HISTORY:
@@ -50,7 +50,7 @@
 
 /***************************** Include Files ********************************/
 #include "xparameters.h"
-#include "xnandps8.h"
+#include "xnandpsu.h"
 /************************** Constant Definitions ****************************/
 
 /**************************** Type Definitions ******************************/
@@ -60,11 +60,11 @@
 /************************** Variable Definitions ****************************/
 
 /**
- * Each XNandPs8 device in the system has an entry in this table.
+ * Each XNandPsu device in the system has an entry in this table.
  */
-XNandPs8_Config XNandPs8_ConfigTable[] = {
+XNandPsu_Config XNandPsu_ConfigTable[] = {
 	{
 		0U,
-		XPAR_XNANDPS8_0_BASEADDR
+		XPAR_XNANDPSU_0_BASEADDR
 	}
 };
diff --git a/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_hw.h b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_hw.h
new file mode 100644
index 00000000..5dcce71c
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_hw.h
@@ -0,0 +1,504 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_hw.h
+*
+* This file contains identifiers and low-level macros/functions for the Arasan
+* NAND flash controller driver.
+*
+* See xnandpsu.h for more information.
+*
+* @note		None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date        Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First Release
+* 2.0   sb     11/04/2014  Changed XNANDPSU_ECC_SLC_MLC_MASK to
+*			   XNANDPSU_ECC_HAMMING_BCH_MASK.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XNANDPSU_HW_H		/* prevent circular inclusions */
+#define XNANDPSU_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/************************** Register Offset Definitions **********************/
+
+#define XNANDPSU_PKT_OFFSET		0x00U	/**< Packet Register */
+#define XNANDPSU_MEM_ADDR1_OFFSET	0x04U	/**< Memory Address
+						  Register 1 */
+#define XNANDPSU_MEM_ADDR2_OFFSET	0x08U	/**< Memory Address
+						  Register 2 */
+#define XNANDPSU_CMD_OFFSET		0x0CU	/**< Command Register */
+#define XNANDPSU_PROG_OFFSET		0x10U	/**< Program Register */
+#define XNANDPSU_INTR_STS_EN_OFFSET	0x14U	/**< Interrupt Status
+						     Enable Register */
+#define XNANDPSU_INTR_SIG_EN_OFFSET	0x18U	/**< Interrupt Signal
+						     Enable Register */
+#define XNANDPSU_INTR_STS_OFFSET	0x1CU	/**< Interrupt Status
+						  Register */
+#define XNANDPSU_READY_BUSY_OFFSET	0x20U	/**< Ready/Busy status
+						  Register */
+#define XNANDPSU_FLASH_STS_OFFSET	0x28U	/**< Flash Status Register */
+#define XNANDPSU_TIMING_OFFSET		0x2CU	/**< Timing Register */
+#define XNANDPSU_BUF_DATA_PORT_OFFSET	0x30U	/**< Buffer Data Port
+						  Register */
+#define XNANDPSU_ECC_OFFSET		0x34U	/**< ECC Register */
+#define XNANDPSU_ECC_ERR_CNT_OFFSET	0x38U	/**< ECC Error Count
+						  Register */
+#define XNANDPSU_ECC_SPR_CMD_OFFSET	0x3CU	/**< ECC Spare Command
+						     Register */
+#define XNANDPSU_ECC_CNT_1BIT_OFFSET	0x40U	/**< Error Count 1bit
+						  Register */
+#define XNANDPSU_ECC_CNT_2BIT_OFFSET	0x44U	/**< Error Count 2bit
+						  Register */
+#define XNANDPSU_ECC_CNT_3BIT_OFFSET	0x48U	/**< Error Count 3bit
+						  Register */
+#define XNANDPSU_ECC_CNT_4BIT_OFFSET	0x4CU	/**< Error Count 4bit
+						  Register */
+#define XNANDPSU_CPU_REL_OFFSET		0x58U	/**< CPU Release Register */
+#define XNANDPSU_ECC_CNT_5BIT_OFFSET	0x5CU	/**< Error Count 5bit
+						  Register */
+#define XNANDPSU_ECC_CNT_6BIT_OFFSET	0x60U	/**< Error Count 6bit
+						  Register */
+#define XNANDPSU_ECC_CNT_7BIT_OFFSET	0x64U	/**< Error Count 7bit
+						  Register */
+#define XNANDPSU_ECC_CNT_8BIT_OFFSET	0x68U	/**< Error Count 8bit
+						  Register */
+#define XNANDPSU_DATA_INTF_OFFSET	0x6CU	/**< Data Interface Register */
+#define XNANDPSU_DMA_SYS_ADDR0_OFFSET	0x50U	/**< DMA System Address 0
+						  Register */
+#define XNANDPSU_DMA_SYS_ADDR1_OFFSET	0x24U	/**< DMA System Address 1
+						  Register */
+#define XNANDPSU_DMA_BUF_BND_OFFSET	0x54U	/**< DMA Buffer Boundary
+						  Register */
+#define XNANDPSU_SLV_DMA_CONF_OFFSET	0x80U	/**< Slave DMA Configuration
+						  Register */
+
+/** @name Packet Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_PKT_PKT_SIZE_MASK		0x000007FFU /**< Packet Size */
+#define XNANDPSU_PKT_PKT_CNT_MASK		0x00FFF000U /**< Packet Count*/
+#define XNANDPSU_PKT_PKT_CNT_SHIFT		12U /**< Packet Count Shift */
+/* @} */
+
+/** @name Memory Address Register 1 bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK	0x0000FFFFU /**< Column Address
+							     Mask */
+#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK		0xFFFF0000U /**< Page, Block
+							     Address Mask */
+#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT	16U /**< Page Shift */
+/* @} */
+
+/** @name Memory Address Register 2 bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK	0x000000FFU /**< Memory Address
+								*/
+#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK	0x01000000U /**< Bus Width */
+#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK	0x0E000000U /**< BCH Mode
+							     Value */
+#define XNANDPSU_MEM_ADDR2_MODE_MASK		0x30000000U /**< Flash
+							     Connection Mode */
+#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK	0xC0000000U /**< Chip Select */
+#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT	30U	/**< Chip select
+							shift */
+#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT	24U	/**< Bus width shift */
+#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT	25U
+/* @} */
+
+/** @name Command Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_CMD_CMD1_MASK			0x000000FFU /**< 1st Cycle
+							     Command */
+#define XNANDPSU_CMD_CMD2_MASK			0x0000FF00U /**< 2nd Cycle
+							     Command */
+#define XNANDPSU_CMD_PG_SIZE_MASK		0x03800000U /**< Page Size */
+#define XNANDPSU_CMD_DMA_EN_MASK		0x0C000000U /**< DMA Enable
+							     Mode */
+#define XNANDPSU_CMD_ADDR_CYCLES_MASK		0x70000000U /**< Number of
+							     Address Cycles */
+#define XNANDPSU_CMD_ECC_ON_MASK		0x80000000U /**< ECC ON/OFF */
+#define XNANDPSU_CMD_CMD2_SHIFT			8U /**< 2nd Cycle Command
+						    Shift */
+#define XNANDPSU_CMD_PG_SIZE_SHIFT		23U /**< Page Size Shift */
+#define XNANDPSU_CMD_DMA_EN_SHIFT		26U /**< DMA Enable Shift */
+#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT		28U /**< Number of Address
+						     Cycles Shift */
+#define XNANDPSU_CMD_ECC_ON_SHIFT		31U /**< ECC ON/OFF */
+/* @} */
+
+/** @name Program Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_PROG_RD_MASK			0x00000001U /**< Read */
+#define XNANDPSU_PROG_MUL_DIE_MASK		0x00000002U /**< Multi Die */
+#define XNANDPSU_PROG_BLK_ERASE_MASK		0x00000004U /**< Block Erase */
+#define XNANDPSU_PROG_RD_STS_MASK		0x00000008U /**< Read Status */
+#define XNANDPSU_PROG_PG_PROG_MASK		0x00000010U /**< Page Program */
+#define XNANDPSU_PROG_MUL_DIE_RD_MASK		0x00000020U /**< Multi Die Rd */
+#define XNANDPSU_PROG_RD_ID_MASK		0x00000040U /**< Read ID */
+#define XNANDPSU_PROG_RD_PRM_PG_MASK		0x00000080U /**< Read Param
+							     Page */
+#define XNANDPSU_PROG_RST_MASK			0x00000100U /**< Reset */
+#define XNANDPSU_PROG_GET_FEATURES_MASK		0x00000200U /**< Get Features */
+#define XNANDPSU_PROG_SET_FEATURES_MASK		0x00000400U /**< Set Features */
+#define XNANDPSU_PROG_RD_UNQ_ID_MASK		0x00000800U /**< Read Unique
+							     ID */
+#define XNANDPSU_PROG_RD_STS_ENH_MASK		0x00001000U /**< Read Status
+							     Enhanced */
+#define XNANDPSU_PROG_RD_INTRLVD_MASK		0x00002000U /**< Read
+							     Interleaved */
+#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK	0x00004000U /**< Change Read
+								Column
+								Enhanced */
+#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK	0x00008000U /**< Copy Back
+								Interleaved */
+#define XNANDPSU_PROG_RD_CACHE_START_MASK	0x00010000U /**< Read Cache
+							     Start */
+#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK		0x00020000U /**< Read Cache
+							     Sequential */
+#define XNANDPSU_PROG_RD_CACHE_RAND_MASK	0x00040000U /**< Read Cache
+								Random */
+#define XNANDPSU_PROG_RD_CACHE_END_MASK		0x00080000U /**< Read Cache
+							     End */
+#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK	0x00100000U /**< Small Data
+							     Move */
+#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK	0x00200000U /**< Change Row
+								Address */
+#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK	0x00400000U /**< Change Row
+								Address End */
+#define XNANDPSU_PROG_RST_LUN_MASK		0x00800000U /**< Reset LUN */
+#define XNANDPSU_PROG_PGM_PG_CLR_MASK		0x01000000U /**< Enhanced
+							     Program Page
+							     Register Clear */
+#define XNANDPSU_PROG_VOL_SEL_MASK		0x02000000U /**< Volume Select */
+#define XNANDPSU_PROG_ODT_CONF_MASK		0x04000000U /**< ODT Configure */
+/* @} */
+
+/** @name Interrupt Status Enable Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write Ready
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read Ready
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								     Bit Error
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single
+								     Bit Error
+								     Status
+								     Enable,
+								     BCH Detect
+								     Error
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error
+								     AHB Status
+								     Enable */
+/* @} */
+
+/** @name Interrupt Signal Enable Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write Ready
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read Ready
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								     Bit Error
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single
+								     Bit Error
+								     Signal
+								     Enable,
+								     BCH Detect
+								     Error
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error
+								     AHB Signal
+								     Enable */
+/* @} */
+
+/** @name Interrupt Status Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write
+								     Ready */
+#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read
+								     Ready */
+#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete */
+#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								    Bit Error */
+#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK		0x00000010U /**< Single
+								     Bit Error,
+								     BCH Detect
+								     Error */
+#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK		0x00000040U /**< DMA
+								     Interrupt
+								     */
+#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK		0x00000080U /**< Error
+								     AHB */
+/* @} */
+
+/** @name Interrupt bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer Write
+								Ready Status
+								Enable */
+#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer Read
+								Ready Status
+								Enable */
+#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								Complete Status
+								Enable */
+#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi Bit Error
+								Status Enable */
+#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single Bit Error
+								Status Enable,
+								BCH Detect Error
+								Status Enable */
+#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA Status
+								Enable */
+#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error AHB Status
+								Enable */
+/* @} */
+
+/** @name ID2 Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ID2_DEVICE_ID2_MASK		0x000000FFU /**< MSB Device ID */
+/* @} */
+
+/** @name Flash Status Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_FLASH_STS_FLASH_STS_MASK	0x0000FFFFU /**< Flash Status
+							     Value */
+/* @} */
+
+/** @name Timing Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_TIMING_TCCS_TIME_MASK		0x00000003U /**< Change column
+							     setup time */
+#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK	0x00000004U /**< Slow/Fast device
+							     */
+#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK	0x00000078U /**< Write/Read data
+							     transaction value
+							     */
+#define XNANDPSU_TIMING_TADL_TIME_MASK		0x00007F80U /**< Address latch
+							     enable to Data
+							     loading time */
+/* @} */
+
+/** @name ECC Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_ADDR_MASK			0x0000FFFFU /**< ECC address */
+#define XNANDPSU_ECC_SIZE_MASK			0x01FF0000U /**< ECC size */
+#define XNANDPSU_ECC_HAMMING_BCH_MASK		0x02000000U /**< Hamming/BCH
+							     support */
+/* @} */
+
+/** @name ECC Error Count Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK	0x000000FFU /**< Packet
+								     bound error
+								     count */
+#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK	0x0000FF00U /**< Page
+								     bound error
+								     count */
+/* @} */
+
+/** @name ECC Spare Command Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK		0x000000FFU /**< ECC
+								     spare
+								     command */
+#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK	0x70000000U /**< Number
+								     of ECC/
+								     spare
+								     address
+								     cycles */
+/* @} */
+
+/** @name Data Interface Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_DATA_INTF_SDR_MASK		0x00000007U /**< SDR mode */
+#define XNANDPSU_DATA_INTF_NVDDR_MASK		0x00000038U /**< NVDDR mode */
+#define XNANDPSU_DATA_INTF_NVDDR2_MASK		0x000001C0U /**< NVDDR2 mode */
+#define XNANDPSU_DATA_INTF_DATA_INTF_MASK	0x00000600U /**< Data
+							     Interface */
+#define XNANDPSU_DATA_INTF_NVDDR_SHIFT		3U /**< NVDDR mode shift */
+#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT	9U /**< Data Interface Shift */
+/* @} */
+
+/** @name DMA Buffer Boundary Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_DMA_BUF_BND_BND_MASK		0x00000007U /**< DMA buffer
+							     boundary */
+#define XNANDPSU_DMA_BUF_BND_4K			0x0U
+#define XNANDPSU_DMA_BUF_BND_8K			0x1U
+#define XNANDPSU_DMA_BUF_BND_16K		0x2U
+#define XNANDPSU_DMA_BUF_BND_32K		0x3U
+#define XNANDPSU_DMA_BUF_BND_64K		0x4U
+#define XNANDPSU_DMA_BUF_BND_128K		0x5U
+#define XNANDPSU_DMA_BUF_BND_256K		0x6U
+#define XNANDPSU_DMA_BUF_BND_512K		0x7U
+/* @} */
+
+/** @name Slave DMA Configuration Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK		0x00000001U /**< Slave
+								     DMA
+								     Transfer
+								     Direction
+								     */
+#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK	0x001FFFFEU /**< Slave
+								     DMA
+								     Transfer
+								     Count */
+#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK	0x00E00000U /**< Slave
+								     DMA
+								     Burst
+								     Size */
+#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK	0x0F000000U /**< DMA
+								     Timeout
+								     Counter
+								     Value */
+#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK		0x10000000U /**< Slave
+								     DMA
+								     Enable */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the base address of controller registers.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XNandPsu_ReadReg(BaseAddress, RegOffset)			\
+			Xil_In32((BaseAddress) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	BaseAddress is the the base address of controller registers.
+* @param	RegOffset is the register offset to be written.
+* @param	Data is the the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XNandPsu_WriteReg(BaseAddress, RegOffset, Data)			\
+			Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XNANDPSU_HW_H end of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_onfi.c b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.c
similarity index 96%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_onfi.c
rename to XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.c
index 581e8fbf..660547f4 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_onfi.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.c
@@ -32,7 +32,7 @@
 /*****************************************************************************/
 /**
 *
-* @file xnandps8_onfi.c
+* @file xnandpsu_onfi.c
 *
 * This file contains the implementation of ONFI specific functions.
 *
@@ -49,8 +49,8 @@
 ******************************************************************************/
 
 /***************************** Include Files *********************************/
-#include "xnandps8_onfi.h"
-#include "xnandps8.h"
+#include "xnandpsu_onfi.h"
+#include "xnandpsu.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -75,7 +75,7 @@
 *		None.
 *
 ******************************************************************************/
-u32 XNandPs8_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length)
+u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length)
 {
 	const u32 CrcInit = 0x4F4EU;
 	const u32 Order = 16U;
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_onfi.h b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.h
similarity index 98%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_onfi.h
rename to XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.h
index cda8a49a..94412188 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_onfi.h
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_onfi.h
@@ -32,7 +32,7 @@
 /*****************************************************************************/
 /**
 *
-* @file xnandps8_onfi.h
+* @file xnandpsu_onfi.h
 *
 * This file defines all the ONFI 3.1 specific commands and values.
 *
@@ -47,8 +47,8 @@
 * </pre>
 *
 ******************************************************************************/
-#ifndef XNANDPS8_ONFI_H		/* prevent circular inclusions */
-#define XNANDPS8_ONFI_H		/* by using protection macros */
+#ifndef XNANDPSU_ONFI_H		/* prevent circular inclusions */
+#define XNANDPSU_ONFI_H		/* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
@@ -331,10 +331,10 @@ extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
 
 /************************** Function Prototypes ******************************/
 
-u32 XNandPs8_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
+u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* XNANDPS8_ONFI_H end of protection macro */
+#endif /* XNANDPSU_ONFI_H end of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_sinit.c b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_sinit.c
similarity index 86%
rename from XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_sinit.c
rename to XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_sinit.c
index 53b6895c..67fa4b6e 100644
--- a/XilinxProcessorIPLib/drivers/nandps8_v2_0/src/xnandps8_sinit.c
+++ b/XilinxProcessorIPLib/drivers/nandpsu/src/xnandpsu_sinit.c
@@ -32,9 +32,9 @@
 /*****************************************************************************/
 /**
 *
-* @file xnandps8_sinit.c
+* @file xnandpsu_sinit.c
 *
-* The implementation of the XNandPs8 driver's static initialzation
+* The implementation of the XNandPsu driver's static initialzation
 * functionality.
 *
 * <pre>
@@ -50,9 +50,9 @@
 /***************************** Include Files ********************************/
 #include "xstatus.h"
 #include "xparameters.h"
-#include "xnandps8.h"
+#include "xnandpsu.h"
 /************************** Constant Definitions ****************************/
-#define XPAR_XNANDPS8_NUM_INSTANCES	1U
+#define XPAR_XNANDPSU_NUM_INSTANCES	1U
 
 /**************************** Type Definitions ******************************/
 
@@ -60,7 +60,7 @@
 
 /************************** Variable Definitions ****************************/
 
-extern XNandPs8_Config XNandPs8_ConfigTable[];
+extern XNandPsu_Config XNandPsu_ConfigTable[];
 
 /************************** Function Prototypes *****************************/
 
@@ -78,17 +78,17 @@ extern XNandPs8_Config XNandPs8_ConfigTable[];
 *		controller ID was not found.
 *
 ******************************************************************************/
-XNandPs8_Config *XNandPs8_LookupConfig(u16 DeviceID)
+XNandPsu_Config *XNandPsu_LookupConfig(u16 DeviceID)
 {
-	XNandPs8_Config *CfgPtr = NULL;
+	XNandPsu_Config *CfgPtr = NULL;
 	u32 Index;
 
-	for (Index = 0U; Index < XPAR_XNANDPS8_NUM_INSTANCES; Index++) {
-		if (XNandPs8_ConfigTable[Index].DeviceId == DeviceID) {
-			CfgPtr = &XNandPs8_ConfigTable[Index];
+	for (Index = 0U; Index < XPAR_XNANDPSU_NUM_INSTANCES; Index++) {
+		if (XNandPsu_ConfigTable[Index].DeviceId == DeviceID) {
+			CfgPtr = &XNandPsu_ConfigTable[Index];
 			break;
 		}
 	}
 
-	return (XNandPs8_Config *)CfgPtr;
+	return (XNandPsu_Config *)CfgPtr;
 }