diff --git a/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h b/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
index a8abd485..091cda54 100755
--- a/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
+++ b/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
@@ -51,6 +51,9 @@
 * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
 *					  to 0x1fff. This fixes the CR#744902.
 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
 * </pre>
 *
 ******************************************************************************/
@@ -377,8 +380,8 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
 /** @name DMA control register bit definitions
  * @{
  */
-#define XEMACPS_DMACR_TXEXTEND_MASK		0x02000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK		0x01000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
 #define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
 													size */
 #define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer