From ec8a0b20f768402d0b24954fb2f57a8e3aebfa33 Mon Sep 17 00:00:00 2001 From: Bhavik Ameta Date: Tue, 5 May 2015 19:45:30 +0530 Subject: [PATCH] sw_services:xilsecure_v1_0: resolved AES and RSA failures DMA interrupt clearing after each transfer in AES resolved RSA failure due to incorrect data type Signed-off-by: Bhavik Ameta --- lib/sw_services/xilsecure/src/xsecure_aes.c | 18 ++++++++++++++++++ lib/sw_services/xilsecure/src/xsecure_rsa.c | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/lib/sw_services/xilsecure/src/xsecure_aes.c b/lib/sw_services/xilsecure/src/xsecure_aes.c index 46e79506..175e2ab6 100755 --- a/lib/sw_services/xilsecure/src/xsecure_aes.c +++ b/lib/sw_services/xilsecure/src/xsecure_aes.c @@ -363,6 +363,10 @@ static u32 XSecure_AesDecryptBlk(XSecure_Aes *InstancePtr, u8 *Dst, XCsuDma_WaitForDone(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL); + /* Acknowledge the transfer has completed */ + XCsuDma_IntrClear(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL, + XCSUDMA_IXR_DONE_MASK); + /* Enable CSU DMA Src channel for byte swapping.*/ XCsuDma_Configure ConfigurValues = {0}; @@ -396,6 +400,12 @@ static u32 XSecure_AesDecryptBlk(XSecure_Aes *InstancePtr, u8 *Dst, /* Wait for the Dst DMA completion. */ XCsuDma_WaitForDone(InstancePtr->CsuDmaPtr, XCSUDMA_DST_CHANNEL); + /* Acknowledge the transfers has completed */ + XCsuDma_IntrClear(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL, + XCSUDMA_IXR_DONE_MASK); + XCsuDma_IntrClear(InstancePtr->CsuDmaPtr, XCSUDMA_DST_CHANNEL, + XCSUDMA_IXR_DONE_MASK); + /* Disble CSU DMA Dst channel for byte swapping. */ XCsuDma_GetConfig(InstancePtr->CsuDmaPtr, XCSUDMA_DST_CHANNEL, @@ -435,6 +445,10 @@ static u32 XSecure_AesDecryptBlk(XSecure_Aes *InstancePtr, u8 *Dst, /* Wait for the Src DMA completion. */ XCsuDma_WaitForDone(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL); + /* Acknowledge the transfer has completed */ + XCsuDma_IntrClear(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL, + XCSUDMA_IXR_DONE_MASK); + /* Restore Key write register to 0. */ XSecure_WriteReg(InstancePtr->BaseAddress, XSECURE_CSU_AES_KUP_WR_OFFSET, 0x0); @@ -446,6 +460,10 @@ static u32 XSecure_AesDecryptBlk(XSecure_Aes *InstancePtr, u8 *Dst, /* Wait for the Src DMA completion. */ XCsuDma_WaitForDone(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL); + /* Acknowledge the transfer has completed */ + XCsuDma_IntrClear(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL, + XCSUDMA_IXR_DONE_MASK); + /* Disable CSU DMA Src channel for byte swapping. */ XCsuDma_GetConfig(InstancePtr->CsuDmaPtr, XCSUDMA_SRC_CHANNEL, diff --git a/lib/sw_services/xilsecure/src/xsecure_rsa.c b/lib/sw_services/xilsecure/src/xsecure_rsa.c index 5f455f5e..4311af8d 100755 --- a/lib/sw_services/xilsecure/src/xsecure_rsa.c +++ b/lib/sw_services/xilsecure/src/xsecure_rsa.c @@ -215,7 +215,7 @@ static void XSecure_RsaGetData(XSecure_Rsa *InstancePtr, u32 *RdData) u32 Index = 0U; u32 DataOffset = 0U; - u32 TmpIndex = 0; + s32 TmpIndex = 0; /* Each of this loop will write 192 bits of data */ for (DataOffset = 0U; DataOffset < 22U; DataOffset++)