From ee628ac79636b797f044ce4ccb91152a26e21c03 Mon Sep 17 00:00:00 2001 From: Rohit Consul Date: Thu, 20 Aug 2015 14:04:03 -0700 Subject: [PATCH] v_deinterlacer: IP Bus Name prefix change IP bus name prefix changed from "AXILITES" to "CTRL" to align with all other HLS IP's in video processing subsystem. Generated driver updated. Signed-off-by: Rohit Consul Acked-by: Srikanth Vemula --- .../v_deinterlacer/data/v_deinterlacer.tcl | 10 ++-- .../v_deinterlacer/src/xv_deinterlacer.c | 60 +++++++++---------- .../v_deinterlacer/src/xv_deinterlacer_hw.h | 36 +++++------ .../v_deinterlacer/src/xv_deinterlacer_l2.c | 2 +- 4 files changed, 54 insertions(+), 54 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.tcl b/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.tcl index c2b5e4d5..a725a773 100755 --- a/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.tcl +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.tcl @@ -33,21 +33,21 @@ proc generate {drv_handle} { xdefine_include_file $drv_handle "xparameters.h" "XV_deinterlacer" \ "NUM_INSTANCES" \ "DEVICE_ID" \ - "C_S_AXI_AXILITES_BASEADDR" \ - "C_S_AXI_AXILITES_HIGHADDR" \ + "C_S_AXI_CTRL_BASEADDR" \ + "C_S_AXI_CTRL_HIGHADDR" \ "NUM_VIDEO_COMPONENTS" \ "MAX_DATA_WIDTH" xdefine_config_file $drv_handle "xv_deinterlacer_g.c" "XV_deinterlacer" \ "DEVICE_ID" \ - "C_S_AXI_AXILITES_BASEADDR" \ + "C_S_AXI_CTRL_BASEADDR" \ "NUM_VIDEO_COMPONENTS" \ "MAX_DATA_WIDTH" xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_deinterlacer" \ "DEVICE_ID" \ - "C_S_AXI_AXILITES_BASEADDR" \ - "C_S_AXI_AXILITES_HIGHADDR" \ + "C_S_AXI_CTRL_BASEADDR" \ + "C_S_AXI_CTRL_HIGHADDR" \ "NUM_VIDEO_COMPONENTS" \ "MAX_DATA_WIDTH" } diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c index cbdd1d2f..d898e4e2 100644 --- a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c @@ -38,8 +38,8 @@ void XV_deinterlacer_Start(XV_deinterlacer *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL) & 0x80; - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL, Data | 0x01); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_AP_CTRL) & 0x80; + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_AP_CTRL, Data | 0x01); } u32 XV_deinterlacer_IsDone(XV_deinterlacer *InstancePtr) { @@ -48,7 +48,7 @@ u32 XV_deinterlacer_IsDone(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_AP_CTRL); return (Data >> 1) & 0x1; } @@ -58,7 +58,7 @@ u32 XV_deinterlacer_IsIdle(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_AP_CTRL); return (Data >> 2) & 0x1; } @@ -68,7 +68,7 @@ u32 XV_deinterlacer_IsReady(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_AP_CTRL); // check ap_start to see if the pcore is ready for next input return !(Data & 0x1); } @@ -77,21 +77,21 @@ void XV_deinterlacer_EnableAutoRestart(XV_deinterlacer *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL, 0x80); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_AP_CTRL, 0x80); } void XV_deinterlacer_DisableAutoRestart(XV_deinterlacer *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL, 0); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_AP_CTRL, 0); } void XV_deinterlacer_Set_width(XV_deinterlacer *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA, Data); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_WIDTH_DATA, Data); } u32 XV_deinterlacer_Get_width(XV_deinterlacer *InstancePtr) { @@ -100,7 +100,7 @@ u32 XV_deinterlacer_Get_width(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_WIDTH_DATA); return Data; } @@ -108,7 +108,7 @@ void XV_deinterlacer_Set_height(XV_deinterlacer *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA, Data); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_HEIGHT_DATA, Data); } u32 XV_deinterlacer_Get_height(XV_deinterlacer *InstancePtr) { @@ -117,14 +117,14 @@ u32 XV_deinterlacer_Get_height(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_HEIGHT_DATA); return Data; } void XV_deinterlacer_Set_read_fb(XV_deinterlacer *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA, Data); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_READ_FB_DATA, Data); } u32 XV_deinterlacer_Get_read_fb(XV_deinterlacer *InstancePtr) { @@ -133,7 +133,7 @@ u32 XV_deinterlacer_Get_read_fb(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_READ_FB_DATA); return Data; } @@ -141,7 +141,7 @@ void XV_deinterlacer_Set_write_fb(XV_deinterlacer *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA, Data); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_WRITE_FB_DATA, Data); } u32 XV_deinterlacer_Get_write_fb(XV_deinterlacer *InstancePtr) { @@ -150,7 +150,7 @@ u32 XV_deinterlacer_Get_write_fb(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_WRITE_FB_DATA); return Data; } @@ -158,7 +158,7 @@ void XV_deinterlacer_Set_colorFormat(XV_deinterlacer *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA, Data); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_COLORFORMAT_DATA, Data); } u32 XV_deinterlacer_Get_colorFormat(XV_deinterlacer *InstancePtr) { @@ -167,7 +167,7 @@ u32 XV_deinterlacer_Get_colorFormat(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_COLORFORMAT_DATA); return Data; } @@ -175,7 +175,7 @@ void XV_deinterlacer_Set_algo(XV_deinterlacer *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA, Data); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_ALGO_DATA, Data); } u32 XV_deinterlacer_Get_algo(XV_deinterlacer *InstancePtr) { @@ -184,7 +184,7 @@ u32 XV_deinterlacer_Get_algo(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_ALGO_DATA); return Data; } @@ -192,7 +192,7 @@ void XV_deinterlacer_Set_invert_field_id(XV_deinterlacer *InstancePtr, u32 Data) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA, Data); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_INVERT_FIELD_ID_DATA, Data); } u32 XV_deinterlacer_Get_invert_field_id(XV_deinterlacer *InstancePtr) { @@ -201,21 +201,21 @@ u32 XV_deinterlacer_Get_invert_field_id(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA); + Data = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_INVERT_FIELD_ID_DATA); return Data; } void XV_deinterlacer_InterruptGlobalEnable(XV_deinterlacer *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_GIE, 1); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_GIE, 1); } void XV_deinterlacer_InterruptGlobalDisable(XV_deinterlacer *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_GIE, 0); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_GIE, 0); } void XV_deinterlacer_InterruptEnable(XV_deinterlacer *InstancePtr, u32 Mask) { @@ -224,8 +224,8 @@ void XV_deinterlacer_InterruptEnable(XV_deinterlacer *InstancePtr, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Register = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER, Register | Mask); + Register = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_IER); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_IER, Register | Mask); } void XV_deinterlacer_InterruptDisable(XV_deinterlacer *InstancePtr, u32 Mask) { @@ -234,27 +234,27 @@ void XV_deinterlacer_InterruptDisable(XV_deinterlacer *InstancePtr, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Register = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER, Register & (~Mask)); + Register = XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_IER); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_IER, Register & (~Mask)); } void XV_deinterlacer_InterruptClear(XV_deinterlacer *InstancePtr, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_ISR, Mask); + XV_deinterlacer_WriteReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_ISR, Mask); } u32 XV_deinterlacer_InterruptGetEnabled(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - return XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER); + return XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_IER); } u32 XV_deinterlacer_InterruptGetStatus(XV_deinterlacer *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - return XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_ISR); + return XV_deinterlacer_ReadReg(InstancePtr->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_ISR); } diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h index d0dc6146..615cea46 100644 --- a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h @@ -50,21 +50,21 @@ // 0x44 : reserved // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) -#define XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL 0x00 -#define XV_DEINTERLACER_AXILITES_ADDR_GIE 0x04 -#define XV_DEINTERLACER_AXILITES_ADDR_IER 0x08 -#define XV_DEINTERLACER_AXILITES_ADDR_ISR 0x0c -#define XV_DEINTERLACER_AXILITES_ADDR_WIDTH_DATA 0x10 -#define XV_DEINTERLACER_AXILITES_BITS_WIDTH_DATA 32 -#define XV_DEINTERLACER_AXILITES_ADDR_HEIGHT_DATA 0x18 -#define XV_DEINTERLACER_AXILITES_BITS_HEIGHT_DATA 32 -#define XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA 0x20 -#define XV_DEINTERLACER_AXILITES_BITS_READ_FB_DATA 32 -#define XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA 0x28 -#define XV_DEINTERLACER_AXILITES_BITS_WRITE_FB_DATA 32 -#define XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA 0x30 -#define XV_DEINTERLACER_AXILITES_BITS_COLORFORMAT_DATA 8 -#define XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA 0x38 -#define XV_DEINTERLACER_AXILITES_BITS_ALGO_DATA 8 -#define XV_DEINTERLACER_AXILITES_ADDR_INVERT_FIELD_ID_DATA 0x40 -#define XV_DEINTERLACER_AXILITES_BITS_INVERT_FIELD_ID_DATA 1 +#define XV_DEINTERLACER_CTRL_ADDR_AP_CTRL 0x00 +#define XV_DEINTERLACER_CTRL_ADDR_GIE 0x04 +#define XV_DEINTERLACER_CTRL_ADDR_IER 0x08 +#define XV_DEINTERLACER_CTRL_ADDR_ISR 0x0c +#define XV_DEINTERLACER_CTRL_ADDR_WIDTH_DATA 0x10 +#define XV_DEINTERLACER_CTRL_BITS_WIDTH_DATA 32 +#define XV_DEINTERLACER_CTRL_ADDR_HEIGHT_DATA 0x18 +#define XV_DEINTERLACER_CTRL_BITS_HEIGHT_DATA 32 +#define XV_DEINTERLACER_CTRL_ADDR_READ_FB_DATA 0x20 +#define XV_DEINTERLACER_CTRL_BITS_READ_FB_DATA 32 +#define XV_DEINTERLACER_CTRL_ADDR_WRITE_FB_DATA 0x28 +#define XV_DEINTERLACER_CTRL_BITS_WRITE_FB_DATA 32 +#define XV_DEINTERLACER_CTRL_ADDR_COLORFORMAT_DATA 0x30 +#define XV_DEINTERLACER_CTRL_BITS_COLORFORMAT_DATA 8 +#define XV_DEINTERLACER_CTRL_ADDR_ALGO_DATA 0x38 +#define XV_DEINTERLACER_CTRL_BITS_ALGO_DATA 8 +#define XV_DEINTERLACER_CTRL_ADDR_INVERT_FIELD_ID_DATA 0x40 +#define XV_DEINTERLACER_CTRL_BITS_INVERT_FIELD_ID_DATA 1 diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.c b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.c index 196ded9d..49b9a36b 100644 --- a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.c +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.c @@ -146,7 +146,7 @@ void XV_DeintDbgReportStatus(XV_deinterlacer *InstancePtr) done = XV_deinterlacer_IsDone(pDeint); idle = XV_deinterlacer_IsIdle(pDeint); ready = XV_deinterlacer_IsReady(pDeint); - ctrl = XV_deinterlacer_ReadReg(pDeint->Config.BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL); + ctrl = XV_deinterlacer_ReadReg(pDeint->Config.BaseAddress, XV_DEINTERLACER_CTRL_ADDR_AP_CTRL); rfb = XV_deinterlacer_Get_read_fb(pDeint); wfb = XV_deinterlacer_Get_write_fb(pDeint);