diff --git a/lib/sw_apps/openamp_echo_test/src/echo_test.c b/lib/sw_apps/openamp_echo_test/src/echo_test.c
index 6130eacd..62b23831 100644
--- a/lib/sw_apps/openamp_echo_test/src/echo_test.c
+++ b/lib/sw_apps/openamp_echo_test/src/echo_test.c
@@ -113,14 +113,6 @@ int main() {
     /* Initialize HW system components */
     init_system();
 
-	/*
-	 * The data caches are disabled due to some unusual behavior
-	 * Upon running the application second time without rebooting,
-	 * communication channel is not being established. It is a known
-	 * issue and need to be fixed in future.
-	 */
-	Xil_DCacheDisable();
-
     rsc_info.rsc_tab = (struct resource_table *)&resources;
     rsc_info.size = sizeof(resources);
 
diff --git a/lib/sw_apps/openamp_echo_test/src/platform.c b/lib/sw_apps/openamp_echo_test/src/platform.c
index 19e7850a..8dc06d1a 100644
--- a/lib/sw_apps/openamp_echo_test/src/platform.c
+++ b/lib/sw_apps/openamp_echo_test/src/platform.c
@@ -43,6 +43,8 @@
 
 #include "platform.h"
 #include "xil_io.h"
+#include "xscugic.h"
+#include "xil_cache.h"
 /*--------------------------- Globals ---------------------------------- */
 struct hil_platform_ops proc_ops = {
 	.enable_interrupt	= _enable_interrupt,
@@ -52,6 +54,7 @@ struct hil_platform_ops proc_ops = {
 	.shutdown_cpu		= _shutdown_cpu,
 };
 
+unsigned int old_value = 0;
 
 int _enable_interrupt(struct proc_vring *vring_hw) {
 
@@ -117,3 +120,57 @@ void deinit_isr(int vect_id, void *data) {
 		Xil_Out32((chn_ipi_info->ipi_base_addr + IPI_ISR_OFFSET), chn_ipi_info->ipi_chn_mask);
 	}
 }
+
+
+void platform_interrupt_enable(u32 vector,u32 polarity, u32 priority) {
+	XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR,vector);
+}
+
+void platform_interrupt_disable(unsigned int vector) {
+	XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR,vector);
+}
+
+void platform_cache_all_flush_invalidate() {
+		Xil_DCacheFlush();
+		Xil_DCacheInvalidate();
+		Xil_ICacheInvalidate();
+}
+
+void platform_cache_disable() {
+		Xil_DCacheDisable();
+		Xil_ICacheDisable();
+}
+
+void platform_map_mem_region(unsigned int va,unsigned int pa, unsigned int size,int is_mem_mapped,int cache_type) {
+	return;
+}
+
+unsigned long platform_vatopa(unsigned long addr) {
+	 return ((unsigned long)addr);
+ }
+
+void *platform_patova(unsigned long addr) {
+	return ((void *)addr);
+}
+
+void restore_global_interrupts() {
+
+	ARM_AR_INT_BITS_SET(old_value);
+
+}
+
+void disable_global_interrupts() {
+
+	unsigned int value = 0;
+
+	ARM_AR_INT_BITS_GET(&value);
+
+	if (value != old_value) {
+
+		ARM_AR_INT_BITS_SET(CORTEXR5_CPSR_INTERRUPTS_BITS);
+
+		old_value = value;
+
+	}
+
+}
diff --git a/lib/sw_apps/openamp_echo_test/src/platform.h b/lib/sw_apps/openamp_echo_test/src/platform.h
index d7204fd9..2960daab 100644
--- a/lib/sw_apps/openamp_echo_test/src/platform.h
+++ b/lib/sw_apps/openamp_echo_test/src/platform.h
@@ -35,6 +35,7 @@
 #include <stdio.h>
 #include "hil.h"
 #include "xil_cache.h"
+#include "xreg_cortexr5.h"
 /* ------------------------- Macros --------------------------*/
 
 /********************/
@@ -55,30 +56,9 @@ void _shutdown_cpu(int cpu_id);
 void platform_isr(int vect_id, void *data);
 void deinit_isr(int vect_id, void *data);
 
-/* define function macros for OpenAMP API */
-#define platform_cache_all_flush_invalidate() \
-	{ \
-		Xil_DCacheFlush(); \
-		Xil_DCacheInvalidate(); \
-		Xil_ICacheInvalidate(); \
-	}
-
-#define platform_cache_disable() \
-	{ \
-		Xil_DCacheDisable(); \
-		Xil_ICacheDisable(); \
-	}
-
 #define platform_dcache_all_flush() { Xil_DCacheFlush(); }
 
 #define platform_dcache_flush_range(addr, len) { Xil_DCacheFlushRange(addr, len); }
-
-#define platform_interrupt_enable(...) zynqMP_r5_gic_interrupt_enable(__VA_ARGS__)
-#define platform_interrupt_disable(...) zynqMP_r5_gic_interrupt_disable(__VA_ARGS__)
-#define platform_map_mem_region(...)
-
-#define platform_vatopa(addr) ((unsigned long)addr)
-#define platform_patova(addr) ((void *)addr)
 /* IPI REGs OFFSET */
 #define IPI_TRIG_OFFSET          0x00000000 /* IPI trigger register offset */
 #define IPI_OBS_OFFSET           0x00000004 /* IPI observation register offset */
@@ -97,4 +77,35 @@ void deinit_isr(int vect_id, void *data);
 #define MASTER_CPU_ID                     0
 #define REMOTE_CPU_ID                     1
 
+#define CORTEXR5_CPSR_INTERRUPTS_BITS (XREG_CPSR_IRQ_ENABLE | XREG_CPSR_FIQ_ENABLE)
+
+/* This macro writes the current program status register (CPSR - all fields) */
+#define ARM_AR_CPSR_CXSF_WRITE(cpsr_cxsf_value) \
+	{ \
+		asm volatile("    MSR     CPSR_cxsf, %0" \
+			: /* No outputs */ \
+			: "r" (cpsr_cxsf_value) ); \
+	}
+
+/* This macro sets the interrupt related bits in the status register / control
+ register to the specified value. */
+#define ARM_AR_INT_BITS_SET(set_bits) \
+	{ \
+		int     tmp_val; \
+		tmp_val = mfcpsr(); \
+		tmp_val &= ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS); \
+		tmp_val |= set_bits; \
+		ARM_AR_CPSR_CXSF_WRITE(tmp_val); \
+	}
+
+/* This macro gets the interrupt related bits from the status register / control
+ register. */
+#define ARM_AR_INT_BITS_GET(get_bits_ptr) \
+	{ \
+		int     tmp_val; \
+		tmp_val = mfcpsr(); \
+		tmp_val &= CORTEXR5_CPSR_INTERRUPTS_BITS; \
+		*get_bits_ptr = tmp_val; \
+	}
+
 #endif /* PLATFORM_H_ */