diff --git a/lib/sw_services/xilpm/data/xilpm.mld b/lib/sw_services/xilpm/data/xilpm.mld new file mode 100644 index 00000000..48721587 --- /dev/null +++ b/lib/sw_services/xilpm/data/xilpm.mld @@ -0,0 +1,42 @@ +#/****************************************************************************** +#* +#* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +#* +#* Permission is hereby granted, free of charge, to any person obtaining a copy +#* of this software and associated documentation files (the "Software"), to deal +#* in the Software without restriction, including without limitation the rights +#* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +#* copies of the Software, and to permit persons to whom the Software is +#* furnished to do so, subject to the following conditions: +#* +#* The above copyright notice and this permission notice shall be included in +#* all copies or substantial portions of the Software. +#* +#* Use of the Software is limited solely to applications: +#* (a) running on a Xilinx device, or +#* (b) that interact with a Xilinx device through a bus or interconnect. +#* +#* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +#* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +#* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +#* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +#* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +#* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +#* SOFTWARE. +#* +#* Except as contained in this notice, the name of the Xilinx shall not be used +#* in advertising or otherwise to promote the sale, use or other dealings in +#* this Software without prior written authorization from Xilinx. +#* +#******************************************************************************/ + +OPTION psf_version = 2.1; + +BEGIN LIBRARY xilpm + OPTION copyfiles = all; + OPTION REQUIRES_OS = (standalone); + OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lxilpm,-lxil,-lgcc,-lc,--end-group"; + OPTION desc = "Power Management API Library for ZynqMP"; + OPTION VERSION = 1.0; + OPTION NAME = xilpm; +END LIBRARY diff --git a/lib/sw_services/xilpm/data/xilpm.tcl b/lib/sw_services/xilpm/data/xilpm.tcl new file mode 100644 index 00000000..a106e3a0 --- /dev/null +++ b/lib/sw_services/xilpm/data/xilpm.tcl @@ -0,0 +1,105 @@ +#/****************************************************************************** +#* +#* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +#* +#* Permission is hereby granted, free of charge, to any person obtaining a copy +#* of this software and associated documentation files (the "Software"), to deal +#* in the Software without restriction, including without limitation the rights +#* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +#* copies of the Software, and to permit persons to whom the Software is +#* furnished to do so, subject to the following conditions: +#* +#* The above copyright notice and this permission notice shall be included in +#* all copies or substantial portions of the Software. +#* +#* Use of the Software is limited solely to applications: +#* (a) running on a Xilinx device, or +#* (b) that interact with a Xilinx device through a bus or interconnect. +#* +#* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +#* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +#* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +#* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +#* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +#* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +#* SOFTWARE. +#* +#* Except as contained in this notice, the name of the Xilinx shall not be used +#* in advertising or otherwise to promote the sale, use or other dealings in +#* this Software without prior written authorization from Xilinx. +#* +#******************************************************************************/ + +proc generate {libhandle} { + # Copy over the right set of files as src based on processor type + set sw_proc_handle [hsi::get_sw_processor] + set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ] + set proctype [common::get_property IP_NAME $hw_proc_handle] + set procname [common::get_property NAME $hw_proc_handle] + + set cortexa53srcdir "./src/apu" + set cortexr5srcdir "./src/rpu" + + set commonsrcdir "./src/common" + + foreach entry [glob -nocomplain [file join $commonsrcdir *]] { + file copy -force $entry "./src" + } + + switch $proctype { + "psu_cortexa53" { + foreach entry [glob -nocomplain [file join $cortexa53srcdir *]] { + file copy -force $entry "./src/" + } + } + + "psu_cortexr5" { + foreach entry [glob -nocomplain [file join $cortexr5srcdir *]] { + file copy -force $entry "./src/" + } + } + + "default" {error "Error: Processor type $proctype is not supported\n"} + + } + + file delete -force $cortexr5srcdir + file delete -force $cortexa53srcdir + file delete -force $commonsrcdir + +} + + +#------- +# post_generate: called after generate called on all libraries +#------- +proc post_generate {libhandle} { + xgen_opts_file $libhandle +} + +#------- +# execs_generate: called after BSP's, libraries and drivers have been compiled +#------- +proc execs_generate {libhandle} { + +} + +proc xgen_opts_file {libhandle} { + + # Copy the include files to the include directory + set srcdir src + set dstdir [file join .. .. include] + + # Create dstdir if it does not exist + if { ! [file exists $dstdir] } { + file mkdir $dstdir + } + + # Get list of files in the srcdir + set sources [glob -join $srcdir *.h] + + # Copy each of the files in the list to dstdir + foreach source $sources { + file copy -force $source $dstdir + } +} diff --git a/lib/sw_services/xilpm/examples/gic_setup.c b/lib/sw_services/xilpm/examples/gic_setup.c new file mode 100644 index 00000000..f21ff035 --- /dev/null +++ b/lib/sw_services/xilpm/examples/gic_setup.c @@ -0,0 +1,128 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * CONTENT + * Generic functions for gic initialization and interrupt enabling + *********************************************************************/ + +#include "gic_setup.h" + +XScuGic GicInst; +/** + * GicSetupHandler() - Connect interrupt Handler to the specified interrupt number + * @IntId Interrupt id + * @PeriphInstPtr Pointer to the peripheral driver + * @Handler Interrupt Handler that for the specified peripheral + * + * @return Status of operation success (XST_* from xstatus.h) + */ +int32_t GicSetupHandler(uint32_t IntId, void *PeriphInstPtr, Xil_ExceptionHandler Handler) +{ + int32_t status; + /* + * Connect a device driver Handler that will be called when an + * interrupt for the device occurs, the device driver Handler + * performs the specific interrupt processing for the device + */ + status = XScuGic_Connect(&GicInst, IntId, + Handler, + PeriphInstPtr); + return status; +} +/** + * GicEnableInterrupt() - Enable interrupt in gic + */ +void GicEnableInterrupt(uint32_t IntId) +{ + XScuGic_Enable(&GicInst, IntId); +} + +/** + * GicInit() - Initialize gic + * + * @return Status of operation success (XST_* from xstatus.h) + */ +int32_t GicInit() +{ + int32_t Status; + XScuGic_Config *GicCfgPtr; + /* Initialize the interrupt controller driver */ + GicCfgPtr = XScuGic_LookupConfig(INTC_DEVICE_ID); + if (NULL == GicCfgPtr) + return XST_FAILURE; + + Status = XScuGic_CfgInitialize(&GicInst, GicCfgPtr, GicCfgPtr->CpuBaseAddress); + if (XST_SUCCESS != Status) + return Status; + + /* + * Connect the interrupt controller interrupt Handler to the + * hardware interrupt handling logic in the processor. + */ + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XScuGic_InterruptHandler, + &GicInst); + + return XST_SUCCESS; +} + +/** + * GicSetupInterruptSystem() - configure the system to receive peripheral interrupt + * @IntId interrupt id of the timer + * @PeriphInstPtr peripheral + * @Handler interrupt Handler + * + * Does everything that is needed for enabling interrupts (gic setup, Handler connecting, + * interrupt enabling on processor and gic level) + * + * @return: status of operation success (XST_* from xstatus.h) + */ +int32_t GicSetupInterruptSystem(uint32_t IntId, + void *PeriphInstPtr, Xil_ExceptionHandler Handler) +{ + int32_t Status; + + Status = GicInit(); + if(XST_SUCCESS != Status) + return Status; + + Status = GicSetupHandler(IntId, PeriphInstPtr, Handler); + if(XST_SUCCESS != Status) + return Status; + + GicEnableInterrupt(IntId); + + Xil_ExceptionEnable(); + + return XST_SUCCESS; +} diff --git a/lib/sw_services/xilpm/examples/gic_setup.h b/lib/sw_services/xilpm/examples/gic_setup.h new file mode 100644 index 00000000..46794133 --- /dev/null +++ b/lib/sw_services/xilpm/examples/gic_setup.h @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _GIC_SETUP_H_ +#define _GIC_SETUP_H_ + +#include + +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID + +extern XScuGic GicInst; + +int32_t GicSetupHandler(uint32_t IntId, void *PeriphInstPtr, Xil_ExceptionHandler Handler); + +void GicEnableInterrupt(uint32_t IntId); + +int32_t GicSetupInterruptSystem(uint32_t IntId, + void *PeriphInstPtr, Xil_ExceptionHandler Handler); + +int32_t GicInit(); +#endif diff --git a/lib/sw_services/xilpm/examples/timer.c b/lib/sw_services/xilpm/examples/timer.c new file mode 100644 index 00000000..79cca405 --- /dev/null +++ b/lib/sw_services/xilpm/examples/timer.c @@ -0,0 +1,133 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * CONTENT + * Timer peripheral driver. Code is mostly reused from + * hello_ttc0_interrupt application. + *********************************************************************/ + +#include +#include + +#include +#include "timer.h" +#include "gic_setup.h" +#include "pm_client.h" + +volatile uint32_t TickCount = 0; +static XTtcPs timer0_inst; + +/** + * TickHandler() - interrupt handler for timer 0 + * @timer_inst: pointer to the timer instance + */ +static void TickHandler(XTtcPs *timer_inst) +{ + uint32_t int_status = XTtcPs_GetInterruptStatus(timer_inst); + int_status &= XTtcPs_ReadReg(timer_inst->Config.BaseAddress, XTTCPS_IER_OFFSET); + XTtcPs_ClearInterruptStatus(timer_inst, int_status); + TickCount++; + pm_dbg("Timer0 interrupt handler, tick_count = %d\n", TickCount); +} + +/** + * TimerSetIntervalMode() - This fuction sets TTC into interval mode + * @timer_inst pointer to the timer instance + * @sec interval timeout in seconds + */ +static void TimerSetIntervalMode(XTtcPs *TimerInstPtr, uint32_t PeriodInSec) +{ + /* Stop the timer */ + XTtcPs_Stop(TimerInstPtr); + /* Set Interval mode */ + XTtcPs_SetOptions(TimerInstPtr, XTTCPS_OPTION_INTERVAL_MODE); + XTtcPs_SetInterval(TimerInstPtr, (PeriodInSec * COUNT_PER_SEC)); + XTtcPs_ResetCounterValue(TimerInstPtr); + XTtcPs_SetPrescaler(TimerInstPtr, 15); + /* Enable interrupt */ + XTtcPs_EnableInterrupts(TimerInstPtr, XTTCPS_IXR_INTERVAL_MASK); +} + +/** + * TimerInit() - initializes timer0 device + * @timeout period for the interval timer interrupt generation + */ +int32_t TimerInit(uint32_t PeriodInSec) +{ + int32_t status; + XTtcPs_Config *timer_config; + /* Look up the configuration based on the device identifier */ + timer_config = XTtcPs_LookupConfig(TTC0_0_DEVICE_ID); + if (NULL == timer_config) { + return XST_FAILURE; + } + /* Initialize the device */ + status = XTtcPs_CfgInitialize(&timer0_inst, timer_config, timer_config->BaseAddress); + if (XST_SUCCESS != status) { + return status; + } + /* Setup interrupts */ + status = GicSetupInterruptSystem(TTC_INT_ID0, + &timer0_inst, (Xil_ExceptionHandler) TickHandler); + if (XST_SUCCESS == status) { + TimerSetIntervalMode(&timer0_inst, PeriodInSec); + XTtcPs_Start(&timer0_inst); + } + return status; +} + +/** + * TimerConfigure() - configure timer to generate periodic interrupts + * timer_period Time between two timer ticks + * + * @return Status of configuration success + */ +int32_t TimerConfigure(uint32_t Period) +{ + int32_t ret_status = TimerInit(Period); + switch (ret_status) { + case XST_SUCCESS: + pm_dbg("OK, configured timer\n"); + break; + case XST_DEVICE_IS_STARTED: + pm_dbg("WARNING, timer is already counting\n"); + break; + case XST_FAILURE: + pm_dbg("ERROR, failed to configure timer\n"); + break; + default: + pm_dbg("??? unhandled status %d\n", ret_status); + break; + } + return ret_status; +} diff --git a/lib/sw_services/xilpm/examples/timer.h b/lib/sw_services/xilpm/examples/timer.h new file mode 100644 index 00000000..86a2c39b --- /dev/null +++ b/lib/sw_services/xilpm/examples/timer.h @@ -0,0 +1,55 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * CONTENT + * Timer interface, contains function to initialize timer and + * global variable tick_count which stores total number of interrupts + * generated by the timer. + *********************************************************************/ + +#ifndef _TIMER_H_ +#define _TIMER_H_ + +#define TTC0_0_DEVICE_ID XPAR_XTTCPS_0_DEVICE_ID +#define COUNT_PER_SEC (XPAR_XTTCPS_0_CLOCK_HZ / 65535) +#define TTC_INT_ID0 XPAR_XTTCPS_0_INTR + +#define TIMER_PERIOD 3 + +int32_t TimerInit(uint32_t timeout); + +int32_t TimerConfigure(uint32_t timer_period); + +extern volatile uint32_t TickCount; + +#endif /* _TIMER_H_ */ diff --git a/lib/sw_services/xilpm/examples/xilpm_selfsuspend_example.c b/lib/sw_services/xilpm/examples/xilpm_selfsuspend_example.c new file mode 100644 index 00000000..5b71c496 --- /dev/null +++ b/lib/sw_services/xilpm/examples/xilpm_selfsuspend_example.c @@ -0,0 +1,193 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + +/********************************************************************* + * + * CONTENT + * Assumptions: only PROCESSOR core is executing this code, + * other cores in PROCESSOR subsystem are already powered down. + * 1) PROCESSOR configures timer0 peripheral to generate interrupts. + * 2) PROCESSOR waits for few interrupts to be generated by the timer and + * then initiates self suspend. Before calling pm_self_suspend APU + * has saved its context (which is in this case only tick_count + * variable value) in CONTEXT memory. Suspending of the PROCESSOR is followed + * by CONTEXT retention. + * 3) Timer is still counting while PROCESSOR is suspended and the next timer + * interrupt causes CONTEXT to be woken up by PMU. + * 4) Processor resumes its execution, meaning that it restores value of + * tick_count from CONTEXT MEM and does not configure timer again because it + * is already configured. PROCESSOR enables interrupts at the processor + * level (CPSR) and handle timer interrupt that caused wake-up. + * 5) PROCESSOR waits for few more timer interrupts and repeats the suspend + * procedure. + *********************************************************************/ + +#include +#include +#include +#include +#include +#include +#include "pm_api_sys.h" +#include "timer.h" +#include "pm_client.h" + +#ifdef __aarch64__ + /* Use OCM for saving context */ + #define CONTEXT_MEM_BASE 0xFFFC0000U +#else + /* Use TCM for saving context */ + #define CONTEXT_MEM_BASE 0x20000U +#endif + +/* The below sections will be saved during suspend */ +extern uint8_t __data_start; +extern uint8_t __bss_start__; +extern uint8_t __data_end; +extern uint8_t __bss_end__; + +/** + * SaveContext() - called to save context of bss and data sections in OCM + */ +static void SaveContext(void) +{ + uint8_t *MemPtr; + uint8_t *ContextMemPtr = (uint8_t *)CONTEXT_MEM_BASE; + for (MemPtr = &__data_start; MemPtr < &__data_end; MemPtr++, ContextMemPtr++) { + *ContextMemPtr = *MemPtr; + } + for (MemPtr = &__bss_start__; MemPtr < &__bss_end__; MemPtr++, ContextMemPtr++) { + *ContextMemPtr = *MemPtr; + } + pm_dbg("Saved context (tick_count = %d)\n", TickCount); +} + +/** + * RestoreContext() - called to restore context of bss and data sections from OCM + */ +static void RestoreContext(void) +{ + uint8_t *MemPtr; + uint8_t *ContextMemPtr = (uint8_t *)CONTEXT_MEM_BASE; + for (MemPtr = &__data_start; MemPtr < &__data_end; MemPtr++, ContextMemPtr++) { + *MemPtr = *ContextMemPtr; + } + for (MemPtr = &__bss_start__; MemPtr < &__bss_end__; MemPtr++, ContextMemPtr++) { + *MemPtr = *ContextMemPtr; + } + pm_dbg("Restored context (tick_count = %d)\n", TickCount); +} + +/** + * PrepareSuspend() - save context and request suspend + */ +static void PrepareSuspend(void) +{ + SaveContext(); +/* usleep is used to prevents UART prints from overlapping */ +#ifdef __aarch64__ + /* APU */ + XPm_SelfSuspend(NODE_APU_0, MAX_LATENCY, 0); + usleep(100000); + XPm_SetRequirement(NODE_OCM_BANK_0, PM_CAP_CONTEXT, 0, REQ_ACK_NO); + usleep(100000); + XPm_SetRequirement(NODE_OCM_BANK_1, PM_CAP_CONTEXT, 0, REQ_ACK_NO); + usleep(100000); + XPm_SetRequirement(NODE_OCM_BANK_2, PM_CAP_CONTEXT, 0, REQ_ACK_NO); + usleep(100000); + XPm_SetRequirement(NODE_OCM_BANK_3, PM_CAP_CONTEXT, 0, REQ_ACK_NO); + usleep(100000); +#else + /* RPU */ + XPm_SelfSuspend(NODE_RPU_0, MAX_LATENCY, 0); + usleep(100000); + XPm_SetRequirement(NODE_TCM_0_A, PM_CAP_CONTEXT, 0, REQ_ACK_NO); + usleep(100000); + XPm_SetRequirement(NODE_TCM_0_B, PM_CAP_CONTEXT, 0, REQ_ACK_NO); + usleep(100000); + XPm_SetRequirement(NODE_TCM_1_A, PM_CAP_CONTEXT, 0, REQ_ACK_NO); + usleep(100000); + XPm_SetRequirement(NODE_TCM_1_B, PM_CAP_CONTEXT, 0, REQ_ACK_NO); + usleep(100000); +#endif /* __aarch64__ */ +} + +/** + * InitApp() - initialize interrupts and context + */ +static uint32_t InitApp(void) +{ + enum XPmBootStatus status; + pm_dbg("Main\n"); + /* Get boot status for APU core #0 */ + status = XPm_GetBootStatus(); + if (PM_INITIAL_BOOT == status) { + pm_dbg("INITIAL BOOT\n"); + /* Configure timer, if configuration fails return from main */ + if (XST_FAILURE == TimerConfigure(TIMER_PERIOD)) { + pm_dbg("Exiting main...\n"); + return XST_FAILURE; + } + } else if (PM_RESUME == status) { + pm_dbg("RESUMED\n"); + RestoreContext(); + /* Timer is already counting, just enable interrupts */ + Xil_ExceptionEnable(); + } else { + pm_dbg("ERROR cannot identify boot reason\n"); + } + return XST_SUCCESS; +} + +int main(void) +{ + Xil_DCacheDisable(); + uint32_t Status = InitApp(); + if (XST_SUCCESS != Status) { + return XST_FAILURE; + } + + pm_dbg("Waiting for ticks...\n"); + /* Wait for 3 timer ticks */ + while ((TickCount + 1) % 4); + + PrepareSuspend(); + pm_dbg("Going to WFI...\n"); + __asm__("wfi"); + /* + * Can execute code below only if interrupt is generated between calling + * the PrepareSuspend and executing wfi. Shouldn't happen. + */ + pm_dbg("Error! WFI exit...\n"); + return XST_FAILURE; +} diff --git a/lib/sw_services/xilpm/src/apu/pm_apu.h b/lib/sw_services/xilpm/src/apu/pm_apu.h new file mode 100644 index 00000000..cf99e94b --- /dev/null +++ b/lib/sw_services/xilpm/src/apu/pm_apu.h @@ -0,0 +1,614 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _PM_APU_H_ +#define _PM_APU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * APU Base Address + */ +#define APU_BASEADDR 0XFD5C0000 + +/** + * Register: APU_ERR_CTRL + */ +#define APU_ERR_CTRL ( ( APU_BASEADDR ) + 0X00000000 ) + +#define APU_ERR_CTRL_PSLVERR_SHIFT 0 +#define APU_ERR_CTRL_PSLVERR_WIDTH 1 +#define APU_ERR_CTRL_PSLVERR_MASK 0X00000001 + +/** + * Register: APU_ISR + */ +#define APU_ISR ( ( APU_BASEADDR ) + 0X00000010 ) + +#define APU_ISR_INV_APB_SHIFT 0 +#define APU_ISR_INV_APB_WIDTH 1 +#define APU_ISR_INV_APB_MASK 0X00000001 + +/** + * Register: APU_IMR + */ +#define APU_IMR ( ( APU_BASEADDR ) + 0X00000014 ) + +#define APU_IMR_INV_APB_SHIFT 0 +#define APU_IMR_INV_APB_WIDTH 1 +#define APU_IMR_INV_APB_MASK 0X00000001 + +/** + * Register: APU_IEN + */ +#define APU_IEN ( ( APU_BASEADDR ) + 0X00000018 ) + +#define APU_IEN_INV_APB_SHIFT 0 +#define APU_IEN_INV_APB_WIDTH 1 +#define APU_IEN_INV_APB_MASK 0X00000001 + +/** + * Register: APU_IDS + */ +#define APU_IDS ( ( APU_BASEADDR ) + 0X0000001C ) + +#define APU_IDS_INV_APB_SHIFT 0 +#define APU_IDS_INV_APB_WIDTH 1 +#define APU_IDS_INV_APB_MASK 0X00000001 + +/** + * Register: APU_CONFIG_0 + */ +#define APU_CONFIG_0 ( ( APU_BASEADDR ) + 0X00000020 ) + +#define APU_CONFIG_0_CFGTE_SHIFT 24 +#define APU_CONFIG_0_CFGTE_WIDTH 4 +#define APU_CONFIG_0_CFGTE_MASK 0X0F000000 + +#define APU_CONFIG_0_CFGEND_SHIFT 16 +#define APU_CONFIG_0_CFGEND_WIDTH 4 +#define APU_CONFIG_0_CFGEND_MASK 0X000F0000 + +#define APU_CONFIG_0_VINITHI_SHIFT 8 +#define APU_CONFIG_0_VINITHI_WIDTH 4 +#define APU_CONFIG_0_VINITHI_MASK 0X00000F00 + +#define APU_CONFIG_0_AA64NAA32_SHIFT 0 +#define APU_CONFIG_0_AA64NAA32_WIDTH 4 +#define APU_CONFIG_0_AA64NAA32_MASK 0X0000000F + +/** + * Register: APU_CONFIG_1 + */ +#define APU_CONFIG_1 ( ( APU_BASEADDR ) + 0X00000024 ) + +#define APU_CONFIG_1_L2RSTDISABLE_SHIFT 29 +#define APU_CONFIG_1_L2RSTDISABLE_WIDTH 1 +#define APU_CONFIG_1_L2RSTDISABLE_MASK 0X20000000 + +#define APU_CONFIG_1_L1RSTDISABLE_SHIFT 28 +#define APU_CONFIG_1_L1RSTDISABLE_WIDTH 1 +#define APU_CONFIG_1_L1RSTDISABLE_MASK 0X10000000 + +#define APU_CONFIG_1_CP15DISABLE_SHIFT 0 +#define APU_CONFIG_1_CP15DISABLE_WIDTH 4 +#define APU_CONFIG_1_CP15DISABLE_MASK 0X0000000F + +/** + * Register: APU_RVBARADDR0L + */ +#define APU_RVBARADDR0L ( ( APU_BASEADDR ) + 0X00000040 ) + +#define APU_RVBARADDR0L_ADDR_SHIFT 2 +#define APU_RVBARADDR0L_ADDR_WIDTH 30 +#define APU_RVBARADDR0L_ADDR_MASK 0XFFFFFFFC + +/** + * Register: APU_RVBARADDR0H + */ +#define APU_RVBARADDR0H ( ( APU_BASEADDR ) + 0X00000044 ) + +#define APU_RVBARADDR0H_ADDR_SHIFT 0 +#define APU_RVBARADDR0H_ADDR_WIDTH 8 +#define APU_RVBARADDR0H_ADDR_MASK 0X000000FF + +/** + * Register: APU_RVBARADDR1L + */ +#define APU_RVBARADDR1L ( ( APU_BASEADDR ) + 0X00000048 ) + +#define APU_RVBARADDR1L_ADDR_SHIFT 2 +#define APU_RVBARADDR1L_ADDR_WIDTH 30 +#define APU_RVBARADDR1L_ADDR_MASK 0XFFFFFFFC + +/** + * Register: APU_RVBARADDR1H + */ +#define APU_RVBARADDR1H ( ( APU_BASEADDR ) + 0X0000004C ) + +#define APU_RVBARADDR1H_ADDR_SHIFT 0 +#define APU_RVBARADDR1H_ADDR_WIDTH 8 +#define APU_RVBARADDR1H_ADDR_MASK 0X000000FF + +/** + * Register: APU_RVBARADDR2L + */ +#define APU_RVBARADDR2L ( ( APU_BASEADDR ) + 0X00000050 ) + +#define APU_RVBARADDR2L_ADDR_SHIFT 2 +#define APU_RVBARADDR2L_ADDR_WIDTH 30 +#define APU_RVBARADDR2L_ADDR_MASK 0XFFFFFFFC + +/** + * Register: APU_RVBARADDR2H + */ +#define APU_RVBARADDR2H ( ( APU_BASEADDR ) + 0X00000054 ) + +#define APU_RVBARADDR2H_ADDR_SHIFT 0 +#define APU_RVBARADDR2H_ADDR_WIDTH 8 +#define APU_RVBARADDR2H_ADDR_MASK 0X000000FF + +/** + * Register: APU_RVBARADDR3L + */ +#define APU_RVBARADDR3L ( ( APU_BASEADDR ) + 0X00000058 ) + +#define APU_RVBARADDR3L_ADDR_SHIFT 2 +#define APU_RVBARADDR3L_ADDR_WIDTH 30 +#define APU_RVBARADDR3L_ADDR_MASK 0XFFFFFFFC + +/** + * Register: APU_RVBARADDR3H + */ +#define APU_RVBARADDR3H ( ( APU_BASEADDR ) + 0X0000005C ) + +#define APU_RVBARADDR3H_ADDR_SHIFT 0 +#define APU_RVBARADDR3H_ADDR_WIDTH 8 +#define APU_RVBARADDR3H_ADDR_MASK 0X000000FF + +/** + * Register: APU_ACE_CTRL + */ +#define APU_ACE_CTRL ( ( APU_BASEADDR ) + 0X00000060 ) + +#define APU_ACE_CTRL_AWQOS_SHIFT 16 +#define APU_ACE_CTRL_AWQOS_WIDTH 4 +#define APU_ACE_CTRL_AWQOS_MASK 0X000F0000 + +#define APU_ACE_CTRL_ARQOS_SHIFT 0 +#define APU_ACE_CTRL_ARQOS_WIDTH 4 +#define APU_ACE_CTRL_ARQOS_MASK 0X0000000F + +/** + * Register: APU_SNOOP_CTRL + */ +#define APU_SNOOP_CTRL ( ( APU_BASEADDR ) + 0X00000080 ) + +#define APU_SNOOP_CTRL_ACE_INACT_SHIFT 4 +#define APU_SNOOP_CTRL_ACE_INACT_WIDTH 1 +#define APU_SNOOP_CTRL_ACE_INACT_MASK 0X00000010 + +#define APU_SNOOP_CTRL_ACP_INACT_SHIFT 0 +#define APU_SNOOP_CTRL_ACP_INACT_WIDTH 1 +#define APU_SNOOP_CTRL_ACP_INACT_MASK 0X00000001 + +/** + * Register: APU_PWRCTL + */ +#define APU_PWRCTL ( ( APU_BASEADDR ) + 0X00000090 ) + +#define APU_PWRCTL_CLREXMONREQ_SHIFT 17 +#define APU_PWRCTL_CLREXMONREQ_WIDTH 1 +#define APU_PWRCTL_CLREXMONREQ_MASK 0X00020000 + +#define APU_PWRCTL_L2FLUSHREQ_SHIFT 16 +#define APU_PWRCTL_L2FLUSHREQ_WIDTH 1 +#define APU_PWRCTL_L2FLUSHREQ_MASK 0X00010000 + +#define APU_PWRCTL_CPUPWRDWNREQ_SHIFT 0 +#define APU_PWRCTL_CPUPWRDWNREQ_WIDTH 4 +#define APU_PWRCTL_CPUPWRDWNREQ_MASK 0X0000000F + +/** + * Register: APU_PWRSTAT + */ +#define APU_PWRSTAT ( ( APU_BASEADDR ) + 0X00000094 ) + +#define APU_PWRSTAT_CLREXMONACK_SHIFT 17 +#define APU_PWRSTAT_CLREXMONACK_WIDTH 1 +#define APU_PWRSTAT_CLREXMONACK_MASK 0X00020000 + +#define APU_PWRSTAT_L2FLUSHDONE_SHIFT 16 +#define APU_PWRSTAT_L2FLUSHDONE_WIDTH 1 +#define APU_PWRSTAT_L2FLUSHDONE_MASK 0X00010000 + +#define APU_PWRSTAT_DBGNOPWRDWN_SHIFT 0 +#define APU_PWRSTAT_DBGNOPWRDWN_WIDTH 4 +#define APU_PWRSTAT_DBGNOPWRDWN_MASK 0X0000000F + +/** + * Register: APU_ECO + */ +#define APU_ECO ( ( APU_BASEADDR ) + 0X000000EC ) + +#define APU_ECO_SPARE_SHIFT 0 +#define APU_ECO_SPARE_WIDTH 32 +#define APU_ECO_SPARE_MASK 0XFFFFFFFF + +/** + * Register: APU_RAM_ADJ_0 + */ +#define APU_RAM_ADJ_0 ( ( APU_BASEADDR ) + 0X000000F0 ) + +#define APU_RAM_ADJ_0_L1_ITAG_EMAS_SHIFT 29 +#define APU_RAM_ADJ_0_L1_ITAG_EMAS_WIDTH 1 +#define APU_RAM_ADJ_0_L1_ITAG_EMAS_MASK 0X20000000 + +#define APU_RAM_ADJ_0_L1_ITAG_EMAW_SHIFT 27 +#define APU_RAM_ADJ_0_L1_ITAG_EMAW_WIDTH 2 +#define APU_RAM_ADJ_0_L1_ITAG_EMAW_MASK 0X18000000 + +#define APU_RAM_ADJ_0_L1_ITAG_EMA_SHIFT 24 +#define APU_RAM_ADJ_0_L1_ITAG_EMA_WIDTH 3 +#define APU_RAM_ADJ_0_L1_ITAG_EMA_MASK 0X07000000 + +#define APU_RAM_ADJ_0_L1_IDATA_EMAS_SHIFT 21 +#define APU_RAM_ADJ_0_L1_IDATA_EMAS_WIDTH 1 +#define APU_RAM_ADJ_0_L1_IDATA_EMAS_MASK 0X00200000 + +#define APU_RAM_ADJ_0_L1_IDATA_EMAW_SHIFT 19 +#define APU_RAM_ADJ_0_L1_IDATA_EMAW_WIDTH 2 +#define APU_RAM_ADJ_0_L1_IDATA_EMAW_MASK 0X00180000 + +#define APU_RAM_ADJ_0_L1_IDATA_EMA_SHIFT 16 +#define APU_RAM_ADJ_0_L1_IDATA_EMA_WIDTH 3 +#define APU_RAM_ADJ_0_L1_IDATA_EMA_MASK 0X00070000 + +#define APU_RAM_ADJ_0_L1_DTAG_EMAS_SHIFT 13 +#define APU_RAM_ADJ_0_L1_DTAG_EMAS_WIDTH 1 +#define APU_RAM_ADJ_0_L1_DTAG_EMAS_MASK 0X00002000 + +#define APU_RAM_ADJ_0_L1_DTAG_EMAW_SHIFT 11 +#define APU_RAM_ADJ_0_L1_DTAG_EMAW_WIDTH 2 +#define APU_RAM_ADJ_0_L1_DTAG_EMAW_MASK 0X00001800 + +#define APU_RAM_ADJ_0_L1_DTAG_EMA_SHIFT 8 +#define APU_RAM_ADJ_0_L1_DTAG_EMA_WIDTH 3 +#define APU_RAM_ADJ_0_L1_DTAG_EMA_MASK 0X00000700 + +#define APU_RAM_ADJ_0_L1_DDATA_EMAS_SHIFT 5 +#define APU_RAM_ADJ_0_L1_DDATA_EMAS_WIDTH 1 +#define APU_RAM_ADJ_0_L1_DDATA_EMAS_MASK 0X00000020 + +#define APU_RAM_ADJ_0_L1_DDATA_EMAW_SHIFT 3 +#define APU_RAM_ADJ_0_L1_DDATA_EMAW_WIDTH 2 +#define APU_RAM_ADJ_0_L1_DDATA_EMAW_MASK 0X00000018 + +#define APU_RAM_ADJ_0_L1_DDATA_EMA_SHIFT 0 +#define APU_RAM_ADJ_0_L1_DDATA_EMA_WIDTH 3 +#define APU_RAM_ADJ_0_L1_DDATA_EMA_MASK 0X00000007 + +/** + * Register: APU_RAM_ADJ_1 + */ +#define APU_RAM_ADJ_1 ( ( APU_BASEADDR ) + 0X000000F4 ) + +#define APU_RAM_ADJ_1_TLB_EMAS_SHIFT 29 +#define APU_RAM_ADJ_1_TLB_EMAS_WIDTH 1 +#define APU_RAM_ADJ_1_TLB_EMAS_MASK 0X20000000 + +#define APU_RAM_ADJ_1_TLB_EMAW_SHIFT 27 +#define APU_RAM_ADJ_1_TLB_EMAW_WIDTH 2 +#define APU_RAM_ADJ_1_TLB_EMAW_MASK 0X18000000 + +#define APU_RAM_ADJ_1_TLB_EMA_SHIFT 24 +#define APU_RAM_ADJ_1_TLB_EMA_WIDTH 3 +#define APU_RAM_ADJ_1_TLB_EMA_MASK 0X07000000 + +#define APU_RAM_ADJ_1_DIRTY_EMAS_SHIFT 21 +#define APU_RAM_ADJ_1_DIRTY_EMAS_WIDTH 1 +#define APU_RAM_ADJ_1_DIRTY_EMAS_MASK 0X00200000 + +#define APU_RAM_ADJ_1_DIRTY_EMAW_SHIFT 19 +#define APU_RAM_ADJ_1_DIRTY_EMAW_WIDTH 2 +#define APU_RAM_ADJ_1_DIRTY_EMAW_MASK 0X00180000 + +#define APU_RAM_ADJ_1_DIRTY_EMA_SHIFT 16 +#define APU_RAM_ADJ_1_DIRTY_EMA_WIDTH 3 +#define APU_RAM_ADJ_1_DIRTY_EMA_MASK 0X00070000 + +#define APU_RAM_ADJ_1_BTAC1_EMAS_SHIFT 13 +#define APU_RAM_ADJ_1_BTAC1_EMAS_WIDTH 1 +#define APU_RAM_ADJ_1_BTAC1_EMAS_MASK 0X00002000 + +#define APU_RAM_ADJ_1_BTAC1_EMAW_SHIFT 11 +#define APU_RAM_ADJ_1_BTAC1_EMAW_WIDTH 2 +#define APU_RAM_ADJ_1_BTAC1_EMAW_MASK 0X00001800 + +#define APU_RAM_ADJ_1_BTAC1_EMA_SHIFT 8 +#define APU_RAM_ADJ_1_BTAC1_EMA_WIDTH 3 +#define APU_RAM_ADJ_1_BTAC1_EMA_MASK 0X00000700 + +#define APU_RAM_ADJ_1_BTAC0_EMAS_SHIFT 5 +#define APU_RAM_ADJ_1_BTAC0_EMAS_WIDTH 1 +#define APU_RAM_ADJ_1_BTAC0_EMAS_MASK 0X00000020 + +#define APU_RAM_ADJ_1_BTAC0_EMAW_SHIFT 3 +#define APU_RAM_ADJ_1_BTAC0_EMAW_WIDTH 2 +#define APU_RAM_ADJ_1_BTAC0_EMAW_MASK 0X00000018 + +#define APU_RAM_ADJ_1_BTAC0_EMA_SHIFT 0 +#define APU_RAM_ADJ_1_BTAC0_EMA_WIDTH 3 +#define APU_RAM_ADJ_1_BTAC0_EMA_MASK 0X00000007 + +/** + * Register: APU_RAM_ADJ_2 + */ +#define APU_RAM_ADJ_2 ( ( APU_BASEADDR ) + 0X000000F8 ) + +#define APU_RAM_ADJ_2_ETF_EMAS_SHIFT 29 +#define APU_RAM_ADJ_2_ETF_EMAS_WIDTH 1 +#define APU_RAM_ADJ_2_ETF_EMAS_MASK 0X20000000 + +#define APU_RAM_ADJ_2_ETF_EMAW_SHIFT 27 +#define APU_RAM_ADJ_2_ETF_EMAW_WIDTH 2 +#define APU_RAM_ADJ_2_ETF_EMAW_MASK 0X18000000 + +#define APU_RAM_ADJ_2_ETF_EMA_SHIFT 24 +#define APU_RAM_ADJ_2_ETF_EMA_WIDTH 3 +#define APU_RAM_ADJ_2_ETF_EMA_MASK 0X07000000 + +#define APU_RAM_ADJ_2_SCU_TAG_EMAS_SHIFT 13 +#define APU_RAM_ADJ_2_SCU_TAG_EMAS_WIDTH 1 +#define APU_RAM_ADJ_2_SCU_TAG_EMAS_MASK 0X00002000 + +#define APU_RAM_ADJ_2_SCU_TAG_EMAW_SHIFT 11 +#define APU_RAM_ADJ_2_SCU_TAG_EMAW_WIDTH 2 +#define APU_RAM_ADJ_2_SCU_TAG_EMAW_MASK 0X00001800 + +#define APU_RAM_ADJ_2_SCU_TAG_EMA_SHIFT 8 +#define APU_RAM_ADJ_2_SCU_TAG_EMA_WIDTH 3 +#define APU_RAM_ADJ_2_SCU_TAG_EMA_MASK 0X00000700 + +#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_SHIFT 5 +#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_WIDTH 1 +#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_MASK 0X00000020 + +#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_SHIFT 3 +#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_WIDTH 2 +#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_MASK 0X00000018 + +#define APU_RAM_ADJ_2_L2_VICTIM_EMA_SHIFT 0 +#define APU_RAM_ADJ_2_L2_VICTIM_EMA_WIDTH 3 +#define APU_RAM_ADJ_2_L2_VICTIM_EMA_MASK 0X00000007 + +/** + * Register: APU_RAM_ADJ_3 + */ +#define APU_RAM_ADJ_3 ( ( APU_BASEADDR ) + 0X000000FC ) + +#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_SHIFT 29 +#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_WIDTH 1 +#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_MASK 0X20000000 + +#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_SHIFT 27 +#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_WIDTH 2 +#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_MASK 0X18000000 + +#define APU_RAM_ADJ_3_L2_TAGECC_EMA_SHIFT 24 +#define APU_RAM_ADJ_3_L2_TAGECC_EMA_WIDTH 3 +#define APU_RAM_ADJ_3_L2_TAGECC_EMA_MASK 0X07000000 + +#define APU_RAM_ADJ_3_L2_TAG_EMAS_SHIFT 21 +#define APU_RAM_ADJ_3_L2_TAG_EMAS_WIDTH 1 +#define APU_RAM_ADJ_3_L2_TAG_EMAS_MASK 0X00200000 + +#define APU_RAM_ADJ_3_L2_TAG_EMAW_SHIFT 19 +#define APU_RAM_ADJ_3_L2_TAG_EMAW_WIDTH 2 +#define APU_RAM_ADJ_3_L2_TAG_EMAW_MASK 0X00180000 + +#define APU_RAM_ADJ_3_L2_TAG_EMA_SHIFT 16 +#define APU_RAM_ADJ_3_L2_TAG_EMA_WIDTH 3 +#define APU_RAM_ADJ_3_L2_TAG_EMA_MASK 0X00070000 + +#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_SHIFT 13 +#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_WIDTH 1 +#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_MASK 0X00002000 + +#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_SHIFT 11 +#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_WIDTH 2 +#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_MASK 0X00001800 + +#define APU_RAM_ADJ_3_L2_DATAECC_EMA_SHIFT 8 +#define APU_RAM_ADJ_3_L2_DATAECC_EMA_WIDTH 3 +#define APU_RAM_ADJ_3_L2_DATAECC_EMA_MASK 0X00000700 + +#define APU_RAM_ADJ_3_L2_DATA_EMAS_SHIFT 5 +#define APU_RAM_ADJ_3_L2_DATA_EMAS_WIDTH 1 +#define APU_RAM_ADJ_3_L2_DATA_EMAS_MASK 0X00000020 + +#define APU_RAM_ADJ_3_L2_DATA_EMAW_SHIFT 3 +#define APU_RAM_ADJ_3_L2_DATA_EMAW_WIDTH 2 +#define APU_RAM_ADJ_3_L2_DATA_EMAW_MASK 0X00000018 + +#define APU_RAM_ADJ_3_L2_DATA_EMA_SHIFT 0 +#define APU_RAM_ADJ_3_L2_DATA_EMA_WIDTH 3 +#define APU_RAM_ADJ_3_L2_DATA_EMA_MASK 0X00000007 + +/** + * Register: APU_XPD_REG0 + */ +#define APU_XPD_REG0 ( ( APU_BASEADDR ) + 0X00000600 ) + +#define APU_XPD_REG0_PRE_LOAD_SHIFT 0 +#define APU_XPD_REG0_PRE_LOAD_WIDTH 32 +#define APU_XPD_REG0_PRE_LOAD_MASK 0XFFFFFFFF + +/** + * Register: APU_XPD_REG1 + */ +#define APU_XPD_REG1 ( ( APU_BASEADDR ) + 0X00000604 ) + +#define APU_XPD_REG1_EXPECTED_SHIFT 0 +#define APU_XPD_REG1_EXPECTED_WIDTH 32 +#define APU_XPD_REG1_EXPECTED_MASK 0XFFFFFFFF + +/** + * Register: APU_XPD_CTRL0 + */ +#define APU_XPD_CTRL0 ( ( APU_BASEADDR ) + 0X00000608 ) + +#define APU_XPD_CTRL0_DELAY_SPARE_SHIFT 25 +#define APU_XPD_CTRL0_DELAY_SPARE_WIDTH 5 +#define APU_XPD_CTRL0_DELAY_SPARE_MASK 0X3E000000 + +#define APU_XPD_CTRL0_CMP_SEL_SHIFT 24 +#define APU_XPD_CTRL0_CMP_SEL_WIDTH 1 +#define APU_XPD_CTRL0_CMP_SEL_MASK 0X01000000 + +#define APU_XPD_CTRL0_DELAY_CELL_TYPE_SHIFT 19 +#define APU_XPD_CTRL0_DELAY_CELL_TYPE_WIDTH 5 +#define APU_XPD_CTRL0_DELAY_CELL_TYPE_MASK 0X00F80000 + +#define APU_XPD_CTRL0_DELAY_VT_TYPE_SHIFT 17 +#define APU_XPD_CTRL0_DELAY_VT_TYPE_WIDTH 2 +#define APU_XPD_CTRL0_DELAY_VT_TYPE_MASK 0X00060000 + +#define APU_XPD_CTRL0_DELAY_VALUE_SHIFT 6 +#define APU_XPD_CTRL0_DELAY_VALUE_WIDTH 11 +#define APU_XPD_CTRL0_DELAY_VALUE_MASK 0X0001FFC0 + +#define APU_XPD_CTRL0_PATH_SEL_SHIFT 0 +#define APU_XPD_CTRL0_PATH_SEL_WIDTH 6 +#define APU_XPD_CTRL0_PATH_SEL_MASK 0X0000003F + +/** + * Register: APU_XPD_CTRL1 + */ +#define APU_XPD_CTRL1 ( ( APU_BASEADDR ) + 0X0000060C ) + +#define APU_XPD_CTRL1_CLK_SPARE_SHIFT 12 +#define APU_XPD_CTRL1_CLK_SPARE_WIDTH 4 +#define APU_XPD_CTRL1_CLK_SPARE_MASK 0X0000F000 + +#define APU_XPD_CTRL1_CLK_PHASE_SEL_SHIFT 10 +#define APU_XPD_CTRL1_CLK_PHASE_SEL_WIDTH 2 +#define APU_XPD_CTRL1_CLK_PHASE_SEL_MASK 0X00000C00 + +#define APU_XPD_CTRL1_CLK_VT_TYPE_SHIFT 8 +#define APU_XPD_CTRL1_CLK_VT_TYPE_WIDTH 2 +#define APU_XPD_CTRL1_CLK_VT_TYPE_MASK 0X00000300 + +#define APU_XPD_CTRL1_CLK_CELL_TYPE_SHIFT 6 +#define APU_XPD_CTRL1_CLK_CELL_TYPE_WIDTH 2 +#define APU_XPD_CTRL1_CLK_CELL_TYPE_MASK 0X000000C0 + +#define APU_XPD_CTRL1_CLK_INSERT_DLY_SHIFT 2 +#define APU_XPD_CTRL1_CLK_INSERT_DLY_WIDTH 4 +#define APU_XPD_CTRL1_CLK_INSERT_DLY_MASK 0X0000003C + +#define APU_XPD_CTRL1_CLK_SEL_SHIFT 0 +#define APU_XPD_CTRL1_CLK_SEL_WIDTH 2 +#define APU_XPD_CTRL1_CLK_SEL_MASK 0X00000003 + +/** + * Register: APU_XPD_CTRL2 + */ +#define APU_XPD_CTRL2 ( ( APU_BASEADDR ) + 0X00000614 ) + +#define APU_XPD_CTRL2_CTRL_SPARE_SHIFT 1 +#define APU_XPD_CTRL2_CTRL_SPARE_WIDTH 2 +#define APU_XPD_CTRL2_CTRL_SPARE_MASK 0X00000006 + +#define APU_XPD_CTRL2_ENABLE_SHIFT 0 +#define APU_XPD_CTRL2_ENABLE_WIDTH 1 +#define APU_XPD_CTRL2_ENABLE_MASK 0X00000001 + +/** + * Register: APU_XPD_CTRL3 + */ +#define APU_XPD_CTRL3 ( ( APU_BASEADDR ) + 0X00000618 ) + +#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_SHIFT 3 +#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_WIDTH 12 +#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_MASK 0X00007FF8 + +#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_SHIFT 2 +#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_WIDTH 1 +#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_MASK 0X00000004 + +#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_SHIFT 1 +#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_WIDTH 1 +#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_MASK 0X00000002 + +#define APU_XPD_CTRL3_DCYCLE_START_SHIFT 0 +#define APU_XPD_CTRL3_DCYCLE_START_WIDTH 1 +#define APU_XPD_CTRL3_DCYCLE_START_MASK 0X00000001 + +/** + * Register: APU_XPD_SOFT_RST + */ +#define APU_XPD_SOFT_RST ( ( APU_BASEADDR ) + 0X0000061C ) + +#define APU_XPD_SOFT_RST_CLK2_SHIFT 2 +#define APU_XPD_SOFT_RST_CLK2_WIDTH 1 +#define APU_XPD_SOFT_RST_CLK2_MASK 0X00000004 + +#define APU_XPD_SOFT_RST_CLK1_SHIFT 1 +#define APU_XPD_SOFT_RST_CLK1_WIDTH 1 +#define APU_XPD_SOFT_RST_CLK1_MASK 0X00000002 + +#define APU_XPD_SOFT_RST_CLK0_SHIFT 0 +#define APU_XPD_SOFT_RST_CLK0_WIDTH 1 +#define APU_XPD_SOFT_RST_CLK0_MASK 0X00000001 + +/** + * Register: APU_XPD_STAT + */ +#define APU_XPD_STAT ( ( APU_BASEADDR ) + 0X00000620 ) + +#define APU_XPD_STAT_CMP_RESULT_SHIFT 1 +#define APU_XPD_STAT_CMP_RESULT_WIDTH 1 +#define APU_XPD_STAT_CMP_RESULT_MASK 0X00000002 + +#define APU_XPD_STAT_CMP_DONE_SHIFT 0 +#define APU_XPD_STAT_CMP_DONE_WIDTH 1 +#define APU_XPD_STAT_CMP_DONE_MASK 0X00000001 + +#ifdef __cplusplus +} +#endif + + +#endif /* _PM_APU_H_ */ diff --git a/lib/sw_services/xilpm/src/apu/pm_client.c b/lib/sw_services/xilpm/src/apu/pm_client.c new file mode 100644 index 00000000..c22356bc --- /dev/null +++ b/lib/sw_services/xilpm/src/apu/pm_client.c @@ -0,0 +1,152 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * CONTENT + * Each PU client in the system have such file with definitions of + * masters in the subsystem and functions for getting informations + * about the master. + *********************************************************************/ + +#include "pm_client.h" + +static const struct XPm_Ipi apu_ipi = { + .mask = IPI_APU_MASK, + .base = IPI_BASEADDR, + .buffer_base = IPI_BUFFER_APU_BASE, +}; + +static const struct XPm_Master pm_apu_0_master = { + .node_id = NODE_APU_0, + .pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK, + .ipi = &apu_ipi, +}; + +static const struct XPm_Master pm_apu_1_master = { + .node_id = NODE_APU_1, + .pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK, + .ipi = &apu_ipi, +}; + +static const struct XPm_Master pm_apu_2_master = { + .node_id = NODE_APU_2, + .pwrdn_mask = APU_2_PWRCTL_CPUPWRDWNREQ_MASK, + .ipi = &apu_ipi, +}; + +static const struct XPm_Master pm_apu_3_master = { + .node_id = NODE_APU_3, + .pwrdn_mask = APU_3_PWRCTL_CPUPWRDWNREQ_MASK, + .ipi = &apu_ipi, +}; + +/* + * Order in pm_master_all array must match cpu ids + */ +static const struct XPm_Master *const pm_masters_all[] = { + &pm_apu_0_master, + &pm_apu_1_master, + &pm_apu_2_master, + &pm_apu_3_master, +}; + +/** + * pm_get_master() - returns pointer to the master structure + * @cpuid: id of the cpu whose master struct pointer should be returned + * + * Return: pointer to a master structure if master is found, otherwise NULL + */ +const struct XPm_Master *pm_get_master(const uint32_t cpuid) +{ + if (cpuid >=0 && PM_ARRAY_SIZE(pm_masters_all)) { + return pm_masters_all[cpuid]; + } + return NULL; +} + +/** + * pm_get_master_by_node() - returns pointer to the master structure + * @nid: ndoe id of the cpu master + * + * Return: pointer to a master structure if master is found, otherwise NULL + */ +const struct XPm_Master *pm_get_master_by_node(const enum XPmNodeId nid) +{ + uint8_t i; + for (i = 0; i < PM_ARRAY_SIZE(pm_masters_all); i++) { + if (nid == pm_masters_all[i]->node_id) { + return pm_masters_all[i]; + } + } + return NULL; +} + +static uint32_t pm_get_cpuid(const enum XPmNodeId node) +{ + uint32_t i; + for (i = 0; i < PM_ARRAY_SIZE(pm_masters_all); i++) { + if (pm_masters_all[i]->node_id == node) { + return i; + } + } + return UNDEFINED_CPUID; +} + +const enum XPmNodeId subsystem_node = NODE_APU; +const struct XPm_Master *primary_master = &pm_apu_0_master; + +void XPm_ClientSuspend(const struct XPm_Master *const master) +{ + /* Disable interrupts at processor level */ + pm_disable_int(); + /* Set powerdown request */ + pm_write(MASTER_PWRCTL, pm_read(MASTER_PWRCTL) | master->pwrdn_mask); +} + +void XPm_ClientAbortSuspend() +{ + /* Enable interrupts at processor level */ + pm_enable_int(); + /* Clear powerdown request */ + pm_write(MASTER_PWRCTL, pm_read(MASTER_PWRCTL) & ~primary_master->pwrdn_mask); +} + +void XPm_ClientWakeup(const struct XPm_Master *const master) +{ + uint32_t cpuid = pm_get_cpuid(master->node_id); + + if (UNDEFINED_CPUID != cpuid) { + uint32_t val = pm_read(MASTER_PWRCTL); + val &= ~(master->pwrdn_mask); + pm_write(MASTER_PWRCTL, val); + } +} diff --git a/lib/sw_services/xilpm/src/apu/pm_client.h b/lib/sw_services/xilpm/src/apu/pm_client.h new file mode 100644 index 00000000..b97e6254 --- /dev/null +++ b/lib/sw_services/xilpm/src/apu/pm_client.h @@ -0,0 +1,95 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * CONTENT + * File is specific for each PU instance and must exist in order to + * port Power Management code for some new PU. + * Contains PU specific macros and macros to be defined depending on + * the execution environment. + *********************************************************************/ + +#ifndef _PM_CLIENT_H_ +#define _PM_CLIENT_H_ + +#include +#include +#include "pm_apu.h" +#include "pm_defs.h" +#include "pm_common.h" + +#define MASTER_PWRCTL APU_PWRCTL + +#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 0x00000001U +#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 0x00000002U +#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 0x00000004U +#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 0x00000008U + +#define IPI_APU_MASK 0x00000001U + +#define IPI_TRIG_OFFSET 0x00000000 +#define IPI_OBS_OFFSET 0x00000004 + +#define UNDEFINED_CPUID (~0) + +#define pm_read(addr) Xil_In32(addr) +#define pm_write(addr, value) Xil_Out32(addr, value) +#define pm_enable_int() Xil_ExceptionEnable() +#define pm_disable_int() Xil_ExceptionDisable() +#define pm_print(MSG, ...) xil_printf("APU: "MSG,##__VA_ARGS__) +#define pm_this_cpuid() 0U + +/* Conditional debugging prints */ +#ifdef DEBUG_MODE + #define pm_dbg(MSG, ...) \ + do { \ + pm_print(MSG,##__VA_ARGS__); \ + } while (0) +#else + #define pm_dbg(MSG, ...) {} +#endif + +#ifndef bool + #define bool uint8_t + #define true 1U + #define false 0U +#endif + +void XPm_ClientSuspend(const struct XPm_Master *const master); +void XPm_ClientAbortSuspend(); +void XPm_ClientWakeup(const struct XPm_Master *const master); + +/* Do not modify below this line */ +extern const enum XPmNodeId subsystem_node; +extern const struct XPm_Master *primary_master; + +#endif /* _PM_CLIENT_H_ */ diff --git a/lib/sw_services/xilpm/src/common/Makefile b/lib/sw_services/xilpm/src/common/Makefile new file mode 100644 index 00000000..f6762177 --- /dev/null +++ b/lib/sw_services/xilpm/src/common/Makefile @@ -0,0 +1,35 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxilpm.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xilpm_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling xilpm library" + +xilpm_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} +include: + echo "Include files for this library have already been copied." +clean: + rm -rf ${OBJECTS} diff --git a/lib/sw_services/xilpm/src/common/pm_api_sys.c b/lib/sw_services/xilpm/src/common/pm_api_sys.c new file mode 100644 index 00000000..b7abb643 --- /dev/null +++ b/lib/sw_services/xilpm/src/common/pm_api_sys.c @@ -0,0 +1,455 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "pm_client.h" +#include "pm_common.h" +#include "pm_api_sys.h" +#include "pm_ipi_buffer.h" + +/** + * Assigning of argument values into array elements. + * pause and pm_dbg are used for debugging and should be removed in + * final version. + */ +#define PACK_PAYLOAD(pl, arg0, arg1, arg2, arg3, arg4) \ + pl[0] = (uint32_t)arg0; \ + pl[1] = (uint32_t)arg1; \ + pl[2] = (uint32_t)arg2; \ + pl[3] = (uint32_t)arg3; \ + pl[4] = (uint32_t)arg4; \ + pm_dbg("%s(%d, %d, %d, %d)\n", __func__, arg1, arg2, arg3, arg4); + +/** + * pm_get_boot_status() - checks for reason of boot + * + * Function returns information about the boot reason. + * If the boot is not a system startup but a resume, + * power down request bitfield for this processor will be cleared. + * + * @return Returns processor boot status + */ +enum XPmBootStatus XPm_GetBootStatus() +{ + uint32_t pwrdn_req = pm_read(MASTER_PWRCTL); + if (0 != (pwrdn_req & primary_master->pwrdn_mask)) { + pm_write(MASTER_PWRCTL, pwrdn_req & (~primary_master->pwrdn_mask)); + return PM_RESUME; + } else { + return PM_INITIAL_BOOT; + } +} + +/** + * pm_ipi_wait() - wait for pmu to handle request + * @master master which is waiting for PMU to handle request + */ +static enum XPmStatus pm_ipi_wait(const struct XPm_Master *const master) +{ + volatile uint32_t status = 1; + + /* Wait until previous interrupt is handled by PMU */ + while (status) { + status = pm_read(master->ipi->base + IPI_OBS_OFFSET) + & IPI_PMU_PM_INT_MASK; + /* TODO: 1) Use timer to add delay between read attempts */ + /* TODO: 2) Return PM_RET_ERR_TIMEOUT if this times out */ + } + return PM_RET_SUCCESS; +} + +/** + * pm_ipi_send() - Sends IPI request to the PMU + * @master Pointer to the master who is initiating request + * @payload API id and call arguments to be written in IPI buffer + * + * @return Returns status, either success or error+reason + */ +static enum XPmStatus pm_ipi_send(const struct XPm_Master *const master, + uint32_t payload[PAYLOAD_ARG_CNT]) +{ + uint32_t i; + uint32_t offset = 0; + uint32_t buffer_base = master->ipi->buffer_base + + IPI_BUFFER_TARGET_PMU_OFFSET + + IPI_BUFFER_REQ_OFFSET; + + /* Wait until previous interrupt is handled by PMU */ + pm_ipi_wait(master); + /* Write payload into IPI buffer */ + for (i = 0; i < PAYLOAD_ARG_CNT; i++) { + pm_write(buffer_base + offset, payload[i]); + offset += PAYLOAD_ARG_SIZE; + } + /* Generate IPI to PMU */ + pm_write(master->ipi->base + IPI_TRIG_OFFSET, IPI_PMU_PM_INT_MASK); + return PM_RET_SUCCESS; +} + +/** + * pm_ipi_buff_read32() - Reads IPI response after PMU has handled interrupt + * @master Pointer to the master who is waiting and reading response + * @value Used to return value from 2nd IPI buffer element (optional) + * + * @return Returns status, either success or error+reason + */ +static enum XPmStatus pm_ipi_buff_read32(const struct XPm_Master *const master, + uint32_t *value) +{ + uint32_t buffer_base = master->ipi->buffer_base + + IPI_BUFFER_TARGET_PMU_OFFSET + + IPI_BUFFER_RESP_OFFSET; + volatile uint32_t status = 1; + + /* Wait until current IPI interrupt is handled by PMU */ + while (status) { + status = pm_read(master->ipi->base + IPI_OBS_OFFSET) & IPI_PMU_PM_INT_MASK; + /* TODO: 1) Use timer to add delay between read attempts */ + /* TODO: 2) Return PM_RET_ERR_TIMEOUT if this times out */ + } + + /* + * Read response from IPI buffer + * buf-0: success or error+reason + * buf-1: value + * buf-2: unused + * buf-3: unused + */ + if (NULL != value) + *value = pm_read(buffer_base + PAYLOAD_ARG_SIZE); + + return pm_read(buffer_base); +} + +/** + * pm_self_suspend() - PM call for master to suspend itself + * @node Node id of the master or subsystem + * @latency Requested maximum wakeup latency (not supported) + * @state Requested state (not supported) + * + * This is a blocking call, it will return only once PMU has responded + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_SelfSuspend(const enum XPmNodeId nid, + const uint32_t latency, + const uint8_t state) +{ + enum XPmStatus ret; + uint32_t payload[PAYLOAD_ARG_CNT]; + + const struct XPm_Master *master = pm_get_master_by_node(nid); + if (NULL == master) { + /* + * If a subsystem node ID (APU or RPU) was passed then + * the master to be used is the primary master. + * E.g. for the APU the primary master is APU0 + */ + if (subsystem_node == nid) { + master = primary_master; + } else { + return PM_RET_ERROR_ARGS; + } + } + /* + * Do client specific suspend operations + * (e.g. disable interrupts and set powerdown request bit) + */ + XPm_ClientSuspend(master); + /* Send request to the PMU */ + PACK_PAYLOAD(payload, PM_SELF_SUSPEND, nid, latency, state, 0); + ret = pm_ipi_send(master, payload); + if (PM_RET_SUCCESS != ret) + return ret; + /* Wait for PMU to finish handling request */ + return pm_ipi_wait(master); +} + +/** + * pm_req_suspend() - PM call to request for another PU or subsystem to + * be suspended gracefully. + * @target Node id of the targeted PU or subsystem + * @ack Flag to specify whether acknowledge is requested + * @latency Requested wakeup latency (not supported) + * @state Requested state (not supported) + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_ReqSuspend(const enum XPmNodeId target, + const enum XPmRequestAck ack, + const uint32_t latency, const uint8_t state) +{ + enum XPmStatus ret; + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PACK_PAYLOAD(payload, PM_REQ_SUSPEND, target, ack, latency, state); + ret = pm_ipi_send(primary_master, payload); + + if ((PM_RET_SUCCESS == ret) && (REQ_ACK_BLOCKING == ack)) + return pm_ipi_buff_read32(primary_master, NULL); + else + return ret; +} + +/** + * pm_req_wakeup() - PM call for master to wake up selected master or subsystem + * @node Node id of the master or subsystem + * @ack Flag to specify whether acknowledge requested + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_ReqWakeUp(const enum XPmNodeId target, + const enum XPmRequestAck ack) +{ + enum XPmStatus ret; + uint32_t payload[PAYLOAD_ARG_CNT]; + const struct XPm_Master *master = pm_get_master_by_node(target); + + XPm_ClientWakeup(master); + /* Send request to the PMU */ + PACK_PAYLOAD(payload, PM_REQ_WAKEUP, target, ack, 0, 0); + ret = pm_ipi_send(primary_master, payload); + + if ((PM_RET_SUCCESS == ret) && (REQ_ACK_BLOCKING == ack)) + return pm_ipi_buff_read32(primary_master, NULL); + else + return ret; +} + +/** + * pm_force_powerdown() - PM call to request for another PU or subsystem to + * be powered down forcefully + * @target Node id of the targeted PU or subsystem + * @ack Flag to specify whether acknowledge is requested + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_ForcePowerDown(const enum XPmNodeId target, + const enum XPmRequestAck ack) +{ + enum XPmStatus ret; + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PACK_PAYLOAD(payload, PM_FORCE_POWERDOWN, target, ack, 0, 0); + ret = pm_ipi_send(primary_master, payload); + + if ((PM_RET_SUCCESS == ret) && (REQ_ACK_BLOCKING == ack)) + return pm_ipi_buff_read32(primary_master, NULL); + else + return ret; +} + +/** + * pm_abort_suspend() - PM call to announce that a prior suspend request + * is to be aborted. + * @reason Reason for the abort + * + * Calling PU expects the PMU to abort the initiated suspend procedure. + * This is a non-blocking call without any acknowledge. + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_AbortSuspend(const enum XPmAbortReason reason) +{ + enum XPmStatus status; + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* + * Do client specific abort suspend operations + * (e.g. enable interrupts and clear powerdown request bit) + */ + XPm_ClientAbortSuspend(); + /* Send request to the PMU */ + PACK_PAYLOAD(payload, PM_ABORT_SUSPEND, reason, primary_master->node_id, 0, 0); + status = pm_ipi_send(primary_master, payload); + if (PM_RET_SUCCESS == status) + /* Wait for PMU to finish handling request */ + status = pm_ipi_wait(primary_master); + return status; +} + +/** + * pm_set_wakeup_source() - PM call to specify the wakeup source while suspended + * @target Node id of the targeted PU or subsystem + * @wkup_node Node id of the wakeup peripheral + * @enable Enable or disable the specified peripheral as wake source + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_SetWakeUpSource(const enum XPmNodeId target, + const enum XPmNodeId wkup_node, + const uint8_t enable) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + PACK_PAYLOAD(payload, PM_SET_WAKEUP_SOURCE, target, wkup_node, enable, 0); + return pm_ipi_send(primary_master, payload); +} + +/** + * pm_system_shutdown() - PM call to request a system shutdown or restart + * @restart Shutdown or restart? 0 for shutdown, 1 for restart + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_SystemShutdown(const uint8_t restart) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + PACK_PAYLOAD(payload, PM_SYSTEM_SHUTDOWN, restart, 0, 0, 0); + return pm_ipi_send(primary_master, payload); +} + +/* APIs for managing PM slaves: */ + +/** + * pm_req_node() - PM call to request a node with specifc capabilities + * @node Node id of the slave + * @capabilities Requested capabilities of the slave + * @qos Quality of service (not supported) + * @ack Flag to specify whether acknowledge is requested + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_ReqNode(const enum XPmNodeId node, + const uint32_t capabilities, + const uint32_t qos, + const enum XPmRequestAck ack) +{ + enum XPmStatus ret; + uint32_t payload[PAYLOAD_ARG_CNT]; + + PACK_PAYLOAD(payload, PM_REQ_NODE, node, capabilities, qos, ack); + ret = pm_ipi_send(primary_master, payload); + + if ((PM_RET_SUCCESS == ret) && (REQ_ACK_BLOCKING == ack)) + return pm_ipi_buff_read32(primary_master, NULL); + else + return ret; +} + +/** + * pm_set_requirement() - PM call to set requirement for PM slaves + * @node Node id of the slave + * @capabilities Requested capabilities of the slave + * @qos Quality of service (not supported) + * @ack Flag to specify whether acknowledge is requested + * + * This API function is to be used for slaves a PU already has requested + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_SetRequirement(const enum XPmNodeId nid, + const uint32_t capabilities, + const uint32_t qos, + const enum XPmRequestAck ack) +{ + enum XPmStatus ret; + uint32_t payload[PAYLOAD_ARG_CNT]; + PACK_PAYLOAD(payload, PM_SET_REQUIREMENT, nid, capabilities, qos, ack); + ret = pm_ipi_send(primary_master, payload); + + if ((PM_RET_SUCCESS == ret) && (REQ_ACK_BLOCKING == ack)) + return pm_ipi_buff_read32(primary_master, NULL); + else + return ret; +} + +/** + * pm_release_node() - PM call to release a node + * @node Node id of the slave + * @latency Requested maximum wakeup latency + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_ReleaseNode(const enum XPmNodeId node, + const uint32_t latency) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + PACK_PAYLOAD(payload, PM_RELEASE_NODE, node, latency, 0, 0); + return pm_ipi_send(primary_master, payload); +} + +/** + * pm_set_max_latency() - PM call to set wakeup latency requirements + * @node Node id of the slave + * @latency Requested maximum wakeup latency + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_SetMaxLatency(const enum XPmNodeId node, + const uint32_t latency) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PACK_PAYLOAD(payload, PM_SET_MAX_LATENCY, node, latency, 0, 0); + return pm_ipi_send(primary_master, payload); +} + +/* Miscellaneous API functions */ + +/** + * pm_get_api_version() - Get version number of PMU PM firmware + * @version Returns 32-bit version number of PMU Power Management Firmware + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_GetApiVersion(uint32_t *version) +{ + enum XPmStatus ret; + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PACK_PAYLOAD(payload, PM_GET_API_VERSION, 0, 0, 0, 0); + ret = pm_ipi_send(primary_master, payload); + + if (PM_RET_SUCCESS != ret) + return ret; + + /* Return result from IPI return buffer */ + return pm_ipi_buff_read32(primary_master, version); +} + + +/** + * pm_get_node_status() - PM call to request a node's current power state + * @node Node id of the slave + * + * @return Returns status, either success or error+reason + */ +enum XPmStatus XPm_GetNodeStatus(const enum XPmNodeId node) +{ + /* TODO: Add power state argument!! */ + uint32_t payload[PAYLOAD_ARG_CNT]; + PACK_PAYLOAD(payload, PM_GET_NODE_STATUS, node, 0, 0, 0); + return pm_ipi_send(primary_master, payload); +} diff --git a/lib/sw_services/xilpm/src/common/pm_api_sys.h b/lib/sw_services/xilpm/src/common/pm_api_sys.h new file mode 100644 index 00000000..bcdf0a2b --- /dev/null +++ b/lib/sw_services/xilpm/src/common/pm_api_sys.h @@ -0,0 +1,91 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _PM_API_SYS_H_ +#define _PM_API_SYS_H_ + +#include +#include "pm_defs.h" + +enum XPmBootStatus XPm_GetBootStatus(); + +/********************************************************** + * System-level API function declarations + **********************************************************/ +enum XPmStatus XPm_ReqSuspend(const enum XPmNodeId node, + const enum XPmRequestAck ack, + const uint32_t latency, + const uint8_t state); + +enum XPmStatus XPm_SelfSuspend(const enum XPmNodeId node, + const uint32_t latency, + const uint8_t state); + +enum XPmStatus XPm_ForcePowerDown(const enum XPmNodeId node, + const enum XPmRequestAck ack); + +enum XPmStatus XPm_AbortSuspend(const enum XPmAbortReason reason); + +enum XPmStatus XPm_ReqWakeUp(const enum XPmNodeId node, + const enum XPmRequestAck ack); + +enum XPmStatus XPm_SetWakeUpSource(const enum XPmNodeId target, + const enum XPmNodeId wkup_node, + const uint8_t enable); + +enum XPmStatus XPm_SystemShutdown(const uint8_t restart); + + + +/* API functions for managing PM Slaves */ +enum XPmStatus XPm_ReqNode(const enum XPmNodeId node, + const uint32_t capabilities, + const uint32_t qos, + const enum XPmRequestAck ack); +enum XPmStatus XPm_ReleaseNode(const enum XPmNodeId node, + const uint32_t latency); +enum XPmStatus XPm_SetRequirement(const enum XPmNodeId node, + const uint32_t capabilities, + const uint32_t qos, + const enum XPmRequestAck ack); +enum XPmStatus XPm_SetMaxLatency(const enum XPmNodeId node, + const uint32_t latency); + +/* Miscellaneous API functions */ +enum XPmStatus XPm_GetApiVersion(uint32_t *version); + +enum XPmStatus XPm_GetNodeStatus(const enum XPmNodeId node); + + + + +#endif /* _PM_API_SYS_H_ */ diff --git a/lib/sw_services/xilpm/src/common/pm_common.h b/lib/sw_services/xilpm/src/common/pm_common.h new file mode 100644 index 00000000..6bf75021 --- /dev/null +++ b/lib/sw_services/xilpm/src/common/pm_common.h @@ -0,0 +1,78 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************** + * CONTENT + * Definitions of commonly used macros and data types needed for + * PU Power Management. This file should be common for all PU's. + *********************************************************************/ + +#ifndef _PM_COMMON_H_ +#define _PM_COMMON_H_ + +#include "pm_ipi.h" +#include "pm_ipi_buffer.h" +#include "pm_defs.h" + +#define DEBUG_MODE + +#define PM_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) + +#define PAYLOAD_ARG_CNT 5U +#define PAYLOAD_ARG_SIZE 4U /* size in bytes */ + +/* Power Management IPI interrupt number */ +#define PM_INT_NUM 0 +#define IPI_PMU_PM_INT_BASE (IPI_PMU_0_TRIG + (PM_INT_NUM * 0x1000)) +#define IPI_PMU_PM_INT_MASK (IPI_APU_ISR_PMU_0_MASK << PM_INT_NUM) +#if (PM_INT_NUM < 0 || PM_INT_NUM > 3) + #error PM_INT_NUM value out of range +#endif + +struct XPm_Ipi { + const uint32_t mask; + const uint32_t base; + const uint32_t buffer_base; +}; + +struct XPm_Master { + const enum XPmNodeId node_id; + const uint32_t pwrdn_mask; + const struct XPm_Ipi *const ipi; +}; + +const enum XPmNodeId pm_get_subsystem_node(void); +const struct XPm_Master *pm_get_master(const uint32_t cpuid); +const struct XPm_Master *pm_get_master_by_node(const enum XPmNodeId nid); + + +#endif /* _PM_COMMON_H_ */ diff --git a/lib/sw_services/xilpm/src/common/pm_defs.h b/lib/sw_services/xilpm/src/common/pm_defs.h new file mode 100644 index 00000000..b0bcb698 --- /dev/null +++ b/lib/sw_services/xilpm/src/common/pm_defs.h @@ -0,0 +1,196 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef PM_DEFS_H_ +#define PM_DEFS_H_ + +/********************************************************************* + * Macro definitions + ********************************************************************/ + +/* + * Version number is a 32bit value, like: + * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR + */ +#define PM_VERSION_MAJOR 0 +#define PM_VERSION_MINOR 1 + +#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR) + +/* Capabilities for RAM */ +#define PM_CAP_ACCESS 0x1U +#define PM_CAP_CONTEXT 0x2U + +#define MAX_LATENCY (~0U) +#define MAX_QOS 100U + +/********************************************************************* + * Enum definitions + ********************************************************************/ + +enum XPmApiId { + /* Miscellaneous API functions: */ + PM_GET_API_VERSION = 1, /* Do not change or move */ + PM_SET_CONFIGURATION = 2, + PM_GET_NODE_STATUS = 3, + PM_GET_OP_CHARACTERISTIC = 4, + PM_REGISTER_NOTIFIER = 5, + /* API for suspending of PUs: */ + PM_REQ_SUSPEND = 6, + PM_SELF_SUSPEND = 7, + PM_FORCE_POWERDOWN = 8, + PM_ABORT_SUSPEND = 9, + PM_REQ_WAKEUP = 10, + PM_SET_WAKEUP_SOURCE = 11, + PM_SYSTEM_SHUTDOWN = 12, + /* API for managing PM slaves: */ + PM_REQ_NODE = 13, + PM_RELEASE_NODE = 14, + PM_SET_REQUIREMENT = 15, + PM_SET_MAX_LATENCY = 16, + /* Direct control API functions: */ + PM_CLOCK_REQUEST = 17, + PM_CLOCK_RELEASE = 18, + PM_CLOCK_SET_RATE = 19, + PM_CLOCK_GET_RATE = 20, + PM_CLOCK_GET_RATE_INFO = 21, + PM_RESET_ASSERT = 22, + PM_RESET_GET_STATUS = 23, + PM_MMIO_WRITE = 24, + PM_MMIO_READ = 25, +}; + +#define PM_API_MIN 1 +#define PM_API_MAX 25 + +enum XPmApiCbId { + PM_INIT_SUSPEND_CB = 30, + PM_ACKNOWLEDGE_CB, + PM_NOTIFY_CB, +}; + +enum XPmNodeId { + NODE_UNKNOWN = 0, + NODE_APU, + NODE_APU_0, + NODE_APU_1, + NODE_APU_2, + NODE_APU_3, + NODE_RPU, + NODE_RPU_0, + NODE_RPU_1, + NODE_PL, + NODE_FPD, + NODE_OCM_BANK_0, + NODE_OCM_BANK_1, + NODE_OCM_BANK_2, + NODE_OCM_BANK_3, + NODE_TCM_0_A, + NODE_TCM_0_B, + NODE_TCM_1_A, + NODE_TCM_1_B, + NODE_L2, + NODE_GPU_PP_0, + NODE_GPU_PP_1, + NODE_USB_0, + NODE_USB_1, + NODE_TTC_0, +}; + +enum XPmRequestAck { + REQ_ACK_NO = 1, + REQ_ACK_BLOCKING = 2, + REQ_ACK_CB_STANDARD = 3, + REQ_ACK_CB_ERROR = 4, +}; + +enum XPmAbortReason { + ABORT_REASON_WKUP_EVENT = 100, + ABORT_REASON_PU_BUSY, + ABORT_REASON_NO_PWRDN, + ABORT_REASON_UNKNOWN, +}; + +enum XPmSuspendReason { + SUSPEND_REASON_PU_REQ = 201, + SUSPEND_REASON_ALERT, + SUSPEND_REASON_SYS_SHUTDOWN, +}; + +enum XPmRamState { + PM_RAM_STATE_OFF = 1, + PM_RAM_STATE_RETENTION, + PM_RAM_STATE_ON, +}; + +enum XPmOpCharType { + PM_OPCHAR_TYPE_POWER = 1, + PM_OPCHAR_TYPE_ENERGY = 2, + PM_OPCHAR_TYPE_TEMP = 3, +}; + +/** + * @PM_RET_SUCCESS: success + * @PM_RET_ERROR_ARGS: illegal arguments provided + * @PM_RET_ERROR_ACCESS: access rights violation + * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU + * @PM_RET_ERROR_NOTSUPPORTED: feature not supported + * @PM_RET_ERROR_PROC: node is not a processor node + * @PM_RET_ERROR_API_ID: illegal API ID + * @PM_RET_ERROR_OTHER: other error + */ +enum XPmStatus { + PM_RET_SUCCESS = 0, + PM_RET_ERROR_ARGS = 1, + PM_RET_ERROR_ACCESS = 2, + PM_RET_ERROR_TIMEOUT = 3, + PM_RET_ERROR_NOTSUPPORTED = 4, + PM_RET_ERROR_PROC = 5, + PM_RET_ERROR_API_ID = 6, + PM_RET_ERROR_FAILURE = 7, + PM_RET_ERROR_COMMUNIC = 8, + PM_RET_ERROR_DOUBLEREQ = 9, + PM_RET_ERROR_OTHER = 25, +}; + +/** + * @PM_INITIAL_BOOT: boot is a fresh system startup + * @PM_RESUME: boot is a resume + * @PM_BOOT_ERROR: error, boot cause cannot be identified + */ +enum XPmBootStatus { + PM_INITIAL_BOOT, + PM_RESUME, + PM_BOOT_ERROR, +}; + +#endif /* PM_DEFS_H_ */ diff --git a/lib/sw_services/xilpm/src/common/pm_ipi.h b/lib/sw_services/xilpm/src/common/pm_ipi.h new file mode 100644 index 00000000..0418c52c --- /dev/null +++ b/lib/sw_services/xilpm/src/common/pm_ipi.h @@ -0,0 +1,3347 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _IPI_H_ +#define _IPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * IPI Base Address + */ +#define IPI_BASEADDR 0XFF300000 + +/** + * Register: IPI_APU_TRIG + */ +#define IPI_APU_TRIG ( ( IPI_BASEADDR ) + 0X00000000 ) + +#define IPI_APU_TRIG_PL_3_SHIFT 27 +#define IPI_APU_TRIG_PL_3_WIDTH 1 +#define IPI_APU_TRIG_PL_3_MASK 0X08000000 + +#define IPI_APU_TRIG_PL_2_SHIFT 26 +#define IPI_APU_TRIG_PL_2_WIDTH 1 +#define IPI_APU_TRIG_PL_2_MASK 0X04000000 + +#define IPI_APU_TRIG_PL_1_SHIFT 25 +#define IPI_APU_TRIG_PL_1_WIDTH 1 +#define IPI_APU_TRIG_PL_1_MASK 0X02000000 + +#define IPI_APU_TRIG_PL_0_SHIFT 24 +#define IPI_APU_TRIG_PL_0_WIDTH 1 +#define IPI_APU_TRIG_PL_0_MASK 0X01000000 + +#define IPI_APU_TRIG_PMU_3_SHIFT 19 +#define IPI_APU_TRIG_PMU_3_WIDTH 1 +#define IPI_APU_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_APU_TRIG_PMU_2_SHIFT 18 +#define IPI_APU_TRIG_PMU_2_WIDTH 1 +#define IPI_APU_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_APU_TRIG_PMU_1_SHIFT 17 +#define IPI_APU_TRIG_PMU_1_WIDTH 1 +#define IPI_APU_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_APU_TRIG_PMU_0_SHIFT 16 +#define IPI_APU_TRIG_PMU_0_WIDTH 1 +#define IPI_APU_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_APU_TRIG_RPU_1_SHIFT 9 +#define IPI_APU_TRIG_RPU_1_WIDTH 1 +#define IPI_APU_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_APU_TRIG_RPU_0_SHIFT 8 +#define IPI_APU_TRIG_RPU_0_WIDTH 1 +#define IPI_APU_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_APU_TRIG_APU_SHIFT 0 +#define IPI_APU_TRIG_APU_WIDTH 1 +#define IPI_APU_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_APU_OBS + */ +#define IPI_APU_OBS ( ( IPI_BASEADDR ) + 0X00000004 ) + +#define IPI_APU_OBS_PL_3_SHIFT 27 +#define IPI_APU_OBS_PL_3_WIDTH 1 +#define IPI_APU_OBS_PL_3_MASK 0X08000000 + +#define IPI_APU_OBS_PL_2_SHIFT 26 +#define IPI_APU_OBS_PL_2_WIDTH 1 +#define IPI_APU_OBS_PL_2_MASK 0X04000000 + +#define IPI_APU_OBS_PL_1_SHIFT 25 +#define IPI_APU_OBS_PL_1_WIDTH 1 +#define IPI_APU_OBS_PL_1_MASK 0X02000000 + +#define IPI_APU_OBS_PL_0_SHIFT 24 +#define IPI_APU_OBS_PL_0_WIDTH 1 +#define IPI_APU_OBS_PL_0_MASK 0X01000000 + +#define IPI_APU_OBS_PMU_3_SHIFT 19 +#define IPI_APU_OBS_PMU_3_WIDTH 1 +#define IPI_APU_OBS_PMU_3_MASK 0X00080000 + +#define IPI_APU_OBS_PMU_2_SHIFT 18 +#define IPI_APU_OBS_PMU_2_WIDTH 1 +#define IPI_APU_OBS_PMU_2_MASK 0X00040000 + +#define IPI_APU_OBS_PMU_1_SHIFT 17 +#define IPI_APU_OBS_PMU_1_WIDTH 1 +#define IPI_APU_OBS_PMU_1_MASK 0X00020000 + +#define IPI_APU_OBS_PMU_0_SHIFT 16 +#define IPI_APU_OBS_PMU_0_WIDTH 1 +#define IPI_APU_OBS_PMU_0_MASK 0X00010000 + +#define IPI_APU_OBS_RPU_1_SHIFT 9 +#define IPI_APU_OBS_RPU_1_WIDTH 1 +#define IPI_APU_OBS_RPU_1_MASK 0X00000200 + +#define IPI_APU_OBS_RPU_0_SHIFT 8 +#define IPI_APU_OBS_RPU_0_WIDTH 1 +#define IPI_APU_OBS_RPU_0_MASK 0X00000100 + +#define IPI_APU_OBS_APU_SHIFT 0 +#define IPI_APU_OBS_APU_WIDTH 1 +#define IPI_APU_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_APU_ISR + */ +#define IPI_APU_ISR ( ( IPI_BASEADDR ) + 0X00000010 ) + +#define IPI_APU_ISR_PL_3_SHIFT 27 +#define IPI_APU_ISR_PL_3_WIDTH 1 +#define IPI_APU_ISR_PL_3_MASK 0X08000000 + +#define IPI_APU_ISR_PL_2_SHIFT 26 +#define IPI_APU_ISR_PL_2_WIDTH 1 +#define IPI_APU_ISR_PL_2_MASK 0X04000000 + +#define IPI_APU_ISR_PL_1_SHIFT 25 +#define IPI_APU_ISR_PL_1_WIDTH 1 +#define IPI_APU_ISR_PL_1_MASK 0X02000000 + +#define IPI_APU_ISR_PL_0_SHIFT 24 +#define IPI_APU_ISR_PL_0_WIDTH 1 +#define IPI_APU_ISR_PL_0_MASK 0X01000000 + +#define IPI_APU_ISR_PMU_3_SHIFT 19 +#define IPI_APU_ISR_PMU_3_WIDTH 1 +#define IPI_APU_ISR_PMU_3_MASK 0X00080000 + +#define IPI_APU_ISR_PMU_2_SHIFT 18 +#define IPI_APU_ISR_PMU_2_WIDTH 1 +#define IPI_APU_ISR_PMU_2_MASK 0X00040000 + +#define IPI_APU_ISR_PMU_1_SHIFT 17 +#define IPI_APU_ISR_PMU_1_WIDTH 1 +#define IPI_APU_ISR_PMU_1_MASK 0X00020000 + +#define IPI_APU_ISR_PMU_0_SHIFT 16 +#define IPI_APU_ISR_PMU_0_WIDTH 1 +#define IPI_APU_ISR_PMU_0_MASK 0X00010000 + +#define IPI_APU_ISR_RPU_1_SHIFT 9 +#define IPI_APU_ISR_RPU_1_WIDTH 1 +#define IPI_APU_ISR_RPU_1_MASK 0X00000200 + +#define IPI_APU_ISR_RPU_0_SHIFT 8 +#define IPI_APU_ISR_RPU_0_WIDTH 1 +#define IPI_APU_ISR_RPU_0_MASK 0X00000100 + +#define IPI_APU_ISR_APU_SHIFT 0 +#define IPI_APU_ISR_APU_WIDTH 1 +#define IPI_APU_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_APU_IMR + */ +#define IPI_APU_IMR ( ( IPI_BASEADDR ) + 0X00000014 ) + +#define IPI_APU_IMR_PL_3_SHIFT 27 +#define IPI_APU_IMR_PL_3_WIDTH 1 +#define IPI_APU_IMR_PL_3_MASK 0X08000000 + +#define IPI_APU_IMR_PL_2_SHIFT 26 +#define IPI_APU_IMR_PL_2_WIDTH 1 +#define IPI_APU_IMR_PL_2_MASK 0X04000000 + +#define IPI_APU_IMR_PL_1_SHIFT 25 +#define IPI_APU_IMR_PL_1_WIDTH 1 +#define IPI_APU_IMR_PL_1_MASK 0X02000000 + +#define IPI_APU_IMR_PL_0_SHIFT 24 +#define IPI_APU_IMR_PL_0_WIDTH 1 +#define IPI_APU_IMR_PL_0_MASK 0X01000000 + +#define IPI_APU_IMR_PMU_3_SHIFT 19 +#define IPI_APU_IMR_PMU_3_WIDTH 1 +#define IPI_APU_IMR_PMU_3_MASK 0X00080000 + +#define IPI_APU_IMR_PMU_2_SHIFT 18 +#define IPI_APU_IMR_PMU_2_WIDTH 1 +#define IPI_APU_IMR_PMU_2_MASK 0X00040000 + +#define IPI_APU_IMR_PMU_1_SHIFT 17 +#define IPI_APU_IMR_PMU_1_WIDTH 1 +#define IPI_APU_IMR_PMU_1_MASK 0X00020000 + +#define IPI_APU_IMR_PMU_0_SHIFT 16 +#define IPI_APU_IMR_PMU_0_WIDTH 1 +#define IPI_APU_IMR_PMU_0_MASK 0X00010000 + +#define IPI_APU_IMR_RPU_1_SHIFT 9 +#define IPI_APU_IMR_RPU_1_WIDTH 1 +#define IPI_APU_IMR_RPU_1_MASK 0X00000200 + +#define IPI_APU_IMR_RPU_0_SHIFT 8 +#define IPI_APU_IMR_RPU_0_WIDTH 1 +#define IPI_APU_IMR_RPU_0_MASK 0X00000100 + +#define IPI_APU_IMR_APU_SHIFT 0 +#define IPI_APU_IMR_APU_WIDTH 1 +#define IPI_APU_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_APU_IER + */ +#define IPI_APU_IER ( ( IPI_BASEADDR ) + 0X00000018 ) + +#define IPI_APU_IER_PL_3_SHIFT 27 +#define IPI_APU_IER_PL_3_WIDTH 1 +#define IPI_APU_IER_PL_3_MASK 0X08000000 + +#define IPI_APU_IER_PL_2_SHIFT 26 +#define IPI_APU_IER_PL_2_WIDTH 1 +#define IPI_APU_IER_PL_2_MASK 0X04000000 + +#define IPI_APU_IER_PL_1_SHIFT 25 +#define IPI_APU_IER_PL_1_WIDTH 1 +#define IPI_APU_IER_PL_1_MASK 0X02000000 + +#define IPI_APU_IER_PL_0_SHIFT 24 +#define IPI_APU_IER_PL_0_WIDTH 1 +#define IPI_APU_IER_PL_0_MASK 0X01000000 + +#define IPI_APU_IER_PMU_3_SHIFT 19 +#define IPI_APU_IER_PMU_3_WIDTH 1 +#define IPI_APU_IER_PMU_3_MASK 0X00080000 + +#define IPI_APU_IER_PMU_2_SHIFT 18 +#define IPI_APU_IER_PMU_2_WIDTH 1 +#define IPI_APU_IER_PMU_2_MASK 0X00040000 + +#define IPI_APU_IER_PMU_1_SHIFT 17 +#define IPI_APU_IER_PMU_1_WIDTH 1 +#define IPI_APU_IER_PMU_1_MASK 0X00020000 + +#define IPI_APU_IER_PMU_0_SHIFT 16 +#define IPI_APU_IER_PMU_0_WIDTH 1 +#define IPI_APU_IER_PMU_0_MASK 0X00010000 + +#define IPI_APU_IER_RPU_1_SHIFT 9 +#define IPI_APU_IER_RPU_1_WIDTH 1 +#define IPI_APU_IER_RPU_1_MASK 0X00000200 + +#define IPI_APU_IER_RPU_0_SHIFT 8 +#define IPI_APU_IER_RPU_0_WIDTH 1 +#define IPI_APU_IER_RPU_0_MASK 0X00000100 + +#define IPI_APU_IER_APU_SHIFT 0 +#define IPI_APU_IER_APU_WIDTH 1 +#define IPI_APU_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_APU_IDR + */ +#define IPI_APU_IDR ( ( IPI_BASEADDR ) + 0X0000001C ) + +#define IPI_APU_IDR_PL_3_SHIFT 27 +#define IPI_APU_IDR_PL_3_WIDTH 1 +#define IPI_APU_IDR_PL_3_MASK 0X08000000 + +#define IPI_APU_IDR_PL_2_SHIFT 26 +#define IPI_APU_IDR_PL_2_WIDTH 1 +#define IPI_APU_IDR_PL_2_MASK 0X04000000 + +#define IPI_APU_IDR_PL_1_SHIFT 25 +#define IPI_APU_IDR_PL_1_WIDTH 1 +#define IPI_APU_IDR_PL_1_MASK 0X02000000 + +#define IPI_APU_IDR_PL_0_SHIFT 24 +#define IPI_APU_IDR_PL_0_WIDTH 1 +#define IPI_APU_IDR_PL_0_MASK 0X01000000 + +#define IPI_APU_IDR_PMU_3_SHIFT 19 +#define IPI_APU_IDR_PMU_3_WIDTH 1 +#define IPI_APU_IDR_PMU_3_MASK 0X00080000 + +#define IPI_APU_IDR_PMU_2_SHIFT 18 +#define IPI_APU_IDR_PMU_2_WIDTH 1 +#define IPI_APU_IDR_PMU_2_MASK 0X00040000 + +#define IPI_APU_IDR_PMU_1_SHIFT 17 +#define IPI_APU_IDR_PMU_1_WIDTH 1 +#define IPI_APU_IDR_PMU_1_MASK 0X00020000 + +#define IPI_APU_IDR_PMU_0_SHIFT 16 +#define IPI_APU_IDR_PMU_0_WIDTH 1 +#define IPI_APU_IDR_PMU_0_MASK 0X00010000 + +#define IPI_APU_IDR_RPU_1_SHIFT 9 +#define IPI_APU_IDR_RPU_1_WIDTH 1 +#define IPI_APU_IDR_RPU_1_MASK 0X00000200 + +#define IPI_APU_IDR_RPU_0_SHIFT 8 +#define IPI_APU_IDR_RPU_0_WIDTH 1 +#define IPI_APU_IDR_RPU_0_MASK 0X00000100 + +#define IPI_APU_IDR_APU_SHIFT 0 +#define IPI_APU_IDR_APU_WIDTH 1 +#define IPI_APU_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_0_TRIG + */ +#define IPI_RPU_0_TRIG ( ( IPI_BASEADDR ) + 0X00010000 ) + +#define IPI_RPU_0_TRIG_PL_3_SHIFT 27 +#define IPI_RPU_0_TRIG_PL_3_WIDTH 1 +#define IPI_RPU_0_TRIG_PL_3_MASK 0X08000000 + +#define IPI_RPU_0_TRIG_PL_2_SHIFT 26 +#define IPI_RPU_0_TRIG_PL_2_WIDTH 1 +#define IPI_RPU_0_TRIG_PL_2_MASK 0X04000000 + +#define IPI_RPU_0_TRIG_PL_1_SHIFT 25 +#define IPI_RPU_0_TRIG_PL_1_WIDTH 1 +#define IPI_RPU_0_TRIG_PL_1_MASK 0X02000000 + +#define IPI_RPU_0_TRIG_PL_0_SHIFT 24 +#define IPI_RPU_0_TRIG_PL_0_WIDTH 1 +#define IPI_RPU_0_TRIG_PL_0_MASK 0X01000000 + +#define IPI_RPU_0_TRIG_PMU_3_SHIFT 19 +#define IPI_RPU_0_TRIG_PMU_3_WIDTH 1 +#define IPI_RPU_0_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_RPU_0_TRIG_PMU_2_SHIFT 18 +#define IPI_RPU_0_TRIG_PMU_2_WIDTH 1 +#define IPI_RPU_0_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_RPU_0_TRIG_PMU_1_SHIFT 17 +#define IPI_RPU_0_TRIG_PMU_1_WIDTH 1 +#define IPI_RPU_0_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_RPU_0_TRIG_PMU_0_SHIFT 16 +#define IPI_RPU_0_TRIG_PMU_0_WIDTH 1 +#define IPI_RPU_0_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_RPU_0_TRIG_RPU_1_SHIFT 9 +#define IPI_RPU_0_TRIG_RPU_1_WIDTH 1 +#define IPI_RPU_0_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_RPU_0_TRIG_RPU_0_SHIFT 8 +#define IPI_RPU_0_TRIG_RPU_0_WIDTH 1 +#define IPI_RPU_0_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_RPU_0_TRIG_APU_SHIFT 0 +#define IPI_RPU_0_TRIG_APU_WIDTH 1 +#define IPI_RPU_0_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_0_OBS + */ +#define IPI_RPU_0_OBS ( ( IPI_BASEADDR ) + 0X00010004 ) + +#define IPI_RPU_0_OBS_PL_3_SHIFT 27 +#define IPI_RPU_0_OBS_PL_3_WIDTH 1 +#define IPI_RPU_0_OBS_PL_3_MASK 0X08000000 + +#define IPI_RPU_0_OBS_PL_2_SHIFT 26 +#define IPI_RPU_0_OBS_PL_2_WIDTH 1 +#define IPI_RPU_0_OBS_PL_2_MASK 0X04000000 + +#define IPI_RPU_0_OBS_PL_1_SHIFT 25 +#define IPI_RPU_0_OBS_PL_1_WIDTH 1 +#define IPI_RPU_0_OBS_PL_1_MASK 0X02000000 + +#define IPI_RPU_0_OBS_PL_0_SHIFT 24 +#define IPI_RPU_0_OBS_PL_0_WIDTH 1 +#define IPI_RPU_0_OBS_PL_0_MASK 0X01000000 + +#define IPI_RPU_0_OBS_PMU_3_SHIFT 19 +#define IPI_RPU_0_OBS_PMU_3_WIDTH 1 +#define IPI_RPU_0_OBS_PMU_3_MASK 0X00080000 + +#define IPI_RPU_0_OBS_PMU_2_SHIFT 18 +#define IPI_RPU_0_OBS_PMU_2_WIDTH 1 +#define IPI_RPU_0_OBS_PMU_2_MASK 0X00040000 + +#define IPI_RPU_0_OBS_PMU_1_SHIFT 17 +#define IPI_RPU_0_OBS_PMU_1_WIDTH 1 +#define IPI_RPU_0_OBS_PMU_1_MASK 0X00020000 + +#define IPI_RPU_0_OBS_PMU_0_SHIFT 16 +#define IPI_RPU_0_OBS_PMU_0_WIDTH 1 +#define IPI_RPU_0_OBS_PMU_0_MASK 0X00010000 + +#define IPI_RPU_0_OBS_RPU_1_SHIFT 9 +#define IPI_RPU_0_OBS_RPU_1_WIDTH 1 +#define IPI_RPU_0_OBS_RPU_1_MASK 0X00000200 + +#define IPI_RPU_0_OBS_RPU_0_SHIFT 8 +#define IPI_RPU_0_OBS_RPU_0_WIDTH 1 +#define IPI_RPU_0_OBS_RPU_0_MASK 0X00000100 + +#define IPI_RPU_0_OBS_APU_SHIFT 0 +#define IPI_RPU_0_OBS_APU_WIDTH 1 +#define IPI_RPU_0_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_0_ISR + */ +#define IPI_RPU_0_ISR ( ( IPI_BASEADDR ) + 0X00010010 ) + +#define IPI_RPU_0_ISR_PL_3_SHIFT 27 +#define IPI_RPU_0_ISR_PL_3_WIDTH 1 +#define IPI_RPU_0_ISR_PL_3_MASK 0X08000000 + +#define IPI_RPU_0_ISR_PL_2_SHIFT 26 +#define IPI_RPU_0_ISR_PL_2_WIDTH 1 +#define IPI_RPU_0_ISR_PL_2_MASK 0X04000000 + +#define IPI_RPU_0_ISR_PL_1_SHIFT 25 +#define IPI_RPU_0_ISR_PL_1_WIDTH 1 +#define IPI_RPU_0_ISR_PL_1_MASK 0X02000000 + +#define IPI_RPU_0_ISR_PL_0_SHIFT 24 +#define IPI_RPU_0_ISR_PL_0_WIDTH 1 +#define IPI_RPU_0_ISR_PL_0_MASK 0X01000000 + +#define IPI_RPU_0_ISR_PMU_3_SHIFT 19 +#define IPI_RPU_0_ISR_PMU_3_WIDTH 1 +#define IPI_RPU_0_ISR_PMU_3_MASK 0X00080000 + +#define IPI_RPU_0_ISR_PMU_2_SHIFT 18 +#define IPI_RPU_0_ISR_PMU_2_WIDTH 1 +#define IPI_RPU_0_ISR_PMU_2_MASK 0X00040000 + +#define IPI_RPU_0_ISR_PMU_1_SHIFT 17 +#define IPI_RPU_0_ISR_PMU_1_WIDTH 1 +#define IPI_RPU_0_ISR_PMU_1_MASK 0X00020000 + +#define IPI_RPU_0_ISR_PMU_0_SHIFT 16 +#define IPI_RPU_0_ISR_PMU_0_WIDTH 1 +#define IPI_RPU_0_ISR_PMU_0_MASK 0X00010000 + +#define IPI_RPU_0_ISR_RPU_1_SHIFT 9 +#define IPI_RPU_0_ISR_RPU_1_WIDTH 1 +#define IPI_RPU_0_ISR_RPU_1_MASK 0X00000200 + +#define IPI_RPU_0_ISR_RPU_0_SHIFT 8 +#define IPI_RPU_0_ISR_RPU_0_WIDTH 1 +#define IPI_RPU_0_ISR_RPU_0_MASK 0X00000100 + +#define IPI_RPU_0_ISR_APU_SHIFT 0 +#define IPI_RPU_0_ISR_APU_WIDTH 1 +#define IPI_RPU_0_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_0_IMR + */ +#define IPI_RPU_0_IMR ( ( IPI_BASEADDR ) + 0X00010014 ) + +#define IPI_RPU_0_IMR_PL_3_SHIFT 27 +#define IPI_RPU_0_IMR_PL_3_WIDTH 1 +#define IPI_RPU_0_IMR_PL_3_MASK 0X08000000 + +#define IPI_RPU_0_IMR_PL_2_SHIFT 26 +#define IPI_RPU_0_IMR_PL_2_WIDTH 1 +#define IPI_RPU_0_IMR_PL_2_MASK 0X04000000 + +#define IPI_RPU_0_IMR_PL_1_SHIFT 25 +#define IPI_RPU_0_IMR_PL_1_WIDTH 1 +#define IPI_RPU_0_IMR_PL_1_MASK 0X02000000 + +#define IPI_RPU_0_IMR_PL_0_SHIFT 24 +#define IPI_RPU_0_IMR_PL_0_WIDTH 1 +#define IPI_RPU_0_IMR_PL_0_MASK 0X01000000 + +#define IPI_RPU_0_IMR_PMU_3_SHIFT 19 +#define IPI_RPU_0_IMR_PMU_3_WIDTH 1 +#define IPI_RPU_0_IMR_PMU_3_MASK 0X00080000 + +#define IPI_RPU_0_IMR_PMU_2_SHIFT 18 +#define IPI_RPU_0_IMR_PMU_2_WIDTH 1 +#define IPI_RPU_0_IMR_PMU_2_MASK 0X00040000 + +#define IPI_RPU_0_IMR_PMU_1_SHIFT 17 +#define IPI_RPU_0_IMR_PMU_1_WIDTH 1 +#define IPI_RPU_0_IMR_PMU_1_MASK 0X00020000 + +#define IPI_RPU_0_IMR_PMU_0_SHIFT 16 +#define IPI_RPU_0_IMR_PMU_0_WIDTH 1 +#define IPI_RPU_0_IMR_PMU_0_MASK 0X00010000 + +#define IPI_RPU_0_IMR_RPU_1_SHIFT 9 +#define IPI_RPU_0_IMR_RPU_1_WIDTH 1 +#define IPI_RPU_0_IMR_RPU_1_MASK 0X00000200 + +#define IPI_RPU_0_IMR_RPU_0_SHIFT 8 +#define IPI_RPU_0_IMR_RPU_0_WIDTH 1 +#define IPI_RPU_0_IMR_RPU_0_MASK 0X00000100 + +#define IPI_RPU_0_IMR_APU_SHIFT 0 +#define IPI_RPU_0_IMR_APU_WIDTH 1 +#define IPI_RPU_0_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_0_IER + */ +#define IPI_RPU_0_IER ( ( IPI_BASEADDR ) + 0X00010018 ) + +#define IPI_RPU_0_IER_PL_3_SHIFT 27 +#define IPI_RPU_0_IER_PL_3_WIDTH 1 +#define IPI_RPU_0_IER_PL_3_MASK 0X08000000 + +#define IPI_RPU_0_IER_PL_2_SHIFT 26 +#define IPI_RPU_0_IER_PL_2_WIDTH 1 +#define IPI_RPU_0_IER_PL_2_MASK 0X04000000 + +#define IPI_RPU_0_IER_PL_1_SHIFT 25 +#define IPI_RPU_0_IER_PL_1_WIDTH 1 +#define IPI_RPU_0_IER_PL_1_MASK 0X02000000 + +#define IPI_RPU_0_IER_PL_0_SHIFT 24 +#define IPI_RPU_0_IER_PL_0_WIDTH 1 +#define IPI_RPU_0_IER_PL_0_MASK 0X01000000 + +#define IPI_RPU_0_IER_PMU_3_SHIFT 19 +#define IPI_RPU_0_IER_PMU_3_WIDTH 1 +#define IPI_RPU_0_IER_PMU_3_MASK 0X00080000 + +#define IPI_RPU_0_IER_PMU_2_SHIFT 18 +#define IPI_RPU_0_IER_PMU_2_WIDTH 1 +#define IPI_RPU_0_IER_PMU_2_MASK 0X00040000 + +#define IPI_RPU_0_IER_PMU_1_SHIFT 17 +#define IPI_RPU_0_IER_PMU_1_WIDTH 1 +#define IPI_RPU_0_IER_PMU_1_MASK 0X00020000 + +#define IPI_RPU_0_IER_PMU_0_SHIFT 16 +#define IPI_RPU_0_IER_PMU_0_WIDTH 1 +#define IPI_RPU_0_IER_PMU_0_MASK 0X00010000 + +#define IPI_RPU_0_IER_RPU_1_SHIFT 9 +#define IPI_RPU_0_IER_RPU_1_WIDTH 1 +#define IPI_RPU_0_IER_RPU_1_MASK 0X00000200 + +#define IPI_RPU_0_IER_RPU_0_SHIFT 8 +#define IPI_RPU_0_IER_RPU_0_WIDTH 1 +#define IPI_RPU_0_IER_RPU_0_MASK 0X00000100 + +#define IPI_RPU_0_IER_APU_SHIFT 0 +#define IPI_RPU_0_IER_APU_WIDTH 1 +#define IPI_RPU_0_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_0_IDR + */ +#define IPI_RPU_0_IDR ( ( IPI_BASEADDR ) + 0X0001001C ) + +#define IPI_RPU_0_IDR_PL_3_SHIFT 27 +#define IPI_RPU_0_IDR_PL_3_WIDTH 1 +#define IPI_RPU_0_IDR_PL_3_MASK 0X08000000 + +#define IPI_RPU_0_IDR_PL_2_SHIFT 26 +#define IPI_RPU_0_IDR_PL_2_WIDTH 1 +#define IPI_RPU_0_IDR_PL_2_MASK 0X04000000 + +#define IPI_RPU_0_IDR_PL_1_SHIFT 25 +#define IPI_RPU_0_IDR_PL_1_WIDTH 1 +#define IPI_RPU_0_IDR_PL_1_MASK 0X02000000 + +#define IPI_RPU_0_IDR_PL_0_SHIFT 24 +#define IPI_RPU_0_IDR_PL_0_WIDTH 1 +#define IPI_RPU_0_IDR_PL_0_MASK 0X01000000 + +#define IPI_RPU_0_IDR_PMU_3_SHIFT 19 +#define IPI_RPU_0_IDR_PMU_3_WIDTH 1 +#define IPI_RPU_0_IDR_PMU_3_MASK 0X00080000 + +#define IPI_RPU_0_IDR_PMU_2_SHIFT 18 +#define IPI_RPU_0_IDR_PMU_2_WIDTH 1 +#define IPI_RPU_0_IDR_PMU_2_MASK 0X00040000 + +#define IPI_RPU_0_IDR_PMU_1_SHIFT 17 +#define IPI_RPU_0_IDR_PMU_1_WIDTH 1 +#define IPI_RPU_0_IDR_PMU_1_MASK 0X00020000 + +#define IPI_RPU_0_IDR_PMU_0_SHIFT 16 +#define IPI_RPU_0_IDR_PMU_0_WIDTH 1 +#define IPI_RPU_0_IDR_PMU_0_MASK 0X00010000 + +#define IPI_RPU_0_IDR_RPU_1_SHIFT 9 +#define IPI_RPU_0_IDR_RPU_1_WIDTH 1 +#define IPI_RPU_0_IDR_RPU_1_MASK 0X00000200 + +#define IPI_RPU_0_IDR_RPU_0_SHIFT 8 +#define IPI_RPU_0_IDR_RPU_0_WIDTH 1 +#define IPI_RPU_0_IDR_RPU_0_MASK 0X00000100 + +#define IPI_RPU_0_IDR_APU_SHIFT 0 +#define IPI_RPU_0_IDR_APU_WIDTH 1 +#define IPI_RPU_0_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_1_TRIG + */ +#define IPI_RPU_1_TRIG ( ( IPI_BASEADDR ) + 0X00020000 ) + +#define IPI_RPU_1_TRIG_PL_3_SHIFT 27 +#define IPI_RPU_1_TRIG_PL_3_WIDTH 1 +#define IPI_RPU_1_TRIG_PL_3_MASK 0X08000000 + +#define IPI_RPU_1_TRIG_PL_2_SHIFT 26 +#define IPI_RPU_1_TRIG_PL_2_WIDTH 1 +#define IPI_RPU_1_TRIG_PL_2_MASK 0X04000000 + +#define IPI_RPU_1_TRIG_PL_1_SHIFT 25 +#define IPI_RPU_1_TRIG_PL_1_WIDTH 1 +#define IPI_RPU_1_TRIG_PL_1_MASK 0X02000000 + +#define IPI_RPU_1_TRIG_PL_0_SHIFT 24 +#define IPI_RPU_1_TRIG_PL_0_WIDTH 1 +#define IPI_RPU_1_TRIG_PL_0_MASK 0X01000000 + +#define IPI_RPU_1_TRIG_PMU_3_SHIFT 19 +#define IPI_RPU_1_TRIG_PMU_3_WIDTH 1 +#define IPI_RPU_1_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_RPU_1_TRIG_PMU_2_SHIFT 18 +#define IPI_RPU_1_TRIG_PMU_2_WIDTH 1 +#define IPI_RPU_1_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_RPU_1_TRIG_PMU_1_SHIFT 17 +#define IPI_RPU_1_TRIG_PMU_1_WIDTH 1 +#define IPI_RPU_1_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_RPU_1_TRIG_PMU_0_SHIFT 16 +#define IPI_RPU_1_TRIG_PMU_0_WIDTH 1 +#define IPI_RPU_1_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_RPU_1_TRIG_RPU_1_SHIFT 9 +#define IPI_RPU_1_TRIG_RPU_1_WIDTH 1 +#define IPI_RPU_1_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_RPU_1_TRIG_RPU_0_SHIFT 8 +#define IPI_RPU_1_TRIG_RPU_0_WIDTH 1 +#define IPI_RPU_1_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_RPU_1_TRIG_APU_SHIFT 0 +#define IPI_RPU_1_TRIG_APU_WIDTH 1 +#define IPI_RPU_1_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_1_OBS + */ +#define IPI_RPU_1_OBS ( ( IPI_BASEADDR ) + 0X00020004 ) + +#define IPI_RPU_1_OBS_PL_3_SHIFT 27 +#define IPI_RPU_1_OBS_PL_3_WIDTH 1 +#define IPI_RPU_1_OBS_PL_3_MASK 0X08000000 + +#define IPI_RPU_1_OBS_PL_2_SHIFT 26 +#define IPI_RPU_1_OBS_PL_2_WIDTH 1 +#define IPI_RPU_1_OBS_PL_2_MASK 0X04000000 + +#define IPI_RPU_1_OBS_PL_1_SHIFT 25 +#define IPI_RPU_1_OBS_PL_1_WIDTH 1 +#define IPI_RPU_1_OBS_PL_1_MASK 0X02000000 + +#define IPI_RPU_1_OBS_PL_0_SHIFT 24 +#define IPI_RPU_1_OBS_PL_0_WIDTH 1 +#define IPI_RPU_1_OBS_PL_0_MASK 0X01000000 + +#define IPI_RPU_1_OBS_PMU_3_SHIFT 19 +#define IPI_RPU_1_OBS_PMU_3_WIDTH 1 +#define IPI_RPU_1_OBS_PMU_3_MASK 0X00080000 + +#define IPI_RPU_1_OBS_PMU_2_SHIFT 18 +#define IPI_RPU_1_OBS_PMU_2_WIDTH 1 +#define IPI_RPU_1_OBS_PMU_2_MASK 0X00040000 + +#define IPI_RPU_1_OBS_PMU_1_SHIFT 17 +#define IPI_RPU_1_OBS_PMU_1_WIDTH 1 +#define IPI_RPU_1_OBS_PMU_1_MASK 0X00020000 + +#define IPI_RPU_1_OBS_PMU_0_SHIFT 16 +#define IPI_RPU_1_OBS_PMU_0_WIDTH 1 +#define IPI_RPU_1_OBS_PMU_0_MASK 0X00010000 + +#define IPI_RPU_1_OBS_RPU_1_SHIFT 9 +#define IPI_RPU_1_OBS_RPU_1_WIDTH 1 +#define IPI_RPU_1_OBS_RPU_1_MASK 0X00000200 + +#define IPI_RPU_1_OBS_RPU_0_SHIFT 8 +#define IPI_RPU_1_OBS_RPU_0_WIDTH 1 +#define IPI_RPU_1_OBS_RPU_0_MASK 0X00000100 + +#define IPI_RPU_1_OBS_APU_SHIFT 0 +#define IPI_RPU_1_OBS_APU_WIDTH 1 +#define IPI_RPU_1_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_1_ISR + */ +#define IPI_RPU_1_ISR ( ( IPI_BASEADDR ) + 0X00020010 ) + +#define IPI_RPU_1_ISR_PL_3_SHIFT 27 +#define IPI_RPU_1_ISR_PL_3_WIDTH 1 +#define IPI_RPU_1_ISR_PL_3_MASK 0X08000000 + +#define IPI_RPU_1_ISR_PL_2_SHIFT 26 +#define IPI_RPU_1_ISR_PL_2_WIDTH 1 +#define IPI_RPU_1_ISR_PL_2_MASK 0X04000000 + +#define IPI_RPU_1_ISR_PL_1_SHIFT 25 +#define IPI_RPU_1_ISR_PL_1_WIDTH 1 +#define IPI_RPU_1_ISR_PL_1_MASK 0X02000000 + +#define IPI_RPU_1_ISR_PL_0_SHIFT 24 +#define IPI_RPU_1_ISR_PL_0_WIDTH 1 +#define IPI_RPU_1_ISR_PL_0_MASK 0X01000000 + +#define IPI_RPU_1_ISR_PMU_3_SHIFT 19 +#define IPI_RPU_1_ISR_PMU_3_WIDTH 1 +#define IPI_RPU_1_ISR_PMU_3_MASK 0X00080000 + +#define IPI_RPU_1_ISR_PMU_2_SHIFT 18 +#define IPI_RPU_1_ISR_PMU_2_WIDTH 1 +#define IPI_RPU_1_ISR_PMU_2_MASK 0X00040000 + +#define IPI_RPU_1_ISR_PMU_1_SHIFT 17 +#define IPI_RPU_1_ISR_PMU_1_WIDTH 1 +#define IPI_RPU_1_ISR_PMU_1_MASK 0X00020000 + +#define IPI_RPU_1_ISR_PMU_0_SHIFT 16 +#define IPI_RPU_1_ISR_PMU_0_WIDTH 1 +#define IPI_RPU_1_ISR_PMU_0_MASK 0X00010000 + +#define IPI_RPU_1_ISR_RPU_1_SHIFT 9 +#define IPI_RPU_1_ISR_RPU_1_WIDTH 1 +#define IPI_RPU_1_ISR_RPU_1_MASK 0X00000200 + +#define IPI_RPU_1_ISR_RPU_0_SHIFT 8 +#define IPI_RPU_1_ISR_RPU_0_WIDTH 1 +#define IPI_RPU_1_ISR_RPU_0_MASK 0X00000100 + +#define IPI_RPU_1_ISR_APU_SHIFT 0 +#define IPI_RPU_1_ISR_APU_WIDTH 1 +#define IPI_RPU_1_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_1_IMR + */ +#define IPI_RPU_1_IMR ( ( IPI_BASEADDR ) + 0X00020014 ) + +#define IPI_RPU_1_IMR_PL_3_SHIFT 27 +#define IPI_RPU_1_IMR_PL_3_WIDTH 1 +#define IPI_RPU_1_IMR_PL_3_MASK 0X08000000 + +#define IPI_RPU_1_IMR_PL_2_SHIFT 26 +#define IPI_RPU_1_IMR_PL_2_WIDTH 1 +#define IPI_RPU_1_IMR_PL_2_MASK 0X04000000 + +#define IPI_RPU_1_IMR_PL_1_SHIFT 25 +#define IPI_RPU_1_IMR_PL_1_WIDTH 1 +#define IPI_RPU_1_IMR_PL_1_MASK 0X02000000 + +#define IPI_RPU_1_IMR_PL_0_SHIFT 24 +#define IPI_RPU_1_IMR_PL_0_WIDTH 1 +#define IPI_RPU_1_IMR_PL_0_MASK 0X01000000 + +#define IPI_RPU_1_IMR_PMU_3_SHIFT 19 +#define IPI_RPU_1_IMR_PMU_3_WIDTH 1 +#define IPI_RPU_1_IMR_PMU_3_MASK 0X00080000 + +#define IPI_RPU_1_IMR_PMU_2_SHIFT 18 +#define IPI_RPU_1_IMR_PMU_2_WIDTH 1 +#define IPI_RPU_1_IMR_PMU_2_MASK 0X00040000 + +#define IPI_RPU_1_IMR_PMU_1_SHIFT 17 +#define IPI_RPU_1_IMR_PMU_1_WIDTH 1 +#define IPI_RPU_1_IMR_PMU_1_MASK 0X00020000 + +#define IPI_RPU_1_IMR_PMU_0_SHIFT 16 +#define IPI_RPU_1_IMR_PMU_0_WIDTH 1 +#define IPI_RPU_1_IMR_PMU_0_MASK 0X00010000 + +#define IPI_RPU_1_IMR_RPU_1_SHIFT 9 +#define IPI_RPU_1_IMR_RPU_1_WIDTH 1 +#define IPI_RPU_1_IMR_RPU_1_MASK 0X00000200 + +#define IPI_RPU_1_IMR_RPU_0_SHIFT 8 +#define IPI_RPU_1_IMR_RPU_0_WIDTH 1 +#define IPI_RPU_1_IMR_RPU_0_MASK 0X00000100 + +#define IPI_RPU_1_IMR_APU_SHIFT 0 +#define IPI_RPU_1_IMR_APU_WIDTH 1 +#define IPI_RPU_1_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_1_IER + */ +#define IPI_RPU_1_IER ( ( IPI_BASEADDR ) + 0X00020018 ) + +#define IPI_RPU_1_IER_PL_3_SHIFT 27 +#define IPI_RPU_1_IER_PL_3_WIDTH 1 +#define IPI_RPU_1_IER_PL_3_MASK 0X08000000 + +#define IPI_RPU_1_IER_PL_2_SHIFT 26 +#define IPI_RPU_1_IER_PL_2_WIDTH 1 +#define IPI_RPU_1_IER_PL_2_MASK 0X04000000 + +#define IPI_RPU_1_IER_PL_1_SHIFT 25 +#define IPI_RPU_1_IER_PL_1_WIDTH 1 +#define IPI_RPU_1_IER_PL_1_MASK 0X02000000 + +#define IPI_RPU_1_IER_PL_0_SHIFT 24 +#define IPI_RPU_1_IER_PL_0_WIDTH 1 +#define IPI_RPU_1_IER_PL_0_MASK 0X01000000 + +#define IPI_RPU_1_IER_PMU_3_SHIFT 19 +#define IPI_RPU_1_IER_PMU_3_WIDTH 1 +#define IPI_RPU_1_IER_PMU_3_MASK 0X00080000 + +#define IPI_RPU_1_IER_PMU_2_SHIFT 18 +#define IPI_RPU_1_IER_PMU_2_WIDTH 1 +#define IPI_RPU_1_IER_PMU_2_MASK 0X00040000 + +#define IPI_RPU_1_IER_PMU_1_SHIFT 17 +#define IPI_RPU_1_IER_PMU_1_WIDTH 1 +#define IPI_RPU_1_IER_PMU_1_MASK 0X00020000 + +#define IPI_RPU_1_IER_PMU_0_SHIFT 16 +#define IPI_RPU_1_IER_PMU_0_WIDTH 1 +#define IPI_RPU_1_IER_PMU_0_MASK 0X00010000 + +#define IPI_RPU_1_IER_RPU_1_SHIFT 9 +#define IPI_RPU_1_IER_RPU_1_WIDTH 1 +#define IPI_RPU_1_IER_RPU_1_MASK 0X00000200 + +#define IPI_RPU_1_IER_RPU_0_SHIFT 8 +#define IPI_RPU_1_IER_RPU_0_WIDTH 1 +#define IPI_RPU_1_IER_RPU_0_MASK 0X00000100 + +#define IPI_RPU_1_IER_APU_SHIFT 0 +#define IPI_RPU_1_IER_APU_WIDTH 1 +#define IPI_RPU_1_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_RPU_1_IDR + */ +#define IPI_RPU_1_IDR ( ( IPI_BASEADDR ) + 0X0002001C ) + +#define IPI_RPU_1_IDR_PL_3_SHIFT 27 +#define IPI_RPU_1_IDR_PL_3_WIDTH 1 +#define IPI_RPU_1_IDR_PL_3_MASK 0X08000000 + +#define IPI_RPU_1_IDR_PL_2_SHIFT 26 +#define IPI_RPU_1_IDR_PL_2_WIDTH 1 +#define IPI_RPU_1_IDR_PL_2_MASK 0X04000000 + +#define IPI_RPU_1_IDR_PL_1_SHIFT 25 +#define IPI_RPU_1_IDR_PL_1_WIDTH 1 +#define IPI_RPU_1_IDR_PL_1_MASK 0X02000000 + +#define IPI_RPU_1_IDR_PL_0_SHIFT 24 +#define IPI_RPU_1_IDR_PL_0_WIDTH 1 +#define IPI_RPU_1_IDR_PL_0_MASK 0X01000000 + +#define IPI_RPU_1_IDR_PMU_3_SHIFT 19 +#define IPI_RPU_1_IDR_PMU_3_WIDTH 1 +#define IPI_RPU_1_IDR_PMU_3_MASK 0X00080000 + +#define IPI_RPU_1_IDR_PMU_2_SHIFT 18 +#define IPI_RPU_1_IDR_PMU_2_WIDTH 1 +#define IPI_RPU_1_IDR_PMU_2_MASK 0X00040000 + +#define IPI_RPU_1_IDR_PMU_1_SHIFT 17 +#define IPI_RPU_1_IDR_PMU_1_WIDTH 1 +#define IPI_RPU_1_IDR_PMU_1_MASK 0X00020000 + +#define IPI_RPU_1_IDR_PMU_0_SHIFT 16 +#define IPI_RPU_1_IDR_PMU_0_WIDTH 1 +#define IPI_RPU_1_IDR_PMU_0_MASK 0X00010000 + +#define IPI_RPU_1_IDR_RPU_1_SHIFT 9 +#define IPI_RPU_1_IDR_RPU_1_WIDTH 1 +#define IPI_RPU_1_IDR_RPU_1_MASK 0X00000200 + +#define IPI_RPU_1_IDR_RPU_0_SHIFT 8 +#define IPI_RPU_1_IDR_RPU_0_WIDTH 1 +#define IPI_RPU_1_IDR_RPU_0_MASK 0X00000100 + +#define IPI_RPU_1_IDR_APU_SHIFT 0 +#define IPI_RPU_1_IDR_APU_WIDTH 1 +#define IPI_RPU_1_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_0_TRIG + */ +#define IPI_PMU_0_TRIG ( ( IPI_BASEADDR ) + 0X00030000 ) + +#define IPI_PMU_0_TRIG_PL_3_SHIFT 27 +#define IPI_PMU_0_TRIG_PL_3_WIDTH 1 +#define IPI_PMU_0_TRIG_PL_3_MASK 0X08000000 + +#define IPI_PMU_0_TRIG_PL_2_SHIFT 26 +#define IPI_PMU_0_TRIG_PL_2_WIDTH 1 +#define IPI_PMU_0_TRIG_PL_2_MASK 0X04000000 + +#define IPI_PMU_0_TRIG_PL_1_SHIFT 25 +#define IPI_PMU_0_TRIG_PL_1_WIDTH 1 +#define IPI_PMU_0_TRIG_PL_1_MASK 0X02000000 + +#define IPI_PMU_0_TRIG_PL_0_SHIFT 24 +#define IPI_PMU_0_TRIG_PL_0_WIDTH 1 +#define IPI_PMU_0_TRIG_PL_0_MASK 0X01000000 + +#define IPI_PMU_0_TRIG_PMU_3_SHIFT 19 +#define IPI_PMU_0_TRIG_PMU_3_WIDTH 1 +#define IPI_PMU_0_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_PMU_0_TRIG_PMU_2_SHIFT 18 +#define IPI_PMU_0_TRIG_PMU_2_WIDTH 1 +#define IPI_PMU_0_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_PMU_0_TRIG_PMU_1_SHIFT 17 +#define IPI_PMU_0_TRIG_PMU_1_WIDTH 1 +#define IPI_PMU_0_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_PMU_0_TRIG_PMU_0_SHIFT 16 +#define IPI_PMU_0_TRIG_PMU_0_WIDTH 1 +#define IPI_PMU_0_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_PMU_0_TRIG_RPU_1_SHIFT 9 +#define IPI_PMU_0_TRIG_RPU_1_WIDTH 1 +#define IPI_PMU_0_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_PMU_0_TRIG_RPU_0_SHIFT 8 +#define IPI_PMU_0_TRIG_RPU_0_WIDTH 1 +#define IPI_PMU_0_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_PMU_0_TRIG_APU_SHIFT 0 +#define IPI_PMU_0_TRIG_APU_WIDTH 1 +#define IPI_PMU_0_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_0_OBS + */ +#define IPI_PMU_0_OBS ( ( IPI_BASEADDR ) + 0X00030004 ) + +#define IPI_PMU_0_OBS_PL_3_SHIFT 27 +#define IPI_PMU_0_OBS_PL_3_WIDTH 1 +#define IPI_PMU_0_OBS_PL_3_MASK 0X08000000 + +#define IPI_PMU_0_OBS_PL_2_SHIFT 26 +#define IPI_PMU_0_OBS_PL_2_WIDTH 1 +#define IPI_PMU_0_OBS_PL_2_MASK 0X04000000 + +#define IPI_PMU_0_OBS_PL_1_SHIFT 25 +#define IPI_PMU_0_OBS_PL_1_WIDTH 1 +#define IPI_PMU_0_OBS_PL_1_MASK 0X02000000 + +#define IPI_PMU_0_OBS_PL_0_SHIFT 24 +#define IPI_PMU_0_OBS_PL_0_WIDTH 1 +#define IPI_PMU_0_OBS_PL_0_MASK 0X01000000 + +#define IPI_PMU_0_OBS_PMU_3_SHIFT 19 +#define IPI_PMU_0_OBS_PMU_3_WIDTH 1 +#define IPI_PMU_0_OBS_PMU_3_MASK 0X00080000 + +#define IPI_PMU_0_OBS_PMU_2_SHIFT 18 +#define IPI_PMU_0_OBS_PMU_2_WIDTH 1 +#define IPI_PMU_0_OBS_PMU_2_MASK 0X00040000 + +#define IPI_PMU_0_OBS_PMU_1_SHIFT 17 +#define IPI_PMU_0_OBS_PMU_1_WIDTH 1 +#define IPI_PMU_0_OBS_PMU_1_MASK 0X00020000 + +#define IPI_PMU_0_OBS_PMU_0_SHIFT 16 +#define IPI_PMU_0_OBS_PMU_0_WIDTH 1 +#define IPI_PMU_0_OBS_PMU_0_MASK 0X00010000 + +#define IPI_PMU_0_OBS_RPU_1_SHIFT 9 +#define IPI_PMU_0_OBS_RPU_1_WIDTH 1 +#define IPI_PMU_0_OBS_RPU_1_MASK 0X00000200 + +#define IPI_PMU_0_OBS_RPU_0_SHIFT 8 +#define IPI_PMU_0_OBS_RPU_0_WIDTH 1 +#define IPI_PMU_0_OBS_RPU_0_MASK 0X00000100 + +#define IPI_PMU_0_OBS_APU_SHIFT 0 +#define IPI_PMU_0_OBS_APU_WIDTH 1 +#define IPI_PMU_0_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_0_ISR + */ +#define IPI_PMU_0_ISR ( ( IPI_BASEADDR ) + 0X00030010 ) + +#define IPI_PMU_0_ISR_PL_3_SHIFT 27 +#define IPI_PMU_0_ISR_PL_3_WIDTH 1 +#define IPI_PMU_0_ISR_PL_3_MASK 0X08000000 + +#define IPI_PMU_0_ISR_PL_2_SHIFT 26 +#define IPI_PMU_0_ISR_PL_2_WIDTH 1 +#define IPI_PMU_0_ISR_PL_2_MASK 0X04000000 + +#define IPI_PMU_0_ISR_PL_1_SHIFT 25 +#define IPI_PMU_0_ISR_PL_1_WIDTH 1 +#define IPI_PMU_0_ISR_PL_1_MASK 0X02000000 + +#define IPI_PMU_0_ISR_PL_0_SHIFT 24 +#define IPI_PMU_0_ISR_PL_0_WIDTH 1 +#define IPI_PMU_0_ISR_PL_0_MASK 0X01000000 + +#define IPI_PMU_0_ISR_PMU_3_SHIFT 19 +#define IPI_PMU_0_ISR_PMU_3_WIDTH 1 +#define IPI_PMU_0_ISR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_0_ISR_PMU_2_SHIFT 18 +#define IPI_PMU_0_ISR_PMU_2_WIDTH 1 +#define IPI_PMU_0_ISR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_0_ISR_PMU_1_SHIFT 17 +#define IPI_PMU_0_ISR_PMU_1_WIDTH 1 +#define IPI_PMU_0_ISR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_0_ISR_PMU_0_SHIFT 16 +#define IPI_PMU_0_ISR_PMU_0_WIDTH 1 +#define IPI_PMU_0_ISR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_0_ISR_RPU_1_SHIFT 9 +#define IPI_PMU_0_ISR_RPU_1_WIDTH 1 +#define IPI_PMU_0_ISR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_0_ISR_RPU_0_SHIFT 8 +#define IPI_PMU_0_ISR_RPU_0_WIDTH 1 +#define IPI_PMU_0_ISR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_0_ISR_APU_SHIFT 0 +#define IPI_PMU_0_ISR_APU_WIDTH 1 +#define IPI_PMU_0_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_0_IMR + */ +#define IPI_PMU_0_IMR ( ( IPI_BASEADDR ) + 0X00030014 ) + +#define IPI_PMU_0_IMR_PL_3_SHIFT 27 +#define IPI_PMU_0_IMR_PL_3_WIDTH 1 +#define IPI_PMU_0_IMR_PL_3_MASK 0X08000000 + +#define IPI_PMU_0_IMR_PL_2_SHIFT 26 +#define IPI_PMU_0_IMR_PL_2_WIDTH 1 +#define IPI_PMU_0_IMR_PL_2_MASK 0X04000000 + +#define IPI_PMU_0_IMR_PL_1_SHIFT 25 +#define IPI_PMU_0_IMR_PL_1_WIDTH 1 +#define IPI_PMU_0_IMR_PL_1_MASK 0X02000000 + +#define IPI_PMU_0_IMR_PL_0_SHIFT 24 +#define IPI_PMU_0_IMR_PL_0_WIDTH 1 +#define IPI_PMU_0_IMR_PL_0_MASK 0X01000000 + +#define IPI_PMU_0_IMR_PMU_3_SHIFT 19 +#define IPI_PMU_0_IMR_PMU_3_WIDTH 1 +#define IPI_PMU_0_IMR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_0_IMR_PMU_2_SHIFT 18 +#define IPI_PMU_0_IMR_PMU_2_WIDTH 1 +#define IPI_PMU_0_IMR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_0_IMR_PMU_1_SHIFT 17 +#define IPI_PMU_0_IMR_PMU_1_WIDTH 1 +#define IPI_PMU_0_IMR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_0_IMR_PMU_0_SHIFT 16 +#define IPI_PMU_0_IMR_PMU_0_WIDTH 1 +#define IPI_PMU_0_IMR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_0_IMR_RPU_1_SHIFT 9 +#define IPI_PMU_0_IMR_RPU_1_WIDTH 1 +#define IPI_PMU_0_IMR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_0_IMR_RPU_0_SHIFT 8 +#define IPI_PMU_0_IMR_RPU_0_WIDTH 1 +#define IPI_PMU_0_IMR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_0_IMR_APU_SHIFT 0 +#define IPI_PMU_0_IMR_APU_WIDTH 1 +#define IPI_PMU_0_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_0_IER + */ +#define IPI_PMU_0_IER ( ( IPI_BASEADDR ) + 0X00030018 ) + +#define IPI_PMU_0_IER_PL_3_SHIFT 27 +#define IPI_PMU_0_IER_PL_3_WIDTH 1 +#define IPI_PMU_0_IER_PL_3_MASK 0X08000000 + +#define IPI_PMU_0_IER_PL_2_SHIFT 26 +#define IPI_PMU_0_IER_PL_2_WIDTH 1 +#define IPI_PMU_0_IER_PL_2_MASK 0X04000000 + +#define IPI_PMU_0_IER_PL_1_SHIFT 25 +#define IPI_PMU_0_IER_PL_1_WIDTH 1 +#define IPI_PMU_0_IER_PL_1_MASK 0X02000000 + +#define IPI_PMU_0_IER_PL_0_SHIFT 24 +#define IPI_PMU_0_IER_PL_0_WIDTH 1 +#define IPI_PMU_0_IER_PL_0_MASK 0X01000000 + +#define IPI_PMU_0_IER_PMU_3_SHIFT 19 +#define IPI_PMU_0_IER_PMU_3_WIDTH 1 +#define IPI_PMU_0_IER_PMU_3_MASK 0X00080000 + +#define IPI_PMU_0_IER_PMU_2_SHIFT 18 +#define IPI_PMU_0_IER_PMU_2_WIDTH 1 +#define IPI_PMU_0_IER_PMU_2_MASK 0X00040000 + +#define IPI_PMU_0_IER_PMU_1_SHIFT 17 +#define IPI_PMU_0_IER_PMU_1_WIDTH 1 +#define IPI_PMU_0_IER_PMU_1_MASK 0X00020000 + +#define IPI_PMU_0_IER_PMU_0_SHIFT 16 +#define IPI_PMU_0_IER_PMU_0_WIDTH 1 +#define IPI_PMU_0_IER_PMU_0_MASK 0X00010000 + +#define IPI_PMU_0_IER_RPU_1_SHIFT 9 +#define IPI_PMU_0_IER_RPU_1_WIDTH 1 +#define IPI_PMU_0_IER_RPU_1_MASK 0X00000200 + +#define IPI_PMU_0_IER_RPU_0_SHIFT 8 +#define IPI_PMU_0_IER_RPU_0_WIDTH 1 +#define IPI_PMU_0_IER_RPU_0_MASK 0X00000100 + +#define IPI_PMU_0_IER_APU_SHIFT 0 +#define IPI_PMU_0_IER_APU_WIDTH 1 +#define IPI_PMU_0_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_0_IDR + */ +#define IPI_PMU_0_IDR ( ( IPI_BASEADDR ) + 0X0003001C ) + +#define IPI_PMU_0_IDR_PL_3_SHIFT 27 +#define IPI_PMU_0_IDR_PL_3_WIDTH 1 +#define IPI_PMU_0_IDR_PL_3_MASK 0X08000000 + +#define IPI_PMU_0_IDR_PL_2_SHIFT 26 +#define IPI_PMU_0_IDR_PL_2_WIDTH 1 +#define IPI_PMU_0_IDR_PL_2_MASK 0X04000000 + +#define IPI_PMU_0_IDR_PL_1_SHIFT 25 +#define IPI_PMU_0_IDR_PL_1_WIDTH 1 +#define IPI_PMU_0_IDR_PL_1_MASK 0X02000000 + +#define IPI_PMU_0_IDR_PL_0_SHIFT 24 +#define IPI_PMU_0_IDR_PL_0_WIDTH 1 +#define IPI_PMU_0_IDR_PL_0_MASK 0X01000000 + +#define IPI_PMU_0_IDR_PMU_3_SHIFT 19 +#define IPI_PMU_0_IDR_PMU_3_WIDTH 1 +#define IPI_PMU_0_IDR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_0_IDR_PMU_2_SHIFT 18 +#define IPI_PMU_0_IDR_PMU_2_WIDTH 1 +#define IPI_PMU_0_IDR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_0_IDR_PMU_1_SHIFT 17 +#define IPI_PMU_0_IDR_PMU_1_WIDTH 1 +#define IPI_PMU_0_IDR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_0_IDR_PMU_0_SHIFT 16 +#define IPI_PMU_0_IDR_PMU_0_WIDTH 1 +#define IPI_PMU_0_IDR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_0_IDR_RPU_1_SHIFT 9 +#define IPI_PMU_0_IDR_RPU_1_WIDTH 1 +#define IPI_PMU_0_IDR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_0_IDR_RPU_0_SHIFT 8 +#define IPI_PMU_0_IDR_RPU_0_WIDTH 1 +#define IPI_PMU_0_IDR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_0_IDR_APU_SHIFT 0 +#define IPI_PMU_0_IDR_APU_WIDTH 1 +#define IPI_PMU_0_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_1_TRIG + */ +#define IPI_PMU_1_TRIG ( ( IPI_BASEADDR ) + 0X00031000 ) + +#define IPI_PMU_1_TRIG_PL_3_SHIFT 27 +#define IPI_PMU_1_TRIG_PL_3_WIDTH 1 +#define IPI_PMU_1_TRIG_PL_3_MASK 0X08000000 + +#define IPI_PMU_1_TRIG_PL_2_SHIFT 26 +#define IPI_PMU_1_TRIG_PL_2_WIDTH 1 +#define IPI_PMU_1_TRIG_PL_2_MASK 0X04000000 + +#define IPI_PMU_1_TRIG_PL_1_SHIFT 25 +#define IPI_PMU_1_TRIG_PL_1_WIDTH 1 +#define IPI_PMU_1_TRIG_PL_1_MASK 0X02000000 + +#define IPI_PMU_1_TRIG_PL_0_SHIFT 24 +#define IPI_PMU_1_TRIG_PL_0_WIDTH 1 +#define IPI_PMU_1_TRIG_PL_0_MASK 0X01000000 + +#define IPI_PMU_1_TRIG_PMU_3_SHIFT 19 +#define IPI_PMU_1_TRIG_PMU_3_WIDTH 1 +#define IPI_PMU_1_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_PMU_1_TRIG_PMU_2_SHIFT 18 +#define IPI_PMU_1_TRIG_PMU_2_WIDTH 1 +#define IPI_PMU_1_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_PMU_1_TRIG_PMU_1_SHIFT 17 +#define IPI_PMU_1_TRIG_PMU_1_WIDTH 1 +#define IPI_PMU_1_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_PMU_1_TRIG_PMU_0_SHIFT 16 +#define IPI_PMU_1_TRIG_PMU_0_WIDTH 1 +#define IPI_PMU_1_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_PMU_1_TRIG_RPU_1_SHIFT 9 +#define IPI_PMU_1_TRIG_RPU_1_WIDTH 1 +#define IPI_PMU_1_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_PMU_1_TRIG_RPU_0_SHIFT 8 +#define IPI_PMU_1_TRIG_RPU_0_WIDTH 1 +#define IPI_PMU_1_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_PMU_1_TRIG_APU_SHIFT 0 +#define IPI_PMU_1_TRIG_APU_WIDTH 1 +#define IPI_PMU_1_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_1_OBS + */ +#define IPI_PMU_1_OBS ( ( IPI_BASEADDR ) + 0X00031004 ) + +#define IPI_PMU_1_OBS_PL_3_SHIFT 27 +#define IPI_PMU_1_OBS_PL_3_WIDTH 1 +#define IPI_PMU_1_OBS_PL_3_MASK 0X08000000 + +#define IPI_PMU_1_OBS_PL_2_SHIFT 26 +#define IPI_PMU_1_OBS_PL_2_WIDTH 1 +#define IPI_PMU_1_OBS_PL_2_MASK 0X04000000 + +#define IPI_PMU_1_OBS_PL_1_SHIFT 25 +#define IPI_PMU_1_OBS_PL_1_WIDTH 1 +#define IPI_PMU_1_OBS_PL_1_MASK 0X02000000 + +#define IPI_PMU_1_OBS_PL_0_SHIFT 24 +#define IPI_PMU_1_OBS_PL_0_WIDTH 1 +#define IPI_PMU_1_OBS_PL_0_MASK 0X01000000 + +#define IPI_PMU_1_OBS_PMU_3_SHIFT 19 +#define IPI_PMU_1_OBS_PMU_3_WIDTH 1 +#define IPI_PMU_1_OBS_PMU_3_MASK 0X00080000 + +#define IPI_PMU_1_OBS_PMU_2_SHIFT 18 +#define IPI_PMU_1_OBS_PMU_2_WIDTH 1 +#define IPI_PMU_1_OBS_PMU_2_MASK 0X00040000 + +#define IPI_PMU_1_OBS_PMU_1_SHIFT 17 +#define IPI_PMU_1_OBS_PMU_1_WIDTH 1 +#define IPI_PMU_1_OBS_PMU_1_MASK 0X00020000 + +#define IPI_PMU_1_OBS_PMU_0_SHIFT 16 +#define IPI_PMU_1_OBS_PMU_0_WIDTH 1 +#define IPI_PMU_1_OBS_PMU_0_MASK 0X00010000 + +#define IPI_PMU_1_OBS_RPU_1_SHIFT 9 +#define IPI_PMU_1_OBS_RPU_1_WIDTH 1 +#define IPI_PMU_1_OBS_RPU_1_MASK 0X00000200 + +#define IPI_PMU_1_OBS_RPU_0_SHIFT 8 +#define IPI_PMU_1_OBS_RPU_0_WIDTH 1 +#define IPI_PMU_1_OBS_RPU_0_MASK 0X00000100 + +#define IPI_PMU_1_OBS_APU_SHIFT 0 +#define IPI_PMU_1_OBS_APU_WIDTH 1 +#define IPI_PMU_1_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_1_ISR + */ +#define IPI_PMU_1_ISR ( ( IPI_BASEADDR ) + 0X00031010 ) + +#define IPI_PMU_1_ISR_PL_3_SHIFT 27 +#define IPI_PMU_1_ISR_PL_3_WIDTH 1 +#define IPI_PMU_1_ISR_PL_3_MASK 0X08000000 + +#define IPI_PMU_1_ISR_PL_2_SHIFT 26 +#define IPI_PMU_1_ISR_PL_2_WIDTH 1 +#define IPI_PMU_1_ISR_PL_2_MASK 0X04000000 + +#define IPI_PMU_1_ISR_PL_1_SHIFT 25 +#define IPI_PMU_1_ISR_PL_1_WIDTH 1 +#define IPI_PMU_1_ISR_PL_1_MASK 0X02000000 + +#define IPI_PMU_1_ISR_PL_0_SHIFT 24 +#define IPI_PMU_1_ISR_PL_0_WIDTH 1 +#define IPI_PMU_1_ISR_PL_0_MASK 0X01000000 + +#define IPI_PMU_1_ISR_PMU_3_SHIFT 19 +#define IPI_PMU_1_ISR_PMU_3_WIDTH 1 +#define IPI_PMU_1_ISR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_1_ISR_PMU_2_SHIFT 18 +#define IPI_PMU_1_ISR_PMU_2_WIDTH 1 +#define IPI_PMU_1_ISR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_1_ISR_PMU_1_SHIFT 17 +#define IPI_PMU_1_ISR_PMU_1_WIDTH 1 +#define IPI_PMU_1_ISR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_1_ISR_PMU_0_SHIFT 16 +#define IPI_PMU_1_ISR_PMU_0_WIDTH 1 +#define IPI_PMU_1_ISR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_1_ISR_RPU_1_SHIFT 9 +#define IPI_PMU_1_ISR_RPU_1_WIDTH 1 +#define IPI_PMU_1_ISR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_1_ISR_RPU_0_SHIFT 8 +#define IPI_PMU_1_ISR_RPU_0_WIDTH 1 +#define IPI_PMU_1_ISR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_1_ISR_APU_SHIFT 0 +#define IPI_PMU_1_ISR_APU_WIDTH 1 +#define IPI_PMU_1_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_1_IMR + */ +#define IPI_PMU_1_IMR ( ( IPI_BASEADDR ) + 0X00031014 ) + +#define IPI_PMU_1_IMR_PL_3_SHIFT 27 +#define IPI_PMU_1_IMR_PL_3_WIDTH 1 +#define IPI_PMU_1_IMR_PL_3_MASK 0X08000000 + +#define IPI_PMU_1_IMR_PL_2_SHIFT 26 +#define IPI_PMU_1_IMR_PL_2_WIDTH 1 +#define IPI_PMU_1_IMR_PL_2_MASK 0X04000000 + +#define IPI_PMU_1_IMR_PL_1_SHIFT 25 +#define IPI_PMU_1_IMR_PL_1_WIDTH 1 +#define IPI_PMU_1_IMR_PL_1_MASK 0X02000000 + +#define IPI_PMU_1_IMR_PL_0_SHIFT 24 +#define IPI_PMU_1_IMR_PL_0_WIDTH 1 +#define IPI_PMU_1_IMR_PL_0_MASK 0X01000000 + +#define IPI_PMU_1_IMR_PMU_3_SHIFT 19 +#define IPI_PMU_1_IMR_PMU_3_WIDTH 1 +#define IPI_PMU_1_IMR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_1_IMR_PMU_2_SHIFT 18 +#define IPI_PMU_1_IMR_PMU_2_WIDTH 1 +#define IPI_PMU_1_IMR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_1_IMR_PMU_1_SHIFT 17 +#define IPI_PMU_1_IMR_PMU_1_WIDTH 1 +#define IPI_PMU_1_IMR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_1_IMR_PMU_0_SHIFT 16 +#define IPI_PMU_1_IMR_PMU_0_WIDTH 1 +#define IPI_PMU_1_IMR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_1_IMR_RPU_1_SHIFT 9 +#define IPI_PMU_1_IMR_RPU_1_WIDTH 1 +#define IPI_PMU_1_IMR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_1_IMR_RPU_0_SHIFT 8 +#define IPI_PMU_1_IMR_RPU_0_WIDTH 1 +#define IPI_PMU_1_IMR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_1_IMR_APU_SHIFT 0 +#define IPI_PMU_1_IMR_APU_WIDTH 1 +#define IPI_PMU_1_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_1_IER + */ +#define IPI_PMU_1_IER ( ( IPI_BASEADDR ) + 0X00031018 ) + +#define IPI_PMU_1_IER_PL_3_SHIFT 27 +#define IPI_PMU_1_IER_PL_3_WIDTH 1 +#define IPI_PMU_1_IER_PL_3_MASK 0X08000000 + +#define IPI_PMU_1_IER_PL_2_SHIFT 26 +#define IPI_PMU_1_IER_PL_2_WIDTH 1 +#define IPI_PMU_1_IER_PL_2_MASK 0X04000000 + +#define IPI_PMU_1_IER_PL_1_SHIFT 25 +#define IPI_PMU_1_IER_PL_1_WIDTH 1 +#define IPI_PMU_1_IER_PL_1_MASK 0X02000000 + +#define IPI_PMU_1_IER_PL_0_SHIFT 24 +#define IPI_PMU_1_IER_PL_0_WIDTH 1 +#define IPI_PMU_1_IER_PL_0_MASK 0X01000000 + +#define IPI_PMU_1_IER_PMU_3_SHIFT 19 +#define IPI_PMU_1_IER_PMU_3_WIDTH 1 +#define IPI_PMU_1_IER_PMU_3_MASK 0X00080000 + +#define IPI_PMU_1_IER_PMU_2_SHIFT 18 +#define IPI_PMU_1_IER_PMU_2_WIDTH 1 +#define IPI_PMU_1_IER_PMU_2_MASK 0X00040000 + +#define IPI_PMU_1_IER_PMU_1_SHIFT 17 +#define IPI_PMU_1_IER_PMU_1_WIDTH 1 +#define IPI_PMU_1_IER_PMU_1_MASK 0X00020000 + +#define IPI_PMU_1_IER_PMU_0_SHIFT 16 +#define IPI_PMU_1_IER_PMU_0_WIDTH 1 +#define IPI_PMU_1_IER_PMU_0_MASK 0X00010000 + +#define IPI_PMU_1_IER_RPU_1_SHIFT 9 +#define IPI_PMU_1_IER_RPU_1_WIDTH 1 +#define IPI_PMU_1_IER_RPU_1_MASK 0X00000200 + +#define IPI_PMU_1_IER_RPU_0_SHIFT 8 +#define IPI_PMU_1_IER_RPU_0_WIDTH 1 +#define IPI_PMU_1_IER_RPU_0_MASK 0X00000100 + +#define IPI_PMU_1_IER_APU_SHIFT 0 +#define IPI_PMU_1_IER_APU_WIDTH 1 +#define IPI_PMU_1_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_1_IDR + */ +#define IPI_PMU_1_IDR ( ( IPI_BASEADDR ) + 0X0003101C ) + +#define IPI_PMU_1_IDR_PL_3_SHIFT 27 +#define IPI_PMU_1_IDR_PL_3_WIDTH 1 +#define IPI_PMU_1_IDR_PL_3_MASK 0X08000000 + +#define IPI_PMU_1_IDR_PL_2_SHIFT 26 +#define IPI_PMU_1_IDR_PL_2_WIDTH 1 +#define IPI_PMU_1_IDR_PL_2_MASK 0X04000000 + +#define IPI_PMU_1_IDR_PL_1_SHIFT 25 +#define IPI_PMU_1_IDR_PL_1_WIDTH 1 +#define IPI_PMU_1_IDR_PL_1_MASK 0X02000000 + +#define IPI_PMU_1_IDR_PL_0_SHIFT 24 +#define IPI_PMU_1_IDR_PL_0_WIDTH 1 +#define IPI_PMU_1_IDR_PL_0_MASK 0X01000000 + +#define IPI_PMU_1_IDR_PMU_3_SHIFT 19 +#define IPI_PMU_1_IDR_PMU_3_WIDTH 1 +#define IPI_PMU_1_IDR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_1_IDR_PMU_2_SHIFT 18 +#define IPI_PMU_1_IDR_PMU_2_WIDTH 1 +#define IPI_PMU_1_IDR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_1_IDR_PMU_1_SHIFT 17 +#define IPI_PMU_1_IDR_PMU_1_WIDTH 1 +#define IPI_PMU_1_IDR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_1_IDR_PMU_0_SHIFT 16 +#define IPI_PMU_1_IDR_PMU_0_WIDTH 1 +#define IPI_PMU_1_IDR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_1_IDR_RPU_1_SHIFT 9 +#define IPI_PMU_1_IDR_RPU_1_WIDTH 1 +#define IPI_PMU_1_IDR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_1_IDR_RPU_0_SHIFT 8 +#define IPI_PMU_1_IDR_RPU_0_WIDTH 1 +#define IPI_PMU_1_IDR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_1_IDR_APU_SHIFT 0 +#define IPI_PMU_1_IDR_APU_WIDTH 1 +#define IPI_PMU_1_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_2_TRIG + */ +#define IPI_PMU_2_TRIG ( ( IPI_BASEADDR ) + 0X00032000 ) + +#define IPI_PMU_2_TRIG_PL_3_SHIFT 27 +#define IPI_PMU_2_TRIG_PL_3_WIDTH 1 +#define IPI_PMU_2_TRIG_PL_3_MASK 0X08000000 + +#define IPI_PMU_2_TRIG_PL_2_SHIFT 26 +#define IPI_PMU_2_TRIG_PL_2_WIDTH 1 +#define IPI_PMU_2_TRIG_PL_2_MASK 0X04000000 + +#define IPI_PMU_2_TRIG_PL_1_SHIFT 25 +#define IPI_PMU_2_TRIG_PL_1_WIDTH 1 +#define IPI_PMU_2_TRIG_PL_1_MASK 0X02000000 + +#define IPI_PMU_2_TRIG_PL_0_SHIFT 24 +#define IPI_PMU_2_TRIG_PL_0_WIDTH 1 +#define IPI_PMU_2_TRIG_PL_0_MASK 0X01000000 + +#define IPI_PMU_2_TRIG_PMU_3_SHIFT 19 +#define IPI_PMU_2_TRIG_PMU_3_WIDTH 1 +#define IPI_PMU_2_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_PMU_2_TRIG_PMU_2_SHIFT 18 +#define IPI_PMU_2_TRIG_PMU_2_WIDTH 1 +#define IPI_PMU_2_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_PMU_2_TRIG_PMU_1_SHIFT 17 +#define IPI_PMU_2_TRIG_PMU_1_WIDTH 1 +#define IPI_PMU_2_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_PMU_2_TRIG_PMU_0_SHIFT 16 +#define IPI_PMU_2_TRIG_PMU_0_WIDTH 1 +#define IPI_PMU_2_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_PMU_2_TRIG_RPU_1_SHIFT 9 +#define IPI_PMU_2_TRIG_RPU_1_WIDTH 1 +#define IPI_PMU_2_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_PMU_2_TRIG_RPU_0_SHIFT 8 +#define IPI_PMU_2_TRIG_RPU_0_WIDTH 1 +#define IPI_PMU_2_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_PMU_2_TRIG_APU_SHIFT 0 +#define IPI_PMU_2_TRIG_APU_WIDTH 1 +#define IPI_PMU_2_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_2_OBS + */ +#define IPI_PMU_2_OBS ( ( IPI_BASEADDR ) + 0X00032004 ) + +#define IPI_PMU_2_OBS_PL_3_SHIFT 27 +#define IPI_PMU_2_OBS_PL_3_WIDTH 1 +#define IPI_PMU_2_OBS_PL_3_MASK 0X08000000 + +#define IPI_PMU_2_OBS_PL_2_SHIFT 26 +#define IPI_PMU_2_OBS_PL_2_WIDTH 1 +#define IPI_PMU_2_OBS_PL_2_MASK 0X04000000 + +#define IPI_PMU_2_OBS_PL_1_SHIFT 25 +#define IPI_PMU_2_OBS_PL_1_WIDTH 1 +#define IPI_PMU_2_OBS_PL_1_MASK 0X02000000 + +#define IPI_PMU_2_OBS_PL_0_SHIFT 24 +#define IPI_PMU_2_OBS_PL_0_WIDTH 1 +#define IPI_PMU_2_OBS_PL_0_MASK 0X01000000 + +#define IPI_PMU_2_OBS_PMU_3_SHIFT 19 +#define IPI_PMU_2_OBS_PMU_3_WIDTH 1 +#define IPI_PMU_2_OBS_PMU_3_MASK 0X00080000 + +#define IPI_PMU_2_OBS_PMU_2_SHIFT 18 +#define IPI_PMU_2_OBS_PMU_2_WIDTH 1 +#define IPI_PMU_2_OBS_PMU_2_MASK 0X00040000 + +#define IPI_PMU_2_OBS_PMU_1_SHIFT 17 +#define IPI_PMU_2_OBS_PMU_1_WIDTH 1 +#define IPI_PMU_2_OBS_PMU_1_MASK 0X00020000 + +#define IPI_PMU_2_OBS_PMU_0_SHIFT 16 +#define IPI_PMU_2_OBS_PMU_0_WIDTH 1 +#define IPI_PMU_2_OBS_PMU_0_MASK 0X00010000 + +#define IPI_PMU_2_OBS_RPU_1_SHIFT 9 +#define IPI_PMU_2_OBS_RPU_1_WIDTH 1 +#define IPI_PMU_2_OBS_RPU_1_MASK 0X00000200 + +#define IPI_PMU_2_OBS_RPU_0_SHIFT 8 +#define IPI_PMU_2_OBS_RPU_0_WIDTH 1 +#define IPI_PMU_2_OBS_RPU_0_MASK 0X00000100 + +#define IPI_PMU_2_OBS_APU_SHIFT 0 +#define IPI_PMU_2_OBS_APU_WIDTH 1 +#define IPI_PMU_2_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_2_ISR + */ +#define IPI_PMU_2_ISR ( ( IPI_BASEADDR ) + 0X00032010 ) + +#define IPI_PMU_2_ISR_PL_3_SHIFT 27 +#define IPI_PMU_2_ISR_PL_3_WIDTH 1 +#define IPI_PMU_2_ISR_PL_3_MASK 0X08000000 + +#define IPI_PMU_2_ISR_PL_2_SHIFT 26 +#define IPI_PMU_2_ISR_PL_2_WIDTH 1 +#define IPI_PMU_2_ISR_PL_2_MASK 0X04000000 + +#define IPI_PMU_2_ISR_PL_1_SHIFT 25 +#define IPI_PMU_2_ISR_PL_1_WIDTH 1 +#define IPI_PMU_2_ISR_PL_1_MASK 0X02000000 + +#define IPI_PMU_2_ISR_PL_0_SHIFT 24 +#define IPI_PMU_2_ISR_PL_0_WIDTH 1 +#define IPI_PMU_2_ISR_PL_0_MASK 0X01000000 + +#define IPI_PMU_2_ISR_PMU_3_SHIFT 19 +#define IPI_PMU_2_ISR_PMU_3_WIDTH 1 +#define IPI_PMU_2_ISR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_2_ISR_PMU_2_SHIFT 18 +#define IPI_PMU_2_ISR_PMU_2_WIDTH 1 +#define IPI_PMU_2_ISR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_2_ISR_PMU_1_SHIFT 17 +#define IPI_PMU_2_ISR_PMU_1_WIDTH 1 +#define IPI_PMU_2_ISR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_2_ISR_PMU_0_SHIFT 16 +#define IPI_PMU_2_ISR_PMU_0_WIDTH 1 +#define IPI_PMU_2_ISR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_2_ISR_RPU_1_SHIFT 9 +#define IPI_PMU_2_ISR_RPU_1_WIDTH 1 +#define IPI_PMU_2_ISR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_2_ISR_RPU_0_SHIFT 8 +#define IPI_PMU_2_ISR_RPU_0_WIDTH 1 +#define IPI_PMU_2_ISR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_2_ISR_APU_SHIFT 0 +#define IPI_PMU_2_ISR_APU_WIDTH 1 +#define IPI_PMU_2_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_2_IMR + */ +#define IPI_PMU_2_IMR ( ( IPI_BASEADDR ) + 0X00032014 ) + +#define IPI_PMU_2_IMR_PL_3_SHIFT 27 +#define IPI_PMU_2_IMR_PL_3_WIDTH 1 +#define IPI_PMU_2_IMR_PL_3_MASK 0X08000000 + +#define IPI_PMU_2_IMR_PL_2_SHIFT 26 +#define IPI_PMU_2_IMR_PL_2_WIDTH 1 +#define IPI_PMU_2_IMR_PL_2_MASK 0X04000000 + +#define IPI_PMU_2_IMR_PL_1_SHIFT 25 +#define IPI_PMU_2_IMR_PL_1_WIDTH 1 +#define IPI_PMU_2_IMR_PL_1_MASK 0X02000000 + +#define IPI_PMU_2_IMR_PL_0_SHIFT 24 +#define IPI_PMU_2_IMR_PL_0_WIDTH 1 +#define IPI_PMU_2_IMR_PL_0_MASK 0X01000000 + +#define IPI_PMU_2_IMR_PMU_3_SHIFT 19 +#define IPI_PMU_2_IMR_PMU_3_WIDTH 1 +#define IPI_PMU_2_IMR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_2_IMR_PMU_2_SHIFT 18 +#define IPI_PMU_2_IMR_PMU_2_WIDTH 1 +#define IPI_PMU_2_IMR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_2_IMR_PMU_1_SHIFT 17 +#define IPI_PMU_2_IMR_PMU_1_WIDTH 1 +#define IPI_PMU_2_IMR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_2_IMR_PMU_0_SHIFT 16 +#define IPI_PMU_2_IMR_PMU_0_WIDTH 1 +#define IPI_PMU_2_IMR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_2_IMR_RPU_1_SHIFT 9 +#define IPI_PMU_2_IMR_RPU_1_WIDTH 1 +#define IPI_PMU_2_IMR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_2_IMR_RPU_0_SHIFT 8 +#define IPI_PMU_2_IMR_RPU_0_WIDTH 1 +#define IPI_PMU_2_IMR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_2_IMR_APU_SHIFT 0 +#define IPI_PMU_2_IMR_APU_WIDTH 1 +#define IPI_PMU_2_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_2_IER + */ +#define IPI_PMU_2_IER ( ( IPI_BASEADDR ) + 0X00032018 ) + +#define IPI_PMU_2_IER_PL_3_SHIFT 27 +#define IPI_PMU_2_IER_PL_3_WIDTH 1 +#define IPI_PMU_2_IER_PL_3_MASK 0X08000000 + +#define IPI_PMU_2_IER_PL_2_SHIFT 26 +#define IPI_PMU_2_IER_PL_2_WIDTH 1 +#define IPI_PMU_2_IER_PL_2_MASK 0X04000000 + +#define IPI_PMU_2_IER_PL_1_SHIFT 25 +#define IPI_PMU_2_IER_PL_1_WIDTH 1 +#define IPI_PMU_2_IER_PL_1_MASK 0X02000000 + +#define IPI_PMU_2_IER_PL_0_SHIFT 24 +#define IPI_PMU_2_IER_PL_0_WIDTH 1 +#define IPI_PMU_2_IER_PL_0_MASK 0X01000000 + +#define IPI_PMU_2_IER_PMU_3_SHIFT 19 +#define IPI_PMU_2_IER_PMU_3_WIDTH 1 +#define IPI_PMU_2_IER_PMU_3_MASK 0X00080000 + +#define IPI_PMU_2_IER_PMU_2_SHIFT 18 +#define IPI_PMU_2_IER_PMU_2_WIDTH 1 +#define IPI_PMU_2_IER_PMU_2_MASK 0X00040000 + +#define IPI_PMU_2_IER_PMU_1_SHIFT 17 +#define IPI_PMU_2_IER_PMU_1_WIDTH 1 +#define IPI_PMU_2_IER_PMU_1_MASK 0X00020000 + +#define IPI_PMU_2_IER_PMU_0_SHIFT 16 +#define IPI_PMU_2_IER_PMU_0_WIDTH 1 +#define IPI_PMU_2_IER_PMU_0_MASK 0X00010000 + +#define IPI_PMU_2_IER_RPU_1_SHIFT 9 +#define IPI_PMU_2_IER_RPU_1_WIDTH 1 +#define IPI_PMU_2_IER_RPU_1_MASK 0X00000200 + +#define IPI_PMU_2_IER_RPU_0_SHIFT 8 +#define IPI_PMU_2_IER_RPU_0_WIDTH 1 +#define IPI_PMU_2_IER_RPU_0_MASK 0X00000100 + +#define IPI_PMU_2_IER_APU_SHIFT 0 +#define IPI_PMU_2_IER_APU_WIDTH 1 +#define IPI_PMU_2_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_2_IDR + */ +#define IPI_PMU_2_IDR ( ( IPI_BASEADDR ) + 0X0003201C ) + +#define IPI_PMU_2_IDR_PL_3_SHIFT 27 +#define IPI_PMU_2_IDR_PL_3_WIDTH 1 +#define IPI_PMU_2_IDR_PL_3_MASK 0X08000000 + +#define IPI_PMU_2_IDR_PL_2_SHIFT 26 +#define IPI_PMU_2_IDR_PL_2_WIDTH 1 +#define IPI_PMU_2_IDR_PL_2_MASK 0X04000000 + +#define IPI_PMU_2_IDR_PL_1_SHIFT 25 +#define IPI_PMU_2_IDR_PL_1_WIDTH 1 +#define IPI_PMU_2_IDR_PL_1_MASK 0X02000000 + +#define IPI_PMU_2_IDR_PL_0_SHIFT 24 +#define IPI_PMU_2_IDR_PL_0_WIDTH 1 +#define IPI_PMU_2_IDR_PL_0_MASK 0X01000000 + +#define IPI_PMU_2_IDR_PMU_3_SHIFT 19 +#define IPI_PMU_2_IDR_PMU_3_WIDTH 1 +#define IPI_PMU_2_IDR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_2_IDR_PMU_2_SHIFT 18 +#define IPI_PMU_2_IDR_PMU_2_WIDTH 1 +#define IPI_PMU_2_IDR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_2_IDR_PMU_1_SHIFT 17 +#define IPI_PMU_2_IDR_PMU_1_WIDTH 1 +#define IPI_PMU_2_IDR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_2_IDR_PMU_0_SHIFT 16 +#define IPI_PMU_2_IDR_PMU_0_WIDTH 1 +#define IPI_PMU_2_IDR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_2_IDR_RPU_1_SHIFT 9 +#define IPI_PMU_2_IDR_RPU_1_WIDTH 1 +#define IPI_PMU_2_IDR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_2_IDR_RPU_0_SHIFT 8 +#define IPI_PMU_2_IDR_RPU_0_WIDTH 1 +#define IPI_PMU_2_IDR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_2_IDR_APU_SHIFT 0 +#define IPI_PMU_2_IDR_APU_WIDTH 1 +#define IPI_PMU_2_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_3_TRIG + */ +#define IPI_PMU_3_TRIG ( ( IPI_BASEADDR ) + 0X00033000 ) + +#define IPI_PMU_3_TRIG_PL_3_SHIFT 27 +#define IPI_PMU_3_TRIG_PL_3_WIDTH 1 +#define IPI_PMU_3_TRIG_PL_3_MASK 0X08000000 + +#define IPI_PMU_3_TRIG_PL_2_SHIFT 26 +#define IPI_PMU_3_TRIG_PL_2_WIDTH 1 +#define IPI_PMU_3_TRIG_PL_2_MASK 0X04000000 + +#define IPI_PMU_3_TRIG_PL_1_SHIFT 25 +#define IPI_PMU_3_TRIG_PL_1_WIDTH 1 +#define IPI_PMU_3_TRIG_PL_1_MASK 0X02000000 + +#define IPI_PMU_3_TRIG_PL_0_SHIFT 24 +#define IPI_PMU_3_TRIG_PL_0_WIDTH 1 +#define IPI_PMU_3_TRIG_PL_0_MASK 0X01000000 + +#define IPI_PMU_3_TRIG_PMU_3_SHIFT 19 +#define IPI_PMU_3_TRIG_PMU_3_WIDTH 1 +#define IPI_PMU_3_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_PMU_3_TRIG_PMU_2_SHIFT 18 +#define IPI_PMU_3_TRIG_PMU_2_WIDTH 1 +#define IPI_PMU_3_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_PMU_3_TRIG_PMU_1_SHIFT 17 +#define IPI_PMU_3_TRIG_PMU_1_WIDTH 1 +#define IPI_PMU_3_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_PMU_3_TRIG_PMU_0_SHIFT 16 +#define IPI_PMU_3_TRIG_PMU_0_WIDTH 1 +#define IPI_PMU_3_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_PMU_3_TRIG_RPU_1_SHIFT 9 +#define IPI_PMU_3_TRIG_RPU_1_WIDTH 1 +#define IPI_PMU_3_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_PMU_3_TRIG_RPU_0_SHIFT 8 +#define IPI_PMU_3_TRIG_RPU_0_WIDTH 1 +#define IPI_PMU_3_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_PMU_3_TRIG_APU_SHIFT 0 +#define IPI_PMU_3_TRIG_APU_WIDTH 1 +#define IPI_PMU_3_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_3_OBS + */ +#define IPI_PMU_3_OBS ( ( IPI_BASEADDR ) + 0X00033004 ) + +#define IPI_PMU_3_OBS_PL_3_SHIFT 27 +#define IPI_PMU_3_OBS_PL_3_WIDTH 1 +#define IPI_PMU_3_OBS_PL_3_MASK 0X08000000 + +#define IPI_PMU_3_OBS_PL_2_SHIFT 26 +#define IPI_PMU_3_OBS_PL_2_WIDTH 1 +#define IPI_PMU_3_OBS_PL_2_MASK 0X04000000 + +#define IPI_PMU_3_OBS_PL_1_SHIFT 25 +#define IPI_PMU_3_OBS_PL_1_WIDTH 1 +#define IPI_PMU_3_OBS_PL_1_MASK 0X02000000 + +#define IPI_PMU_3_OBS_PL_0_SHIFT 24 +#define IPI_PMU_3_OBS_PL_0_WIDTH 1 +#define IPI_PMU_3_OBS_PL_0_MASK 0X01000000 + +#define IPI_PMU_3_OBS_PMU_3_SHIFT 19 +#define IPI_PMU_3_OBS_PMU_3_WIDTH 1 +#define IPI_PMU_3_OBS_PMU_3_MASK 0X00080000 + +#define IPI_PMU_3_OBS_PMU_2_SHIFT 18 +#define IPI_PMU_3_OBS_PMU_2_WIDTH 1 +#define IPI_PMU_3_OBS_PMU_2_MASK 0X00040000 + +#define IPI_PMU_3_OBS_PMU_1_SHIFT 17 +#define IPI_PMU_3_OBS_PMU_1_WIDTH 1 +#define IPI_PMU_3_OBS_PMU_1_MASK 0X00020000 + +#define IPI_PMU_3_OBS_PMU_0_SHIFT 16 +#define IPI_PMU_3_OBS_PMU_0_WIDTH 1 +#define IPI_PMU_3_OBS_PMU_0_MASK 0X00010000 + +#define IPI_PMU_3_OBS_RPU_1_SHIFT 9 +#define IPI_PMU_3_OBS_RPU_1_WIDTH 1 +#define IPI_PMU_3_OBS_RPU_1_MASK 0X00000200 + +#define IPI_PMU_3_OBS_RPU_0_SHIFT 8 +#define IPI_PMU_3_OBS_RPU_0_WIDTH 1 +#define IPI_PMU_3_OBS_RPU_0_MASK 0X00000100 + +#define IPI_PMU_3_OBS_APU_SHIFT 0 +#define IPI_PMU_3_OBS_APU_WIDTH 1 +#define IPI_PMU_3_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_3_ISR + */ +#define IPI_PMU_3_ISR ( ( IPI_BASEADDR ) + 0X00033010 ) + +#define IPI_PMU_3_ISR_PL_3_SHIFT 27 +#define IPI_PMU_3_ISR_PL_3_WIDTH 1 +#define IPI_PMU_3_ISR_PL_3_MASK 0X08000000 + +#define IPI_PMU_3_ISR_PL_2_SHIFT 26 +#define IPI_PMU_3_ISR_PL_2_WIDTH 1 +#define IPI_PMU_3_ISR_PL_2_MASK 0X04000000 + +#define IPI_PMU_3_ISR_PL_1_SHIFT 25 +#define IPI_PMU_3_ISR_PL_1_WIDTH 1 +#define IPI_PMU_3_ISR_PL_1_MASK 0X02000000 + +#define IPI_PMU_3_ISR_PL_0_SHIFT 24 +#define IPI_PMU_3_ISR_PL_0_WIDTH 1 +#define IPI_PMU_3_ISR_PL_0_MASK 0X01000000 + +#define IPI_PMU_3_ISR_PMU_3_SHIFT 19 +#define IPI_PMU_3_ISR_PMU_3_WIDTH 1 +#define IPI_PMU_3_ISR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_3_ISR_PMU_2_SHIFT 18 +#define IPI_PMU_3_ISR_PMU_2_WIDTH 1 +#define IPI_PMU_3_ISR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_3_ISR_PMU_1_SHIFT 17 +#define IPI_PMU_3_ISR_PMU_1_WIDTH 1 +#define IPI_PMU_3_ISR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_3_ISR_PMU_0_SHIFT 16 +#define IPI_PMU_3_ISR_PMU_0_WIDTH 1 +#define IPI_PMU_3_ISR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_3_ISR_RPU_1_SHIFT 9 +#define IPI_PMU_3_ISR_RPU_1_WIDTH 1 +#define IPI_PMU_3_ISR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_3_ISR_RPU_0_SHIFT 8 +#define IPI_PMU_3_ISR_RPU_0_WIDTH 1 +#define IPI_PMU_3_ISR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_3_ISR_APU_SHIFT 0 +#define IPI_PMU_3_ISR_APU_WIDTH 1 +#define IPI_PMU_3_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_3_IMR + */ +#define IPI_PMU_3_IMR ( ( IPI_BASEADDR ) + 0X00033014 ) + +#define IPI_PMU_3_IMR_PL_3_SHIFT 27 +#define IPI_PMU_3_IMR_PL_3_WIDTH 1 +#define IPI_PMU_3_IMR_PL_3_MASK 0X08000000 + +#define IPI_PMU_3_IMR_PL_2_SHIFT 26 +#define IPI_PMU_3_IMR_PL_2_WIDTH 1 +#define IPI_PMU_3_IMR_PL_2_MASK 0X04000000 + +#define IPI_PMU_3_IMR_PL_1_SHIFT 25 +#define IPI_PMU_3_IMR_PL_1_WIDTH 1 +#define IPI_PMU_3_IMR_PL_1_MASK 0X02000000 + +#define IPI_PMU_3_IMR_PL_0_SHIFT 24 +#define IPI_PMU_3_IMR_PL_0_WIDTH 1 +#define IPI_PMU_3_IMR_PL_0_MASK 0X01000000 + +#define IPI_PMU_3_IMR_PMU_3_SHIFT 19 +#define IPI_PMU_3_IMR_PMU_3_WIDTH 1 +#define IPI_PMU_3_IMR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_3_IMR_PMU_2_SHIFT 18 +#define IPI_PMU_3_IMR_PMU_2_WIDTH 1 +#define IPI_PMU_3_IMR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_3_IMR_PMU_1_SHIFT 17 +#define IPI_PMU_3_IMR_PMU_1_WIDTH 1 +#define IPI_PMU_3_IMR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_3_IMR_PMU_0_SHIFT 16 +#define IPI_PMU_3_IMR_PMU_0_WIDTH 1 +#define IPI_PMU_3_IMR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_3_IMR_RPU_1_SHIFT 9 +#define IPI_PMU_3_IMR_RPU_1_WIDTH 1 +#define IPI_PMU_3_IMR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_3_IMR_RPU_0_SHIFT 8 +#define IPI_PMU_3_IMR_RPU_0_WIDTH 1 +#define IPI_PMU_3_IMR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_3_IMR_APU_SHIFT 0 +#define IPI_PMU_3_IMR_APU_WIDTH 1 +#define IPI_PMU_3_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_3_IER + */ +#define IPI_PMU_3_IER ( ( IPI_BASEADDR ) + 0X00033018 ) + +#define IPI_PMU_3_IER_PL_3_SHIFT 27 +#define IPI_PMU_3_IER_PL_3_WIDTH 1 +#define IPI_PMU_3_IER_PL_3_MASK 0X08000000 + +#define IPI_PMU_3_IER_PL_2_SHIFT 26 +#define IPI_PMU_3_IER_PL_2_WIDTH 1 +#define IPI_PMU_3_IER_PL_2_MASK 0X04000000 + +#define IPI_PMU_3_IER_PL_1_SHIFT 25 +#define IPI_PMU_3_IER_PL_1_WIDTH 1 +#define IPI_PMU_3_IER_PL_1_MASK 0X02000000 + +#define IPI_PMU_3_IER_PL_0_SHIFT 24 +#define IPI_PMU_3_IER_PL_0_WIDTH 1 +#define IPI_PMU_3_IER_PL_0_MASK 0X01000000 + +#define IPI_PMU_3_IER_PMU_3_SHIFT 19 +#define IPI_PMU_3_IER_PMU_3_WIDTH 1 +#define IPI_PMU_3_IER_PMU_3_MASK 0X00080000 + +#define IPI_PMU_3_IER_PMU_2_SHIFT 18 +#define IPI_PMU_3_IER_PMU_2_WIDTH 1 +#define IPI_PMU_3_IER_PMU_2_MASK 0X00040000 + +#define IPI_PMU_3_IER_PMU_1_SHIFT 17 +#define IPI_PMU_3_IER_PMU_1_WIDTH 1 +#define IPI_PMU_3_IER_PMU_1_MASK 0X00020000 + +#define IPI_PMU_3_IER_PMU_0_SHIFT 16 +#define IPI_PMU_3_IER_PMU_0_WIDTH 1 +#define IPI_PMU_3_IER_PMU_0_MASK 0X00010000 + +#define IPI_PMU_3_IER_RPU_1_SHIFT 9 +#define IPI_PMU_3_IER_RPU_1_WIDTH 1 +#define IPI_PMU_3_IER_RPU_1_MASK 0X00000200 + +#define IPI_PMU_3_IER_RPU_0_SHIFT 8 +#define IPI_PMU_3_IER_RPU_0_WIDTH 1 +#define IPI_PMU_3_IER_RPU_0_MASK 0X00000100 + +#define IPI_PMU_3_IER_APU_SHIFT 0 +#define IPI_PMU_3_IER_APU_WIDTH 1 +#define IPI_PMU_3_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_PMU_3_IDR + */ +#define IPI_PMU_3_IDR ( ( IPI_BASEADDR ) + 0X0003301C ) + +#define IPI_PMU_3_IDR_PL_3_SHIFT 27 +#define IPI_PMU_3_IDR_PL_3_WIDTH 1 +#define IPI_PMU_3_IDR_PL_3_MASK 0X08000000 + +#define IPI_PMU_3_IDR_PL_2_SHIFT 26 +#define IPI_PMU_3_IDR_PL_2_WIDTH 1 +#define IPI_PMU_3_IDR_PL_2_MASK 0X04000000 + +#define IPI_PMU_3_IDR_PL_1_SHIFT 25 +#define IPI_PMU_3_IDR_PL_1_WIDTH 1 +#define IPI_PMU_3_IDR_PL_1_MASK 0X02000000 + +#define IPI_PMU_3_IDR_PL_0_SHIFT 24 +#define IPI_PMU_3_IDR_PL_0_WIDTH 1 +#define IPI_PMU_3_IDR_PL_0_MASK 0X01000000 + +#define IPI_PMU_3_IDR_PMU_3_SHIFT 19 +#define IPI_PMU_3_IDR_PMU_3_WIDTH 1 +#define IPI_PMU_3_IDR_PMU_3_MASK 0X00080000 + +#define IPI_PMU_3_IDR_PMU_2_SHIFT 18 +#define IPI_PMU_3_IDR_PMU_2_WIDTH 1 +#define IPI_PMU_3_IDR_PMU_2_MASK 0X00040000 + +#define IPI_PMU_3_IDR_PMU_1_SHIFT 17 +#define IPI_PMU_3_IDR_PMU_1_WIDTH 1 +#define IPI_PMU_3_IDR_PMU_1_MASK 0X00020000 + +#define IPI_PMU_3_IDR_PMU_0_SHIFT 16 +#define IPI_PMU_3_IDR_PMU_0_WIDTH 1 +#define IPI_PMU_3_IDR_PMU_0_MASK 0X00010000 + +#define IPI_PMU_3_IDR_RPU_1_SHIFT 9 +#define IPI_PMU_3_IDR_RPU_1_WIDTH 1 +#define IPI_PMU_3_IDR_RPU_1_MASK 0X00000200 + +#define IPI_PMU_3_IDR_RPU_0_SHIFT 8 +#define IPI_PMU_3_IDR_RPU_0_WIDTH 1 +#define IPI_PMU_3_IDR_RPU_0_MASK 0X00000100 + +#define IPI_PMU_3_IDR_APU_SHIFT 0 +#define IPI_PMU_3_IDR_APU_WIDTH 1 +#define IPI_PMU_3_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_0_TRIG + */ +#define IPI_PL_0_TRIG ( ( IPI_BASEADDR ) + 0X00040000 ) + +#define IPI_PL_0_TRIG_PL_3_SHIFT 27 +#define IPI_PL_0_TRIG_PL_3_WIDTH 1 +#define IPI_PL_0_TRIG_PL_3_MASK 0X08000000 + +#define IPI_PL_0_TRIG_PL_2_SHIFT 26 +#define IPI_PL_0_TRIG_PL_2_WIDTH 1 +#define IPI_PL_0_TRIG_PL_2_MASK 0X04000000 + +#define IPI_PL_0_TRIG_PL_1_SHIFT 25 +#define IPI_PL_0_TRIG_PL_1_WIDTH 1 +#define IPI_PL_0_TRIG_PL_1_MASK 0X02000000 + +#define IPI_PL_0_TRIG_PL_0_SHIFT 24 +#define IPI_PL_0_TRIG_PL_0_WIDTH 1 +#define IPI_PL_0_TRIG_PL_0_MASK 0X01000000 + +#define IPI_PL_0_TRIG_PMU_3_SHIFT 19 +#define IPI_PL_0_TRIG_PMU_3_WIDTH 1 +#define IPI_PL_0_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_PL_0_TRIG_PMU_2_SHIFT 18 +#define IPI_PL_0_TRIG_PMU_2_WIDTH 1 +#define IPI_PL_0_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_PL_0_TRIG_PMU_1_SHIFT 17 +#define IPI_PL_0_TRIG_PMU_1_WIDTH 1 +#define IPI_PL_0_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_PL_0_TRIG_PMU_0_SHIFT 16 +#define IPI_PL_0_TRIG_PMU_0_WIDTH 1 +#define IPI_PL_0_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_PL_0_TRIG_RPU_1_SHIFT 9 +#define IPI_PL_0_TRIG_RPU_1_WIDTH 1 +#define IPI_PL_0_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_PL_0_TRIG_RPU_0_SHIFT 8 +#define IPI_PL_0_TRIG_RPU_0_WIDTH 1 +#define IPI_PL_0_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_PL_0_TRIG_APU_SHIFT 0 +#define IPI_PL_0_TRIG_APU_WIDTH 1 +#define IPI_PL_0_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_0_OBS + */ +#define IPI_PL_0_OBS ( ( IPI_BASEADDR ) + 0X00040004 ) + +#define IPI_PL_0_OBS_PL_3_SHIFT 27 +#define IPI_PL_0_OBS_PL_3_WIDTH 1 +#define IPI_PL_0_OBS_PL_3_MASK 0X08000000 + +#define IPI_PL_0_OBS_PL_2_SHIFT 26 +#define IPI_PL_0_OBS_PL_2_WIDTH 1 +#define IPI_PL_0_OBS_PL_2_MASK 0X04000000 + +#define IPI_PL_0_OBS_PL_1_SHIFT 25 +#define IPI_PL_0_OBS_PL_1_WIDTH 1 +#define IPI_PL_0_OBS_PL_1_MASK 0X02000000 + +#define IPI_PL_0_OBS_PL_0_SHIFT 24 +#define IPI_PL_0_OBS_PL_0_WIDTH 1 +#define IPI_PL_0_OBS_PL_0_MASK 0X01000000 + +#define IPI_PL_0_OBS_PMU_3_SHIFT 19 +#define IPI_PL_0_OBS_PMU_3_WIDTH 1 +#define IPI_PL_0_OBS_PMU_3_MASK 0X00080000 + +#define IPI_PL_0_OBS_PMU_2_SHIFT 18 +#define IPI_PL_0_OBS_PMU_2_WIDTH 1 +#define IPI_PL_0_OBS_PMU_2_MASK 0X00040000 + +#define IPI_PL_0_OBS_PMU_1_SHIFT 17 +#define IPI_PL_0_OBS_PMU_1_WIDTH 1 +#define IPI_PL_0_OBS_PMU_1_MASK 0X00020000 + +#define IPI_PL_0_OBS_PMU_0_SHIFT 16 +#define IPI_PL_0_OBS_PMU_0_WIDTH 1 +#define IPI_PL_0_OBS_PMU_0_MASK 0X00010000 + +#define IPI_PL_0_OBS_RPU_1_SHIFT 9 +#define IPI_PL_0_OBS_RPU_1_WIDTH 1 +#define IPI_PL_0_OBS_RPU_1_MASK 0X00000200 + +#define IPI_PL_0_OBS_RPU_0_SHIFT 8 +#define IPI_PL_0_OBS_RPU_0_WIDTH 1 +#define IPI_PL_0_OBS_RPU_0_MASK 0X00000100 + +#define IPI_PL_0_OBS_APU_SHIFT 0 +#define IPI_PL_0_OBS_APU_WIDTH 1 +#define IPI_PL_0_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_0_ISR + */ +#define IPI_PL_0_ISR ( ( IPI_BASEADDR ) + 0X00040010 ) + +#define IPI_PL_0_ISR_PL_3_SHIFT 27 +#define IPI_PL_0_ISR_PL_3_WIDTH 1 +#define IPI_PL_0_ISR_PL_3_MASK 0X08000000 + +#define IPI_PL_0_ISR_PL_2_SHIFT 26 +#define IPI_PL_0_ISR_PL_2_WIDTH 1 +#define IPI_PL_0_ISR_PL_2_MASK 0X04000000 + +#define IPI_PL_0_ISR_PL_1_SHIFT 25 +#define IPI_PL_0_ISR_PL_1_WIDTH 1 +#define IPI_PL_0_ISR_PL_1_MASK 0X02000000 + +#define IPI_PL_0_ISR_PL_0_SHIFT 24 +#define IPI_PL_0_ISR_PL_0_WIDTH 1 +#define IPI_PL_0_ISR_PL_0_MASK 0X01000000 + +#define IPI_PL_0_ISR_PMU_3_SHIFT 19 +#define IPI_PL_0_ISR_PMU_3_WIDTH 1 +#define IPI_PL_0_ISR_PMU_3_MASK 0X00080000 + +#define IPI_PL_0_ISR_PMU_2_SHIFT 18 +#define IPI_PL_0_ISR_PMU_2_WIDTH 1 +#define IPI_PL_0_ISR_PMU_2_MASK 0X00040000 + +#define IPI_PL_0_ISR_PMU_1_SHIFT 17 +#define IPI_PL_0_ISR_PMU_1_WIDTH 1 +#define IPI_PL_0_ISR_PMU_1_MASK 0X00020000 + +#define IPI_PL_0_ISR_PMU_0_SHIFT 16 +#define IPI_PL_0_ISR_PMU_0_WIDTH 1 +#define IPI_PL_0_ISR_PMU_0_MASK 0X00010000 + +#define IPI_PL_0_ISR_RPU_1_SHIFT 9 +#define IPI_PL_0_ISR_RPU_1_WIDTH 1 +#define IPI_PL_0_ISR_RPU_1_MASK 0X00000200 + +#define IPI_PL_0_ISR_RPU_0_SHIFT 8 +#define IPI_PL_0_ISR_RPU_0_WIDTH 1 +#define IPI_PL_0_ISR_RPU_0_MASK 0X00000100 + +#define IPI_PL_0_ISR_APU_SHIFT 0 +#define IPI_PL_0_ISR_APU_WIDTH 1 +#define IPI_PL_0_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_0_IMR + */ +#define IPI_PL_0_IMR ( ( IPI_BASEADDR ) + 0X00040014 ) + +#define IPI_PL_0_IMR_PL_3_SHIFT 27 +#define IPI_PL_0_IMR_PL_3_WIDTH 1 +#define IPI_PL_0_IMR_PL_3_MASK 0X08000000 + +#define IPI_PL_0_IMR_PL_2_SHIFT 26 +#define IPI_PL_0_IMR_PL_2_WIDTH 1 +#define IPI_PL_0_IMR_PL_2_MASK 0X04000000 + +#define IPI_PL_0_IMR_PL_1_SHIFT 25 +#define IPI_PL_0_IMR_PL_1_WIDTH 1 +#define IPI_PL_0_IMR_PL_1_MASK 0X02000000 + +#define IPI_PL_0_IMR_PL_0_SHIFT 24 +#define IPI_PL_0_IMR_PL_0_WIDTH 1 +#define IPI_PL_0_IMR_PL_0_MASK 0X01000000 + +#define IPI_PL_0_IMR_PMU_3_SHIFT 19 +#define IPI_PL_0_IMR_PMU_3_WIDTH 1 +#define IPI_PL_0_IMR_PMU_3_MASK 0X00080000 + +#define IPI_PL_0_IMR_PMU_2_SHIFT 18 +#define IPI_PL_0_IMR_PMU_2_WIDTH 1 +#define IPI_PL_0_IMR_PMU_2_MASK 0X00040000 + +#define IPI_PL_0_IMR_PMU_1_SHIFT 17 +#define IPI_PL_0_IMR_PMU_1_WIDTH 1 +#define IPI_PL_0_IMR_PMU_1_MASK 0X00020000 + +#define IPI_PL_0_IMR_PMU_0_SHIFT 16 +#define IPI_PL_0_IMR_PMU_0_WIDTH 1 +#define IPI_PL_0_IMR_PMU_0_MASK 0X00010000 + +#define IPI_PL_0_IMR_RPU_1_SHIFT 9 +#define IPI_PL_0_IMR_RPU_1_WIDTH 1 +#define IPI_PL_0_IMR_RPU_1_MASK 0X00000200 + +#define IPI_PL_0_IMR_RPU_0_SHIFT 8 +#define IPI_PL_0_IMR_RPU_0_WIDTH 1 +#define IPI_PL_0_IMR_RPU_0_MASK 0X00000100 + +#define IPI_PL_0_IMR_APU_SHIFT 0 +#define IPI_PL_0_IMR_APU_WIDTH 1 +#define IPI_PL_0_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_0_IER + */ +#define IPI_PL_0_IER ( ( IPI_BASEADDR ) + 0X00040018 ) + +#define IPI_PL_0_IER_PL_3_SHIFT 27 +#define IPI_PL_0_IER_PL_3_WIDTH 1 +#define IPI_PL_0_IER_PL_3_MASK 0X08000000 + +#define IPI_PL_0_IER_PL_2_SHIFT 26 +#define IPI_PL_0_IER_PL_2_WIDTH 1 +#define IPI_PL_0_IER_PL_2_MASK 0X04000000 + +#define IPI_PL_0_IER_PL_1_SHIFT 25 +#define IPI_PL_0_IER_PL_1_WIDTH 1 +#define IPI_PL_0_IER_PL_1_MASK 0X02000000 + +#define IPI_PL_0_IER_PL_0_SHIFT 24 +#define IPI_PL_0_IER_PL_0_WIDTH 1 +#define IPI_PL_0_IER_PL_0_MASK 0X01000000 + +#define IPI_PL_0_IER_PMU_3_SHIFT 19 +#define IPI_PL_0_IER_PMU_3_WIDTH 1 +#define IPI_PL_0_IER_PMU_3_MASK 0X00080000 + +#define IPI_PL_0_IER_PMU_2_SHIFT 18 +#define IPI_PL_0_IER_PMU_2_WIDTH 1 +#define IPI_PL_0_IER_PMU_2_MASK 0X00040000 + +#define IPI_PL_0_IER_PMU_1_SHIFT 17 +#define IPI_PL_0_IER_PMU_1_WIDTH 1 +#define IPI_PL_0_IER_PMU_1_MASK 0X00020000 + +#define IPI_PL_0_IER_PMU_0_SHIFT 16 +#define IPI_PL_0_IER_PMU_0_WIDTH 1 +#define IPI_PL_0_IER_PMU_0_MASK 0X00010000 + +#define IPI_PL_0_IER_RPU_1_SHIFT 9 +#define IPI_PL_0_IER_RPU_1_WIDTH 1 +#define IPI_PL_0_IER_RPU_1_MASK 0X00000200 + +#define IPI_PL_0_IER_RPU_0_SHIFT 8 +#define IPI_PL_0_IER_RPU_0_WIDTH 1 +#define IPI_PL_0_IER_RPU_0_MASK 0X00000100 + +#define IPI_PL_0_IER_APU_SHIFT 0 +#define IPI_PL_0_IER_APU_WIDTH 1 +#define IPI_PL_0_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_0_IDR + */ +#define IPI_PL_0_IDR ( ( IPI_BASEADDR ) + 0X0004001C ) + +#define IPI_PL_0_IDR_PL_3_SHIFT 27 +#define IPI_PL_0_IDR_PL_3_WIDTH 1 +#define IPI_PL_0_IDR_PL_3_MASK 0X08000000 + +#define IPI_PL_0_IDR_PL_2_SHIFT 26 +#define IPI_PL_0_IDR_PL_2_WIDTH 1 +#define IPI_PL_0_IDR_PL_2_MASK 0X04000000 + +#define IPI_PL_0_IDR_PL_1_SHIFT 25 +#define IPI_PL_0_IDR_PL_1_WIDTH 1 +#define IPI_PL_0_IDR_PL_1_MASK 0X02000000 + +#define IPI_PL_0_IDR_PL_0_SHIFT 24 +#define IPI_PL_0_IDR_PL_0_WIDTH 1 +#define IPI_PL_0_IDR_PL_0_MASK 0X01000000 + +#define IPI_PL_0_IDR_PMU_3_SHIFT 19 +#define IPI_PL_0_IDR_PMU_3_WIDTH 1 +#define IPI_PL_0_IDR_PMU_3_MASK 0X00080000 + +#define IPI_PL_0_IDR_PMU_2_SHIFT 18 +#define IPI_PL_0_IDR_PMU_2_WIDTH 1 +#define IPI_PL_0_IDR_PMU_2_MASK 0X00040000 + +#define IPI_PL_0_IDR_PMU_1_SHIFT 17 +#define IPI_PL_0_IDR_PMU_1_WIDTH 1 +#define IPI_PL_0_IDR_PMU_1_MASK 0X00020000 + +#define IPI_PL_0_IDR_PMU_0_SHIFT 16 +#define IPI_PL_0_IDR_PMU_0_WIDTH 1 +#define IPI_PL_0_IDR_PMU_0_MASK 0X00010000 + +#define IPI_PL_0_IDR_RPU_1_SHIFT 9 +#define IPI_PL_0_IDR_RPU_1_WIDTH 1 +#define IPI_PL_0_IDR_RPU_1_MASK 0X00000200 + +#define IPI_PL_0_IDR_RPU_0_SHIFT 8 +#define IPI_PL_0_IDR_RPU_0_WIDTH 1 +#define IPI_PL_0_IDR_RPU_0_MASK 0X00000100 + +#define IPI_PL_0_IDR_APU_SHIFT 0 +#define IPI_PL_0_IDR_APU_WIDTH 1 +#define IPI_PL_0_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_1_TRIG + */ +#define IPI_PL_1_TRIG ( ( IPI_BASEADDR ) + 0X00050000 ) + +#define IPI_PL_1_TRIG_PL_3_SHIFT 27 +#define IPI_PL_1_TRIG_PL_3_WIDTH 1 +#define IPI_PL_1_TRIG_PL_3_MASK 0X08000000 + +#define IPI_PL_1_TRIG_PL_2_SHIFT 26 +#define IPI_PL_1_TRIG_PL_2_WIDTH 1 +#define IPI_PL_1_TRIG_PL_2_MASK 0X04000000 + +#define IPI_PL_1_TRIG_PL_1_SHIFT 25 +#define IPI_PL_1_TRIG_PL_1_WIDTH 1 +#define IPI_PL_1_TRIG_PL_1_MASK 0X02000000 + +#define IPI_PL_1_TRIG_PL_0_SHIFT 24 +#define IPI_PL_1_TRIG_PL_0_WIDTH 1 +#define IPI_PL_1_TRIG_PL_0_MASK 0X01000000 + +#define IPI_PL_1_TRIG_PMU_3_SHIFT 19 +#define IPI_PL_1_TRIG_PMU_3_WIDTH 1 +#define IPI_PL_1_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_PL_1_TRIG_PMU_2_SHIFT 18 +#define IPI_PL_1_TRIG_PMU_2_WIDTH 1 +#define IPI_PL_1_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_PL_1_TRIG_PMU_1_SHIFT 17 +#define IPI_PL_1_TRIG_PMU_1_WIDTH 1 +#define IPI_PL_1_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_PL_1_TRIG_PMU_0_SHIFT 16 +#define IPI_PL_1_TRIG_PMU_0_WIDTH 1 +#define IPI_PL_1_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_PL_1_TRIG_RPU_1_SHIFT 9 +#define IPI_PL_1_TRIG_RPU_1_WIDTH 1 +#define IPI_PL_1_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_PL_1_TRIG_RPU_0_SHIFT 8 +#define IPI_PL_1_TRIG_RPU_0_WIDTH 1 +#define IPI_PL_1_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_PL_1_TRIG_APU_SHIFT 0 +#define IPI_PL_1_TRIG_APU_WIDTH 1 +#define IPI_PL_1_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_1_OBS + */ +#define IPI_PL_1_OBS ( ( IPI_BASEADDR ) + 0X00050004 ) + +#define IPI_PL_1_OBS_PL_3_SHIFT 27 +#define IPI_PL_1_OBS_PL_3_WIDTH 1 +#define IPI_PL_1_OBS_PL_3_MASK 0X08000000 + +#define IPI_PL_1_OBS_PL_2_SHIFT 26 +#define IPI_PL_1_OBS_PL_2_WIDTH 1 +#define IPI_PL_1_OBS_PL_2_MASK 0X04000000 + +#define IPI_PL_1_OBS_PL_1_SHIFT 25 +#define IPI_PL_1_OBS_PL_1_WIDTH 1 +#define IPI_PL_1_OBS_PL_1_MASK 0X02000000 + +#define IPI_PL_1_OBS_PL_0_SHIFT 24 +#define IPI_PL_1_OBS_PL_0_WIDTH 1 +#define IPI_PL_1_OBS_PL_0_MASK 0X01000000 + +#define IPI_PL_1_OBS_PMU_3_SHIFT 19 +#define IPI_PL_1_OBS_PMU_3_WIDTH 1 +#define IPI_PL_1_OBS_PMU_3_MASK 0X00080000 + +#define IPI_PL_1_OBS_PMU_2_SHIFT 18 +#define IPI_PL_1_OBS_PMU_2_WIDTH 1 +#define IPI_PL_1_OBS_PMU_2_MASK 0X00040000 + +#define IPI_PL_1_OBS_PMU_1_SHIFT 17 +#define IPI_PL_1_OBS_PMU_1_WIDTH 1 +#define IPI_PL_1_OBS_PMU_1_MASK 0X00020000 + +#define IPI_PL_1_OBS_PMU_0_SHIFT 16 +#define IPI_PL_1_OBS_PMU_0_WIDTH 1 +#define IPI_PL_1_OBS_PMU_0_MASK 0X00010000 + +#define IPI_PL_1_OBS_RPU_1_SHIFT 9 +#define IPI_PL_1_OBS_RPU_1_WIDTH 1 +#define IPI_PL_1_OBS_RPU_1_MASK 0X00000200 + +#define IPI_PL_1_OBS_RPU_0_SHIFT 8 +#define IPI_PL_1_OBS_RPU_0_WIDTH 1 +#define IPI_PL_1_OBS_RPU_0_MASK 0X00000100 + +#define IPI_PL_1_OBS_APU_SHIFT 0 +#define IPI_PL_1_OBS_APU_WIDTH 1 +#define IPI_PL_1_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_1_ISR + */ +#define IPI_PL_1_ISR ( ( IPI_BASEADDR ) + 0X00050010 ) + +#define IPI_PL_1_ISR_PL_3_SHIFT 27 +#define IPI_PL_1_ISR_PL_3_WIDTH 1 +#define IPI_PL_1_ISR_PL_3_MASK 0X08000000 + +#define IPI_PL_1_ISR_PL_2_SHIFT 26 +#define IPI_PL_1_ISR_PL_2_WIDTH 1 +#define IPI_PL_1_ISR_PL_2_MASK 0X04000000 + +#define IPI_PL_1_ISR_PL_1_SHIFT 25 +#define IPI_PL_1_ISR_PL_1_WIDTH 1 +#define IPI_PL_1_ISR_PL_1_MASK 0X02000000 + +#define IPI_PL_1_ISR_PL_0_SHIFT 24 +#define IPI_PL_1_ISR_PL_0_WIDTH 1 +#define IPI_PL_1_ISR_PL_0_MASK 0X01000000 + +#define IPI_PL_1_ISR_PMU_3_SHIFT 19 +#define IPI_PL_1_ISR_PMU_3_WIDTH 1 +#define IPI_PL_1_ISR_PMU_3_MASK 0X00080000 + +#define IPI_PL_1_ISR_PMU_2_SHIFT 18 +#define IPI_PL_1_ISR_PMU_2_WIDTH 1 +#define IPI_PL_1_ISR_PMU_2_MASK 0X00040000 + +#define IPI_PL_1_ISR_PMU_1_SHIFT 17 +#define IPI_PL_1_ISR_PMU_1_WIDTH 1 +#define IPI_PL_1_ISR_PMU_1_MASK 0X00020000 + +#define IPI_PL_1_ISR_PMU_0_SHIFT 16 +#define IPI_PL_1_ISR_PMU_0_WIDTH 1 +#define IPI_PL_1_ISR_PMU_0_MASK 0X00010000 + +#define IPI_PL_1_ISR_RPU_1_SHIFT 9 +#define IPI_PL_1_ISR_RPU_1_WIDTH 1 +#define IPI_PL_1_ISR_RPU_1_MASK 0X00000200 + +#define IPI_PL_1_ISR_RPU_0_SHIFT 8 +#define IPI_PL_1_ISR_RPU_0_WIDTH 1 +#define IPI_PL_1_ISR_RPU_0_MASK 0X00000100 + +#define IPI_PL_1_ISR_APU_SHIFT 0 +#define IPI_PL_1_ISR_APU_WIDTH 1 +#define IPI_PL_1_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_1_IMR + */ +#define IPI_PL_1_IMR ( ( IPI_BASEADDR ) + 0X00050014 ) + +#define IPI_PL_1_IMR_PL_3_SHIFT 27 +#define IPI_PL_1_IMR_PL_3_WIDTH 1 +#define IPI_PL_1_IMR_PL_3_MASK 0X08000000 + +#define IPI_PL_1_IMR_PL_2_SHIFT 26 +#define IPI_PL_1_IMR_PL_2_WIDTH 1 +#define IPI_PL_1_IMR_PL_2_MASK 0X04000000 + +#define IPI_PL_1_IMR_PL_1_SHIFT 25 +#define IPI_PL_1_IMR_PL_1_WIDTH 1 +#define IPI_PL_1_IMR_PL_1_MASK 0X02000000 + +#define IPI_PL_1_IMR_PL_0_SHIFT 24 +#define IPI_PL_1_IMR_PL_0_WIDTH 1 +#define IPI_PL_1_IMR_PL_0_MASK 0X01000000 + +#define IPI_PL_1_IMR_PMU_3_SHIFT 19 +#define IPI_PL_1_IMR_PMU_3_WIDTH 1 +#define IPI_PL_1_IMR_PMU_3_MASK 0X00080000 + +#define IPI_PL_1_IMR_PMU_2_SHIFT 18 +#define IPI_PL_1_IMR_PMU_2_WIDTH 1 +#define IPI_PL_1_IMR_PMU_2_MASK 0X00040000 + +#define IPI_PL_1_IMR_PMU_1_SHIFT 17 +#define IPI_PL_1_IMR_PMU_1_WIDTH 1 +#define IPI_PL_1_IMR_PMU_1_MASK 0X00020000 + +#define IPI_PL_1_IMR_PMU_0_SHIFT 16 +#define IPI_PL_1_IMR_PMU_0_WIDTH 1 +#define IPI_PL_1_IMR_PMU_0_MASK 0X00010000 + +#define IPI_PL_1_IMR_RPU_1_SHIFT 9 +#define IPI_PL_1_IMR_RPU_1_WIDTH 1 +#define IPI_PL_1_IMR_RPU_1_MASK 0X00000200 + +#define IPI_PL_1_IMR_RPU_0_SHIFT 8 +#define IPI_PL_1_IMR_RPU_0_WIDTH 1 +#define IPI_PL_1_IMR_RPU_0_MASK 0X00000100 + +#define IPI_PL_1_IMR_APU_SHIFT 0 +#define IPI_PL_1_IMR_APU_WIDTH 1 +#define IPI_PL_1_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_1_IER + */ +#define IPI_PL_1_IER ( ( IPI_BASEADDR ) + 0X00050018 ) + +#define IPI_PL_1_IER_PL_3_SHIFT 27 +#define IPI_PL_1_IER_PL_3_WIDTH 1 +#define IPI_PL_1_IER_PL_3_MASK 0X08000000 + +#define IPI_PL_1_IER_PL_2_SHIFT 26 +#define IPI_PL_1_IER_PL_2_WIDTH 1 +#define IPI_PL_1_IER_PL_2_MASK 0X04000000 + +#define IPI_PL_1_IER_PL_1_SHIFT 25 +#define IPI_PL_1_IER_PL_1_WIDTH 1 +#define IPI_PL_1_IER_PL_1_MASK 0X02000000 + +#define IPI_PL_1_IER_PL_0_SHIFT 24 +#define IPI_PL_1_IER_PL_0_WIDTH 1 +#define IPI_PL_1_IER_PL_0_MASK 0X01000000 + +#define IPI_PL_1_IER_PMU_3_SHIFT 19 +#define IPI_PL_1_IER_PMU_3_WIDTH 1 +#define IPI_PL_1_IER_PMU_3_MASK 0X00080000 + +#define IPI_PL_1_IER_PMU_2_SHIFT 18 +#define IPI_PL_1_IER_PMU_2_WIDTH 1 +#define IPI_PL_1_IER_PMU_2_MASK 0X00040000 + +#define IPI_PL_1_IER_PMU_1_SHIFT 17 +#define IPI_PL_1_IER_PMU_1_WIDTH 1 +#define IPI_PL_1_IER_PMU_1_MASK 0X00020000 + +#define IPI_PL_1_IER_PMU_0_SHIFT 16 +#define IPI_PL_1_IER_PMU_0_WIDTH 1 +#define IPI_PL_1_IER_PMU_0_MASK 0X00010000 + +#define IPI_PL_1_IER_RPU_1_SHIFT 9 +#define IPI_PL_1_IER_RPU_1_WIDTH 1 +#define IPI_PL_1_IER_RPU_1_MASK 0X00000200 + +#define IPI_PL_1_IER_RPU_0_SHIFT 8 +#define IPI_PL_1_IER_RPU_0_WIDTH 1 +#define IPI_PL_1_IER_RPU_0_MASK 0X00000100 + +#define IPI_PL_1_IER_APU_SHIFT 0 +#define IPI_PL_1_IER_APU_WIDTH 1 +#define IPI_PL_1_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_1_IDR + */ +#define IPI_PL_1_IDR ( ( IPI_BASEADDR ) + 0X0005001C ) + +#define IPI_PL_1_IDR_PL_3_SHIFT 27 +#define IPI_PL_1_IDR_PL_3_WIDTH 1 +#define IPI_PL_1_IDR_PL_3_MASK 0X08000000 + +#define IPI_PL_1_IDR_PL_2_SHIFT 26 +#define IPI_PL_1_IDR_PL_2_WIDTH 1 +#define IPI_PL_1_IDR_PL_2_MASK 0X04000000 + +#define IPI_PL_1_IDR_PL_1_SHIFT 25 +#define IPI_PL_1_IDR_PL_1_WIDTH 1 +#define IPI_PL_1_IDR_PL_1_MASK 0X02000000 + +#define IPI_PL_1_IDR_PL_0_SHIFT 24 +#define IPI_PL_1_IDR_PL_0_WIDTH 1 +#define IPI_PL_1_IDR_PL_0_MASK 0X01000000 + +#define IPI_PL_1_IDR_PMU_3_SHIFT 19 +#define IPI_PL_1_IDR_PMU_3_WIDTH 1 +#define IPI_PL_1_IDR_PMU_3_MASK 0X00080000 + +#define IPI_PL_1_IDR_PMU_2_SHIFT 18 +#define IPI_PL_1_IDR_PMU_2_WIDTH 1 +#define IPI_PL_1_IDR_PMU_2_MASK 0X00040000 + +#define IPI_PL_1_IDR_PMU_1_SHIFT 17 +#define IPI_PL_1_IDR_PMU_1_WIDTH 1 +#define IPI_PL_1_IDR_PMU_1_MASK 0X00020000 + +#define IPI_PL_1_IDR_PMU_0_SHIFT 16 +#define IPI_PL_1_IDR_PMU_0_WIDTH 1 +#define IPI_PL_1_IDR_PMU_0_MASK 0X00010000 + +#define IPI_PL_1_IDR_RPU_1_SHIFT 9 +#define IPI_PL_1_IDR_RPU_1_WIDTH 1 +#define IPI_PL_1_IDR_RPU_1_MASK 0X00000200 + +#define IPI_PL_1_IDR_RPU_0_SHIFT 8 +#define IPI_PL_1_IDR_RPU_0_WIDTH 1 +#define IPI_PL_1_IDR_RPU_0_MASK 0X00000100 + +#define IPI_PL_1_IDR_APU_SHIFT 0 +#define IPI_PL_1_IDR_APU_WIDTH 1 +#define IPI_PL_1_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_2_TRIG + */ +#define IPI_PL_2_TRIG ( ( IPI_BASEADDR ) + 0X00060000 ) + +#define IPI_PL_2_TRIG_PL_3_SHIFT 27 +#define IPI_PL_2_TRIG_PL_3_WIDTH 1 +#define IPI_PL_2_TRIG_PL_3_MASK 0X08000000 + +#define IPI_PL_2_TRIG_PL_2_SHIFT 26 +#define IPI_PL_2_TRIG_PL_2_WIDTH 1 +#define IPI_PL_2_TRIG_PL_2_MASK 0X04000000 + +#define IPI_PL_2_TRIG_PL_1_SHIFT 25 +#define IPI_PL_2_TRIG_PL_1_WIDTH 1 +#define IPI_PL_2_TRIG_PL_1_MASK 0X02000000 + +#define IPI_PL_2_TRIG_PL_0_SHIFT 24 +#define IPI_PL_2_TRIG_PL_0_WIDTH 1 +#define IPI_PL_2_TRIG_PL_0_MASK 0X01000000 + +#define IPI_PL_2_TRIG_PMU_3_SHIFT 19 +#define IPI_PL_2_TRIG_PMU_3_WIDTH 1 +#define IPI_PL_2_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_PL_2_TRIG_PMU_2_SHIFT 18 +#define IPI_PL_2_TRIG_PMU_2_WIDTH 1 +#define IPI_PL_2_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_PL_2_TRIG_PMU_1_SHIFT 17 +#define IPI_PL_2_TRIG_PMU_1_WIDTH 1 +#define IPI_PL_2_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_PL_2_TRIG_PMU_0_SHIFT 16 +#define IPI_PL_2_TRIG_PMU_0_WIDTH 1 +#define IPI_PL_2_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_PL_2_TRIG_RPU_1_SHIFT 9 +#define IPI_PL_2_TRIG_RPU_1_WIDTH 1 +#define IPI_PL_2_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_PL_2_TRIG_RPU_0_SHIFT 8 +#define IPI_PL_2_TRIG_RPU_0_WIDTH 1 +#define IPI_PL_2_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_PL_2_TRIG_APU_SHIFT 0 +#define IPI_PL_2_TRIG_APU_WIDTH 1 +#define IPI_PL_2_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_2_OBS + */ +#define IPI_PL_2_OBS ( ( IPI_BASEADDR ) + 0X00060004 ) + +#define IPI_PL_2_OBS_PL_3_SHIFT 27 +#define IPI_PL_2_OBS_PL_3_WIDTH 1 +#define IPI_PL_2_OBS_PL_3_MASK 0X08000000 + +#define IPI_PL_2_OBS_PL_2_SHIFT 26 +#define IPI_PL_2_OBS_PL_2_WIDTH 1 +#define IPI_PL_2_OBS_PL_2_MASK 0X04000000 + +#define IPI_PL_2_OBS_PL_1_SHIFT 25 +#define IPI_PL_2_OBS_PL_1_WIDTH 1 +#define IPI_PL_2_OBS_PL_1_MASK 0X02000000 + +#define IPI_PL_2_OBS_PL_0_SHIFT 24 +#define IPI_PL_2_OBS_PL_0_WIDTH 1 +#define IPI_PL_2_OBS_PL_0_MASK 0X01000000 + +#define IPI_PL_2_OBS_PMU_3_SHIFT 19 +#define IPI_PL_2_OBS_PMU_3_WIDTH 1 +#define IPI_PL_2_OBS_PMU_3_MASK 0X00080000 + +#define IPI_PL_2_OBS_PMU_2_SHIFT 18 +#define IPI_PL_2_OBS_PMU_2_WIDTH 1 +#define IPI_PL_2_OBS_PMU_2_MASK 0X00040000 + +#define IPI_PL_2_OBS_PMU_1_SHIFT 17 +#define IPI_PL_2_OBS_PMU_1_WIDTH 1 +#define IPI_PL_2_OBS_PMU_1_MASK 0X00020000 + +#define IPI_PL_2_OBS_PMU_0_SHIFT 16 +#define IPI_PL_2_OBS_PMU_0_WIDTH 1 +#define IPI_PL_2_OBS_PMU_0_MASK 0X00010000 + +#define IPI_PL_2_OBS_RPU_1_SHIFT 9 +#define IPI_PL_2_OBS_RPU_1_WIDTH 1 +#define IPI_PL_2_OBS_RPU_1_MASK 0X00000200 + +#define IPI_PL_2_OBS_RPU_0_SHIFT 8 +#define IPI_PL_2_OBS_RPU_0_WIDTH 1 +#define IPI_PL_2_OBS_RPU_0_MASK 0X00000100 + +#define IPI_PL_2_OBS_APU_SHIFT 0 +#define IPI_PL_2_OBS_APU_WIDTH 1 +#define IPI_PL_2_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_2_ISR + */ +#define IPI_PL_2_ISR ( ( IPI_BASEADDR ) + 0X00060010 ) + +#define IPI_PL_2_ISR_PL_3_SHIFT 27 +#define IPI_PL_2_ISR_PL_3_WIDTH 1 +#define IPI_PL_2_ISR_PL_3_MASK 0X08000000 + +#define IPI_PL_2_ISR_PL_2_SHIFT 26 +#define IPI_PL_2_ISR_PL_2_WIDTH 1 +#define IPI_PL_2_ISR_PL_2_MASK 0X04000000 + +#define IPI_PL_2_ISR_PL_1_SHIFT 25 +#define IPI_PL_2_ISR_PL_1_WIDTH 1 +#define IPI_PL_2_ISR_PL_1_MASK 0X02000000 + +#define IPI_PL_2_ISR_PL_0_SHIFT 24 +#define IPI_PL_2_ISR_PL_0_WIDTH 1 +#define IPI_PL_2_ISR_PL_0_MASK 0X01000000 + +#define IPI_PL_2_ISR_PMU_3_SHIFT 19 +#define IPI_PL_2_ISR_PMU_3_WIDTH 1 +#define IPI_PL_2_ISR_PMU_3_MASK 0X00080000 + +#define IPI_PL_2_ISR_PMU_2_SHIFT 18 +#define IPI_PL_2_ISR_PMU_2_WIDTH 1 +#define IPI_PL_2_ISR_PMU_2_MASK 0X00040000 + +#define IPI_PL_2_ISR_PMU_1_SHIFT 17 +#define IPI_PL_2_ISR_PMU_1_WIDTH 1 +#define IPI_PL_2_ISR_PMU_1_MASK 0X00020000 + +#define IPI_PL_2_ISR_PMU_0_SHIFT 16 +#define IPI_PL_2_ISR_PMU_0_WIDTH 1 +#define IPI_PL_2_ISR_PMU_0_MASK 0X00010000 + +#define IPI_PL_2_ISR_RPU_1_SHIFT 9 +#define IPI_PL_2_ISR_RPU_1_WIDTH 1 +#define IPI_PL_2_ISR_RPU_1_MASK 0X00000200 + +#define IPI_PL_2_ISR_RPU_0_SHIFT 8 +#define IPI_PL_2_ISR_RPU_0_WIDTH 1 +#define IPI_PL_2_ISR_RPU_0_MASK 0X00000100 + +#define IPI_PL_2_ISR_APU_SHIFT 0 +#define IPI_PL_2_ISR_APU_WIDTH 1 +#define IPI_PL_2_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_2_IMR + */ +#define IPI_PL_2_IMR ( ( IPI_BASEADDR ) + 0X00060014 ) + +#define IPI_PL_2_IMR_PL_3_SHIFT 27 +#define IPI_PL_2_IMR_PL_3_WIDTH 1 +#define IPI_PL_2_IMR_PL_3_MASK 0X08000000 + +#define IPI_PL_2_IMR_PL_2_SHIFT 26 +#define IPI_PL_2_IMR_PL_2_WIDTH 1 +#define IPI_PL_2_IMR_PL_2_MASK 0X04000000 + +#define IPI_PL_2_IMR_PL_1_SHIFT 25 +#define IPI_PL_2_IMR_PL_1_WIDTH 1 +#define IPI_PL_2_IMR_PL_1_MASK 0X02000000 + +#define IPI_PL_2_IMR_PL_0_SHIFT 24 +#define IPI_PL_2_IMR_PL_0_WIDTH 1 +#define IPI_PL_2_IMR_PL_0_MASK 0X01000000 + +#define IPI_PL_2_IMR_PMU_3_SHIFT 19 +#define IPI_PL_2_IMR_PMU_3_WIDTH 1 +#define IPI_PL_2_IMR_PMU_3_MASK 0X00080000 + +#define IPI_PL_2_IMR_PMU_2_SHIFT 18 +#define IPI_PL_2_IMR_PMU_2_WIDTH 1 +#define IPI_PL_2_IMR_PMU_2_MASK 0X00040000 + +#define IPI_PL_2_IMR_PMU_1_SHIFT 17 +#define IPI_PL_2_IMR_PMU_1_WIDTH 1 +#define IPI_PL_2_IMR_PMU_1_MASK 0X00020000 + +#define IPI_PL_2_IMR_PMU_0_SHIFT 16 +#define IPI_PL_2_IMR_PMU_0_WIDTH 1 +#define IPI_PL_2_IMR_PMU_0_MASK 0X00010000 + +#define IPI_PL_2_IMR_RPU_1_SHIFT 9 +#define IPI_PL_2_IMR_RPU_1_WIDTH 1 +#define IPI_PL_2_IMR_RPU_1_MASK 0X00000200 + +#define IPI_PL_2_IMR_RPU_0_SHIFT 8 +#define IPI_PL_2_IMR_RPU_0_WIDTH 1 +#define IPI_PL_2_IMR_RPU_0_MASK 0X00000100 + +#define IPI_PL_2_IMR_APU_SHIFT 0 +#define IPI_PL_2_IMR_APU_WIDTH 1 +#define IPI_PL_2_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_2_IER + */ +#define IPI_PL_2_IER ( ( IPI_BASEADDR ) + 0X00060018 ) + +#define IPI_PL_2_IER_PL_3_SHIFT 27 +#define IPI_PL_2_IER_PL_3_WIDTH 1 +#define IPI_PL_2_IER_PL_3_MASK 0X08000000 + +#define IPI_PL_2_IER_PL_2_SHIFT 26 +#define IPI_PL_2_IER_PL_2_WIDTH 1 +#define IPI_PL_2_IER_PL_2_MASK 0X04000000 + +#define IPI_PL_2_IER_PL_1_SHIFT 25 +#define IPI_PL_2_IER_PL_1_WIDTH 1 +#define IPI_PL_2_IER_PL_1_MASK 0X02000000 + +#define IPI_PL_2_IER_PL_0_SHIFT 24 +#define IPI_PL_2_IER_PL_0_WIDTH 1 +#define IPI_PL_2_IER_PL_0_MASK 0X01000000 + +#define IPI_PL_2_IER_PMU_3_SHIFT 19 +#define IPI_PL_2_IER_PMU_3_WIDTH 1 +#define IPI_PL_2_IER_PMU_3_MASK 0X00080000 + +#define IPI_PL_2_IER_PMU_2_SHIFT 18 +#define IPI_PL_2_IER_PMU_2_WIDTH 1 +#define IPI_PL_2_IER_PMU_2_MASK 0X00040000 + +#define IPI_PL_2_IER_PMU_1_SHIFT 17 +#define IPI_PL_2_IER_PMU_1_WIDTH 1 +#define IPI_PL_2_IER_PMU_1_MASK 0X00020000 + +#define IPI_PL_2_IER_PMU_0_SHIFT 16 +#define IPI_PL_2_IER_PMU_0_WIDTH 1 +#define IPI_PL_2_IER_PMU_0_MASK 0X00010000 + +#define IPI_PL_2_IER_RPU_1_SHIFT 9 +#define IPI_PL_2_IER_RPU_1_WIDTH 1 +#define IPI_PL_2_IER_RPU_1_MASK 0X00000200 + +#define IPI_PL_2_IER_RPU_0_SHIFT 8 +#define IPI_PL_2_IER_RPU_0_WIDTH 1 +#define IPI_PL_2_IER_RPU_0_MASK 0X00000100 + +#define IPI_PL_2_IER_APU_SHIFT 0 +#define IPI_PL_2_IER_APU_WIDTH 1 +#define IPI_PL_2_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_2_IDR + */ +#define IPI_PL_2_IDR ( ( IPI_BASEADDR ) + 0X0006001C ) + +#define IPI_PL_2_IDR_PL_3_SHIFT 27 +#define IPI_PL_2_IDR_PL_3_WIDTH 1 +#define IPI_PL_2_IDR_PL_3_MASK 0X08000000 + +#define IPI_PL_2_IDR_PL_2_SHIFT 26 +#define IPI_PL_2_IDR_PL_2_WIDTH 1 +#define IPI_PL_2_IDR_PL_2_MASK 0X04000000 + +#define IPI_PL_2_IDR_PL_1_SHIFT 25 +#define IPI_PL_2_IDR_PL_1_WIDTH 1 +#define IPI_PL_2_IDR_PL_1_MASK 0X02000000 + +#define IPI_PL_2_IDR_PL_0_SHIFT 24 +#define IPI_PL_2_IDR_PL_0_WIDTH 1 +#define IPI_PL_2_IDR_PL_0_MASK 0X01000000 + +#define IPI_PL_2_IDR_PMU_3_SHIFT 19 +#define IPI_PL_2_IDR_PMU_3_WIDTH 1 +#define IPI_PL_2_IDR_PMU_3_MASK 0X00080000 + +#define IPI_PL_2_IDR_PMU_2_SHIFT 18 +#define IPI_PL_2_IDR_PMU_2_WIDTH 1 +#define IPI_PL_2_IDR_PMU_2_MASK 0X00040000 + +#define IPI_PL_2_IDR_PMU_1_SHIFT 17 +#define IPI_PL_2_IDR_PMU_1_WIDTH 1 +#define IPI_PL_2_IDR_PMU_1_MASK 0X00020000 + +#define IPI_PL_2_IDR_PMU_0_SHIFT 16 +#define IPI_PL_2_IDR_PMU_0_WIDTH 1 +#define IPI_PL_2_IDR_PMU_0_MASK 0X00010000 + +#define IPI_PL_2_IDR_RPU_1_SHIFT 9 +#define IPI_PL_2_IDR_RPU_1_WIDTH 1 +#define IPI_PL_2_IDR_RPU_1_MASK 0X00000200 + +#define IPI_PL_2_IDR_RPU_0_SHIFT 8 +#define IPI_PL_2_IDR_RPU_0_WIDTH 1 +#define IPI_PL_2_IDR_RPU_0_MASK 0X00000100 + +#define IPI_PL_2_IDR_APU_SHIFT 0 +#define IPI_PL_2_IDR_APU_WIDTH 1 +#define IPI_PL_2_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_3_TRIG + */ +#define IPI_PL_3_TRIG ( ( IPI_BASEADDR ) + 0X00070000 ) + +#define IPI_PL_3_TRIG_PL_3_SHIFT 27 +#define IPI_PL_3_TRIG_PL_3_WIDTH 1 +#define IPI_PL_3_TRIG_PL_3_MASK 0X08000000 + +#define IPI_PL_3_TRIG_PL_2_SHIFT 26 +#define IPI_PL_3_TRIG_PL_2_WIDTH 1 +#define IPI_PL_3_TRIG_PL_2_MASK 0X04000000 + +#define IPI_PL_3_TRIG_PL_1_SHIFT 25 +#define IPI_PL_3_TRIG_PL_1_WIDTH 1 +#define IPI_PL_3_TRIG_PL_1_MASK 0X02000000 + +#define IPI_PL_3_TRIG_PL_0_SHIFT 24 +#define IPI_PL_3_TRIG_PL_0_WIDTH 1 +#define IPI_PL_3_TRIG_PL_0_MASK 0X01000000 + +#define IPI_PL_3_TRIG_PMU_3_SHIFT 19 +#define IPI_PL_3_TRIG_PMU_3_WIDTH 1 +#define IPI_PL_3_TRIG_PMU_3_MASK 0X00080000 + +#define IPI_PL_3_TRIG_PMU_2_SHIFT 18 +#define IPI_PL_3_TRIG_PMU_2_WIDTH 1 +#define IPI_PL_3_TRIG_PMU_2_MASK 0X00040000 + +#define IPI_PL_3_TRIG_PMU_1_SHIFT 17 +#define IPI_PL_3_TRIG_PMU_1_WIDTH 1 +#define IPI_PL_3_TRIG_PMU_1_MASK 0X00020000 + +#define IPI_PL_3_TRIG_PMU_0_SHIFT 16 +#define IPI_PL_3_TRIG_PMU_0_WIDTH 1 +#define IPI_PL_3_TRIG_PMU_0_MASK 0X00010000 + +#define IPI_PL_3_TRIG_RPU_1_SHIFT 9 +#define IPI_PL_3_TRIG_RPU_1_WIDTH 1 +#define IPI_PL_3_TRIG_RPU_1_MASK 0X00000200 + +#define IPI_PL_3_TRIG_RPU_0_SHIFT 8 +#define IPI_PL_3_TRIG_RPU_0_WIDTH 1 +#define IPI_PL_3_TRIG_RPU_0_MASK 0X00000100 + +#define IPI_PL_3_TRIG_APU_SHIFT 0 +#define IPI_PL_3_TRIG_APU_WIDTH 1 +#define IPI_PL_3_TRIG_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_3_OBS + */ +#define IPI_PL_3_OBS ( ( IPI_BASEADDR ) + 0X00070004 ) + +#define IPI_PL_3_OBS_PL_3_SHIFT 27 +#define IPI_PL_3_OBS_PL_3_WIDTH 1 +#define IPI_PL_3_OBS_PL_3_MASK 0X08000000 + +#define IPI_PL_3_OBS_PL_2_SHIFT 26 +#define IPI_PL_3_OBS_PL_2_WIDTH 1 +#define IPI_PL_3_OBS_PL_2_MASK 0X04000000 + +#define IPI_PL_3_OBS_PL_1_SHIFT 25 +#define IPI_PL_3_OBS_PL_1_WIDTH 1 +#define IPI_PL_3_OBS_PL_1_MASK 0X02000000 + +#define IPI_PL_3_OBS_PL_0_SHIFT 24 +#define IPI_PL_3_OBS_PL_0_WIDTH 1 +#define IPI_PL_3_OBS_PL_0_MASK 0X01000000 + +#define IPI_PL_3_OBS_PMU_3_SHIFT 19 +#define IPI_PL_3_OBS_PMU_3_WIDTH 1 +#define IPI_PL_3_OBS_PMU_3_MASK 0X00080000 + +#define IPI_PL_3_OBS_PMU_2_SHIFT 18 +#define IPI_PL_3_OBS_PMU_2_WIDTH 1 +#define IPI_PL_3_OBS_PMU_2_MASK 0X00040000 + +#define IPI_PL_3_OBS_PMU_1_SHIFT 17 +#define IPI_PL_3_OBS_PMU_1_WIDTH 1 +#define IPI_PL_3_OBS_PMU_1_MASK 0X00020000 + +#define IPI_PL_3_OBS_PMU_0_SHIFT 16 +#define IPI_PL_3_OBS_PMU_0_WIDTH 1 +#define IPI_PL_3_OBS_PMU_0_MASK 0X00010000 + +#define IPI_PL_3_OBS_RPU_1_SHIFT 9 +#define IPI_PL_3_OBS_RPU_1_WIDTH 1 +#define IPI_PL_3_OBS_RPU_1_MASK 0X00000200 + +#define IPI_PL_3_OBS_RPU_0_SHIFT 8 +#define IPI_PL_3_OBS_RPU_0_WIDTH 1 +#define IPI_PL_3_OBS_RPU_0_MASK 0X00000100 + +#define IPI_PL_3_OBS_APU_SHIFT 0 +#define IPI_PL_3_OBS_APU_WIDTH 1 +#define IPI_PL_3_OBS_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_3_ISR + */ +#define IPI_PL_3_ISR ( ( IPI_BASEADDR ) + 0X00070010 ) + +#define IPI_PL_3_ISR_PL_3_SHIFT 27 +#define IPI_PL_3_ISR_PL_3_WIDTH 1 +#define IPI_PL_3_ISR_PL_3_MASK 0X08000000 + +#define IPI_PL_3_ISR_PL_2_SHIFT 26 +#define IPI_PL_3_ISR_PL_2_WIDTH 1 +#define IPI_PL_3_ISR_PL_2_MASK 0X04000000 + +#define IPI_PL_3_ISR_PL_1_SHIFT 25 +#define IPI_PL_3_ISR_PL_1_WIDTH 1 +#define IPI_PL_3_ISR_PL_1_MASK 0X02000000 + +#define IPI_PL_3_ISR_PL_0_SHIFT 24 +#define IPI_PL_3_ISR_PL_0_WIDTH 1 +#define IPI_PL_3_ISR_PL_0_MASK 0X01000000 + +#define IPI_PL_3_ISR_PMU_3_SHIFT 19 +#define IPI_PL_3_ISR_PMU_3_WIDTH 1 +#define IPI_PL_3_ISR_PMU_3_MASK 0X00080000 + +#define IPI_PL_3_ISR_PMU_2_SHIFT 18 +#define IPI_PL_3_ISR_PMU_2_WIDTH 1 +#define IPI_PL_3_ISR_PMU_2_MASK 0X00040000 + +#define IPI_PL_3_ISR_PMU_1_SHIFT 17 +#define IPI_PL_3_ISR_PMU_1_WIDTH 1 +#define IPI_PL_3_ISR_PMU_1_MASK 0X00020000 + +#define IPI_PL_3_ISR_PMU_0_SHIFT 16 +#define IPI_PL_3_ISR_PMU_0_WIDTH 1 +#define IPI_PL_3_ISR_PMU_0_MASK 0X00010000 + +#define IPI_PL_3_ISR_RPU_1_SHIFT 9 +#define IPI_PL_3_ISR_RPU_1_WIDTH 1 +#define IPI_PL_3_ISR_RPU_1_MASK 0X00000200 + +#define IPI_PL_3_ISR_RPU_0_SHIFT 8 +#define IPI_PL_3_ISR_RPU_0_WIDTH 1 +#define IPI_PL_3_ISR_RPU_0_MASK 0X00000100 + +#define IPI_PL_3_ISR_APU_SHIFT 0 +#define IPI_PL_3_ISR_APU_WIDTH 1 +#define IPI_PL_3_ISR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_3_IMR + */ +#define IPI_PL_3_IMR ( ( IPI_BASEADDR ) + 0X00070014 ) + +#define IPI_PL_3_IMR_PL_3_SHIFT 27 +#define IPI_PL_3_IMR_PL_3_WIDTH 1 +#define IPI_PL_3_IMR_PL_3_MASK 0X08000000 + +#define IPI_PL_3_IMR_PL_2_SHIFT 26 +#define IPI_PL_3_IMR_PL_2_WIDTH 1 +#define IPI_PL_3_IMR_PL_2_MASK 0X04000000 + +#define IPI_PL_3_IMR_PL_1_SHIFT 25 +#define IPI_PL_3_IMR_PL_1_WIDTH 1 +#define IPI_PL_3_IMR_PL_1_MASK 0X02000000 + +#define IPI_PL_3_IMR_PL_0_SHIFT 24 +#define IPI_PL_3_IMR_PL_0_WIDTH 1 +#define IPI_PL_3_IMR_PL_0_MASK 0X01000000 + +#define IPI_PL_3_IMR_PMU_3_SHIFT 19 +#define IPI_PL_3_IMR_PMU_3_WIDTH 1 +#define IPI_PL_3_IMR_PMU_3_MASK 0X00080000 + +#define IPI_PL_3_IMR_PMU_2_SHIFT 18 +#define IPI_PL_3_IMR_PMU_2_WIDTH 1 +#define IPI_PL_3_IMR_PMU_2_MASK 0X00040000 + +#define IPI_PL_3_IMR_PMU_1_SHIFT 17 +#define IPI_PL_3_IMR_PMU_1_WIDTH 1 +#define IPI_PL_3_IMR_PMU_1_MASK 0X00020000 + +#define IPI_PL_3_IMR_PMU_0_SHIFT 16 +#define IPI_PL_3_IMR_PMU_0_WIDTH 1 +#define IPI_PL_3_IMR_PMU_0_MASK 0X00010000 + +#define IPI_PL_3_IMR_RPU_1_SHIFT 9 +#define IPI_PL_3_IMR_RPU_1_WIDTH 1 +#define IPI_PL_3_IMR_RPU_1_MASK 0X00000200 + +#define IPI_PL_3_IMR_RPU_0_SHIFT 8 +#define IPI_PL_3_IMR_RPU_0_WIDTH 1 +#define IPI_PL_3_IMR_RPU_0_MASK 0X00000100 + +#define IPI_PL_3_IMR_APU_SHIFT 0 +#define IPI_PL_3_IMR_APU_WIDTH 1 +#define IPI_PL_3_IMR_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_3_IER + */ +#define IPI_PL_3_IER ( ( IPI_BASEADDR ) + 0X00070018 ) + +#define IPI_PL_3_IER_PL_3_SHIFT 27 +#define IPI_PL_3_IER_PL_3_WIDTH 1 +#define IPI_PL_3_IER_PL_3_MASK 0X08000000 + +#define IPI_PL_3_IER_PL_2_SHIFT 26 +#define IPI_PL_3_IER_PL_2_WIDTH 1 +#define IPI_PL_3_IER_PL_2_MASK 0X04000000 + +#define IPI_PL_3_IER_PL_1_SHIFT 25 +#define IPI_PL_3_IER_PL_1_WIDTH 1 +#define IPI_PL_3_IER_PL_1_MASK 0X02000000 + +#define IPI_PL_3_IER_PL_0_SHIFT 24 +#define IPI_PL_3_IER_PL_0_WIDTH 1 +#define IPI_PL_3_IER_PL_0_MASK 0X01000000 + +#define IPI_PL_3_IER_PMU_3_SHIFT 19 +#define IPI_PL_3_IER_PMU_3_WIDTH 1 +#define IPI_PL_3_IER_PMU_3_MASK 0X00080000 + +#define IPI_PL_3_IER_PMU_2_SHIFT 18 +#define IPI_PL_3_IER_PMU_2_WIDTH 1 +#define IPI_PL_3_IER_PMU_2_MASK 0X00040000 + +#define IPI_PL_3_IER_PMU_1_SHIFT 17 +#define IPI_PL_3_IER_PMU_1_WIDTH 1 +#define IPI_PL_3_IER_PMU_1_MASK 0X00020000 + +#define IPI_PL_3_IER_PMU_0_SHIFT 16 +#define IPI_PL_3_IER_PMU_0_WIDTH 1 +#define IPI_PL_3_IER_PMU_0_MASK 0X00010000 + +#define IPI_PL_3_IER_RPU_1_SHIFT 9 +#define IPI_PL_3_IER_RPU_1_WIDTH 1 +#define IPI_PL_3_IER_RPU_1_MASK 0X00000200 + +#define IPI_PL_3_IER_RPU_0_SHIFT 8 +#define IPI_PL_3_IER_RPU_0_WIDTH 1 +#define IPI_PL_3_IER_RPU_0_MASK 0X00000100 + +#define IPI_PL_3_IER_APU_SHIFT 0 +#define IPI_PL_3_IER_APU_WIDTH 1 +#define IPI_PL_3_IER_APU_MASK 0X00000001 + +/** + * Register: IPI_PL_3_IDR + */ +#define IPI_PL_3_IDR ( ( IPI_BASEADDR ) + 0X0007001C ) + +#define IPI_PL_3_IDR_PL_3_SHIFT 27 +#define IPI_PL_3_IDR_PL_3_WIDTH 1 +#define IPI_PL_3_IDR_PL_3_MASK 0X08000000 + +#define IPI_PL_3_IDR_PL_2_SHIFT 26 +#define IPI_PL_3_IDR_PL_2_WIDTH 1 +#define IPI_PL_3_IDR_PL_2_MASK 0X04000000 + +#define IPI_PL_3_IDR_PL_1_SHIFT 25 +#define IPI_PL_3_IDR_PL_1_WIDTH 1 +#define IPI_PL_3_IDR_PL_1_MASK 0X02000000 + +#define IPI_PL_3_IDR_PL_0_SHIFT 24 +#define IPI_PL_3_IDR_PL_0_WIDTH 1 +#define IPI_PL_3_IDR_PL_0_MASK 0X01000000 + +#define IPI_PL_3_IDR_PMU_3_SHIFT 19 +#define IPI_PL_3_IDR_PMU_3_WIDTH 1 +#define IPI_PL_3_IDR_PMU_3_MASK 0X00080000 + +#define IPI_PL_3_IDR_PMU_2_SHIFT 18 +#define IPI_PL_3_IDR_PMU_2_WIDTH 1 +#define IPI_PL_3_IDR_PMU_2_MASK 0X00040000 + +#define IPI_PL_3_IDR_PMU_1_SHIFT 17 +#define IPI_PL_3_IDR_PMU_1_WIDTH 1 +#define IPI_PL_3_IDR_PMU_1_MASK 0X00020000 + +#define IPI_PL_3_IDR_PMU_0_SHIFT 16 +#define IPI_PL_3_IDR_PMU_0_WIDTH 1 +#define IPI_PL_3_IDR_PMU_0_MASK 0X00010000 + +#define IPI_PL_3_IDR_RPU_1_SHIFT 9 +#define IPI_PL_3_IDR_RPU_1_WIDTH 1 +#define IPI_PL_3_IDR_RPU_1_MASK 0X00000200 + +#define IPI_PL_3_IDR_RPU_0_SHIFT 8 +#define IPI_PL_3_IDR_RPU_0_WIDTH 1 +#define IPI_PL_3_IDR_RPU_0_MASK 0X00000100 + +#define IPI_PL_3_IDR_APU_SHIFT 0 +#define IPI_PL_3_IDR_APU_WIDTH 1 +#define IPI_PL_3_IDR_APU_MASK 0X00000001 + +/** + * Register: IPI_IPI_CTRL + */ +#define IPI_IPI_CTRL ( ( IPI_BASEADDR ) + 0X00080000 ) + +#define IPI_IPI_CTRL_SLVERR_ENABLE_SHIFT 0 +#define IPI_IPI_CTRL_SLVERR_ENABLE_WIDTH 1 +#define IPI_IPI_CTRL_SLVERR_ENABLE_MASK 0X00000001 + +/** + * Register: IPI_IPI_ISR + */ +#define IPI_IPI_ISR ( ( IPI_BASEADDR ) + 0X00080010 ) + +#define IPI_IPI_ISR_ADDR_DECODE_ERR_SHIFT 0 +#define IPI_IPI_ISR_ADDR_DECODE_ERR_WIDTH 1 +#define IPI_IPI_ISR_ADDR_DECODE_ERR_MASK 0X00000001 + +/** + * Register: IPI_IPI_IMR + */ +#define IPI_IPI_IMR ( ( IPI_BASEADDR ) + 0X00080014 ) + +#define IPI_IPI_IMR_ADDR_DECODE_ERR_SHIFT 0 +#define IPI_IPI_IMR_ADDR_DECODE_ERR_WIDTH 1 +#define IPI_IPI_IMR_ADDR_DECODE_ERR_MASK 0X00000001 + +/** + * Register: IPI_IPI_IER + */ +#define IPI_IPI_IER ( ( IPI_BASEADDR ) + 0X00080018 ) + +#define IPI_IPI_IER_ADDR_DECODE_ERR_SHIFT 0 +#define IPI_IPI_IER_ADDR_DECODE_ERR_WIDTH 1 +#define IPI_IPI_IER_ADDR_DECODE_ERR_MASK 0X00000001 + +/** + * Register: IPI_IPI_ECO + */ +#define IPI_IPI_ECO ( ( IPI_BASEADDR ) + 0X00080020 ) + +#define IPI_IPI_ECO_ECO_SHIFT 0 +#define IPI_IPI_ECO_ECO_WIDTH 32 +#define IPI_IPI_ECO_ECO_MASK 0XFFFFFFFF + +/** + * Register: IPI_SAFETY_CHK + */ +#define IPI_SAFETY_CHK ( ( IPI_BASEADDR ) + 0X00080030 ) + +#define IPI_SAFETY_CHK_DATA_SHIFT 0 +#define IPI_SAFETY_CHK_DATA_WIDTH 32 +#define IPI_SAFETY_CHK_DATA_MASK 0XFFFFFFFF + +/** + * Register: IPI_IPI_IDR + */ +#define IPI_IPI_IDR ( ( IPI_BASEADDR ) + 0X000C001C ) + +#define IPI_IPI_IDR_ADDR_DECODE_ERR_SHIFT 0 +#define IPI_IPI_IDR_ADDR_DECODE_ERR_WIDTH 1 +#define IPI_IPI_IDR_ADDR_DECODE_ERR_MASK 0X00000001 + +#ifdef __cplusplus +} +#endif + + +#endif /* _IPI_H_ */ diff --git a/lib/sw_services/xilpm/src/common/pm_ipi_buffer.h b/lib/sw_services/xilpm/src/common/pm_ipi_buffer.h new file mode 100644 index 00000000..f286d564 --- /dev/null +++ b/lib/sw_services/xilpm/src/common/pm_ipi_buffer.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef PM_IPI_BUFFER_H_ +#define PM_IPI_BUFFER_H_ + +#define IPI_BUFFER_BASEADDR 0xFF990000U + +#define IPI_BUFFER_RPU_0_BASE (IPI_BUFFER_BASEADDR + 0x0U) +#define IPI_BUFFER_RPU_1_BASE (IPI_BUFFER_BASEADDR + 0x200U) +#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) +#define IPI_BUFFER_PL_0_BASE (IPI_BUFFER_BASEADDR + 0x600U) +#define IPI_BUFFER_PL_1_BASE (IPI_BUFFER_BASEADDR + 0x800U) +#define IPI_BUFFER_PL_2_BASE (IPI_BUFFER_BASEADDR + 0xA00U) +#define IPI_BUFFER_PL_3_BASE (IPI_BUFFER_BASEADDR + 0xC00U) +#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U) + +#define IPI_BUFFER_TARGET_RPU_0_OFFSET 0x0U +#define IPI_BUFFER_TARGET_RPU_1_OFFSET 0x40U +#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U +#define IPI_BUFFER_TARGET_PL_0_OFFSET 0xC0U +#define IPI_BUFFER_TARGET_PL_1_OFFSET 0x100U +#define IPI_BUFFER_TARGET_PL_2_OFFSET 0x140U +#define IPI_BUFFER_TARGET_PL_3_OFFSET 0x180U +#define IPI_BUFFER_TARGET_PMU_OFFSET 0x1C0U + +#define IPI_BUFFER_REQ_OFFSET 0x0U +#define IPI_BUFFER_RESP_OFFSET 0x20U + +#endif diff --git a/lib/sw_services/xilpm/src/rpu/pm_client.c b/lib/sw_services/xilpm/src/rpu/pm_client.c new file mode 100644 index 00000000..6724bd53 --- /dev/null +++ b/lib/sw_services/xilpm/src/rpu/pm_client.c @@ -0,0 +1,142 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * CONTENT + * Each PU client in the system have such file with definitions of + * masters in the subsystem and functions for getting informations + * about the master. + *********************************************************************/ + +#include "pm_client.h" + +static const struct XPm_Ipi rpu_0_ipi = { + .mask = IPI_RPU_MASK, + .base = IPI_BASEADDR, + .buffer_base = IPI_BUFFER_RPU_0_BASE, +}; + +static const struct XPm_Master pm_rpu_0_master = { + .node_id = NODE_RPU_0, + .pwrdn_mask = RPU_RPU_0_PWRDWN_EN_MASK, + .ipi = &rpu_0_ipi, +}; + +#if 0 +static const struct XPm_Master pm_rpu_1_master = { + .node_id = NODE_APU_1, + .pwrdn_mask = RPU_RPU_0_PWRDWN_EN_MASK, + .ipi = &rpu_0_ipi, +}; +#endif + +/* + * Order in pm_master_all array must match cpu ids + */ +static const struct XPm_Master *const pm_masters_all[] = { + &pm_rpu_0_master, +#if 0 + &pm_rpu_1_master, +#endif +}; + +/** + * pm_get_master() - returns pointer to the master structure + * @cpuid: id of the cpu whose master struct pointer should be returned + * + * Return: pointer to a master structure if master is found, otherwise NULL + */ +const struct XPm_Master *pm_get_master(const uint32_t cpuid) +{ + if (cpuid >=0 && PM_ARRAY_SIZE(pm_masters_all)) { + return pm_masters_all[cpuid]; + } + return NULL; +} + +/** + * pm_get_master_by_node() - returns pointer to the master structure + * @nid: ndoe id of the cpu master + * + * Return: pointer to a master structure if master is found, otherwise NULL + */ +const struct XPm_Master *pm_get_master_by_node(const enum XPmNodeId nid) +{ + uint8_t i; + for (i = 0; i < PM_ARRAY_SIZE(pm_masters_all); i++) { + if (nid == pm_masters_all[i]->node_id) { + return pm_masters_all[i]; + } + } + return NULL; +} + +static uint32_t pm_get_cpuid(const enum XPmNodeId node) +{ + uint32_t i; + for (i = 0; i < PM_ARRAY_SIZE(pm_masters_all); i++) { + if (pm_masters_all[i]->node_id == node) { + return i; + } + } + return UNDEFINED_CPUID; +} + +const enum XPmNodeId subsystem_node = NODE_RPU; +const struct XPm_Master *primary_master = &pm_rpu_0_master; + +void XPm_ClientSuspend(const struct XPm_Master *const master) +{ + /* Disable interrupts at processor level */ + pm_disable_int(); + /* Set powerdown request */ + pm_write(MASTER_PWRCTL, pm_read(MASTER_PWRCTL) | master->pwrdn_mask); +} + +void XPm_ClientAbortSuspend() +{ + /* Enable interrupts at processor level */ + pm_enable_int(); + /* Clear powerdown request */ + pm_write(MASTER_PWRCTL, pm_read(MASTER_PWRCTL) & ~primary_master->pwrdn_mask); +} + +void XPm_ClientWakeup(const struct XPm_Master *const master) +{ + uint32_t cpuid = pm_get_cpuid(master->node_id); + + if (UNDEFINED_CPUID != cpuid) { + uint32_t val = pm_read(MASTER_PWRCTL); + val &= ~(master->pwrdn_mask); + pm_write(MASTER_PWRCTL, val); + } +} diff --git a/lib/sw_services/xilpm/src/rpu/pm_client.h b/lib/sw_services/xilpm/src/rpu/pm_client.h new file mode 100644 index 00000000..81520cb2 --- /dev/null +++ b/lib/sw_services/xilpm/src/rpu/pm_client.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * CONTENT + * File is specific for each PU instance and must exist in order to + * port Power Management code for some new PU. + * Contains PU specific macros and macros to be defined depending on + * the execution environment. + *********************************************************************/ + +#ifndef _PM_CLIENT_H_ +#define _PM_CLIENT_H_ + +#include +#include +#include "pm_rpu.h" +#include "pm_defs.h" +#include "pm_common.h" + +#define MASTER_PWRCTL RPU_RPU_0_PWRDWN + +#define IPI_RPU_MASK 0x00000100U + +#define IPI_TRIG_OFFSET 0x00010000 +#define IPI_OBS_OFFSET 0x00010004 + +#define UNDEFINED_CPUID (~0) + +#define pm_read(addr) Xil_In32(addr) +#define pm_write(addr, value) Xil_Out32(addr, value) +#define pm_enable_int() Xil_ExceptionEnable() +#define pm_disable_int() Xil_ExceptionDisable() +#define pm_print(MSG, ...) xil_printf("RPU: "MSG,##__VA_ARGS__) +#define pm_this_cpuid() 0U + +/* Conditional debugging prints */ +#ifdef DEBUG_MODE + #define pm_dbg(MSG, ...) \ + do { \ + pm_print(MSG,##__VA_ARGS__); \ + } while (0) +#else + #define pm_dbg(MSG, ...) {} +#endif + +#ifndef bool + #define bool uint8_t + #define true 1U + #define false 0U +#endif + +void XPm_ClientSuspend(const struct XPm_Master *const master); +void XPm_ClientAbortSuspend(); +void XPm_ClientWakeup(const struct XPm_Master *const master); + +/* Do not modify below this line */ +extern const enum XPmNodeId subsystem_node; +extern const struct XPm_Master *primary_master; + +#endif /* _PM_CLIENT_H_ */ diff --git a/lib/sw_services/xilpm/src/rpu/pm_rpu.h b/lib/sw_services/xilpm/src/rpu/pm_rpu.h new file mode 100644 index 00000000..cb19c6c3 --- /dev/null +++ b/lib/sw_services/xilpm/src/rpu/pm_rpu.h @@ -0,0 +1,1527 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _PM_RPU_H_ +#define _PM_RPU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * RPU Base Address + */ +#define RPU_BASEADDR 0XFF9A0000 + +/** + * Register: RPU_RPU_GLBL_CNTL + */ +#define RPU_RPU_GLBL_CNTL ( ( RPU_BASEADDR ) + 0X00000000 ) + +#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_SHIFT 10 +#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_MASK 0X00000400 + +#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_SHIFT 8 +#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_MASK 0X00000100 + +#define RPU_RPU_GLBL_CNTL_TCM_WAIT_SHIFT 7 +#define RPU_RPU_GLBL_CNTL_TCM_WAIT_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_TCM_WAIT_MASK 0X00000080 + +#define RPU_RPU_GLBL_CNTL_TCM_COMB_SHIFT 6 +#define RPU_RPU_GLBL_CNTL_TCM_COMB_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_TCM_COMB_MASK 0X00000040 + +#define RPU_RPU_GLBL_CNTL_TEINIT_SHIFT 5 +#define RPU_RPU_GLBL_CNTL_TEINIT_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_TEINIT_MASK 0X00000020 + +#define RPU_RPU_GLBL_CNTL_SLCLAMP_SHIFT 4 +#define RPU_RPU_GLBL_CNTL_SLCLAMP_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_SLCLAMP_MASK 0X00000010 + +#define RPU_RPU_GLBL_CNTL_SLSPLIT_SHIFT 3 +#define RPU_RPU_GLBL_CNTL_SLSPLIT_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_SLSPLIT_MASK 0X00000008 + +#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_SHIFT 2 +#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_MASK 0X00000004 + +#define RPU_RPU_GLBL_CNTL_CFGIE_SHIFT 1 +#define RPU_RPU_GLBL_CNTL_CFGIE_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_CFGIE_MASK 0X00000002 + +#define RPU_RPU_GLBL_CNTL_CFGEE_SHIFT 0 +#define RPU_RPU_GLBL_CNTL_CFGEE_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_CFGEE_MASK 0X00000001 + +/** + * Register: RPU_RPU_GLBL_STATUS + */ +#define RPU_RPU_GLBL_STATUS ( ( RPU_BASEADDR ) + 0X00000004 ) + +#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_SHIFT 0 +#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_WIDTH 1 +#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_MASK 0X00000001 + +/** + * Register: RPU_RPU_ERR_CNTL + */ +#define RPU_RPU_ERR_CNTL ( ( RPU_BASEADDR ) + 0X00000008 ) + +#define RPU_RPU_ERR_CNTL_APB_ERR_RES_SHIFT 0 +#define RPU_RPU_ERR_CNTL_APB_ERR_RES_WIDTH 1 +#define RPU_RPU_ERR_CNTL_APB_ERR_RES_MASK 0X00000001 + +/** + * Register: RPU_RPU_RAM + */ +#define RPU_RPU_RAM ( ( RPU_BASEADDR ) + 0X0000000C ) + +#define RPU_RPU_RAM_RAMCONTROL1_SHIFT 8 +#define RPU_RPU_RAM_RAMCONTROL1_WIDTH 8 +#define RPU_RPU_RAM_RAMCONTROL1_MASK 0X0000FF00 + +#define RPU_RPU_RAM_RAMCONTROL0_SHIFT 0 +#define RPU_RPU_RAM_RAMCONTROL0_WIDTH 8 +#define RPU_RPU_RAM_RAMCONTROL0_MASK 0X000000FF + +/** + * Register: RPU_RPU_CACHE_DATA + */ +#define RPU_RPU_CACHE_DATA ( ( RPU_BASEADDR ) + 0X00000010 ) + +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_SHIFT 29 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_MASK 0X20000000 + +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_SHIFT 27 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_MASK 0X18000000 + +#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_SHIFT 24 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_MASK 0X07000000 + +#define RPU_RPU_CACHE_DATA_DTAG_EMAS_SHIFT 23 +#define RPU_RPU_CACHE_DATA_DTAG_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_DTAG_EMAS_MASK 0X00800000 + +#define RPU_RPU_CACHE_DATA_DTAG_EMAW_SHIFT 21 +#define RPU_RPU_CACHE_DATA_DTAG_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_DTAG_EMAW_MASK 0X00600000 + +#define RPU_RPU_CACHE_DATA_DTAG_EMA_SHIFT 18 +#define RPU_RPU_CACHE_DATA_DTAG_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_DTAG_EMA_MASK 0X001C0000 + +#define RPU_RPU_CACHE_DATA_DDATA_EMAS_SHIFT 17 +#define RPU_RPU_CACHE_DATA_DDATA_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_DDATA_EMAS_MASK 0X00020000 + +#define RPU_RPU_CACHE_DATA_DDATA_EMAW_SHIFT 15 +#define RPU_RPU_CACHE_DATA_DDATA_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_DDATA_EMAW_MASK 0X00018000 + +#define RPU_RPU_CACHE_DATA_DDATA_EMA_SHIFT 12 +#define RPU_RPU_CACHE_DATA_DDATA_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_DDATA_EMA_MASK 0X00007000 + +#define RPU_RPU_CACHE_DATA_ITAG_EMAS_SHIFT 11 +#define RPU_RPU_CACHE_DATA_ITAG_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_ITAG_EMAS_MASK 0X00000800 + +#define RPU_RPU_CACHE_DATA_ITAG_EMAW_SHIFT 9 +#define RPU_RPU_CACHE_DATA_ITAG_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_ITAG_EMAW_MASK 0X00000600 + +#define RPU_RPU_CACHE_DATA_ITAG_EMA_SHIFT 6 +#define RPU_RPU_CACHE_DATA_ITAG_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_ITAG_EMA_MASK 0X000001C0 + +#define RPU_RPU_CACHE_DATA_IDATA_EMAS_SHIFT 5 +#define RPU_RPU_CACHE_DATA_IDATA_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_IDATA_EMAS_MASK 0X00000020 + +#define RPU_RPU_CACHE_DATA_IDATA_EMAW_SHIFT 3 +#define RPU_RPU_CACHE_DATA_IDATA_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_IDATA_EMAW_MASK 0X00000018 + +#define RPU_RPU_CACHE_DATA_IDATA_EMA_SHIFT 0 +#define RPU_RPU_CACHE_DATA_IDATA_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_IDATA_EMA_MASK 0X00000007 + +/** + * Register: RPU_RPU_CACHE_SYN + */ +#define RPU_RPU_CACHE_SYN ( ( RPU_BASEADDR ) + 0X00000014 ) + +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_SHIFT 29 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_MASK 0X20000000 + +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_SHIFT 27 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_MASK 0X18000000 + +#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_SHIFT 24 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_MASK 0X07000000 + +#define RPU_RPU_CACHE_SYN_DTAG_EMAS_SHIFT 23 +#define RPU_RPU_CACHE_SYN_DTAG_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_DTAG_EMAS_MASK 0X00800000 + +#define RPU_RPU_CACHE_SYN_DTAG_EMAW_SHIFT 21 +#define RPU_RPU_CACHE_SYN_DTAG_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_DTAG_EMAW_MASK 0X00600000 + +#define RPU_RPU_CACHE_SYN_DTAG_EMA_SHIFT 18 +#define RPU_RPU_CACHE_SYN_DTAG_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_DTAG_EMA_MASK 0X001C0000 + +#define RPU_RPU_CACHE_SYN_DDATA_EMAS_SHIFT 17 +#define RPU_RPU_CACHE_SYN_DDATA_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_DDATA_EMAS_MASK 0X00020000 + +#define RPU_RPU_CACHE_SYN_DDATA_EMAW_SHIFT 15 +#define RPU_RPU_CACHE_SYN_DDATA_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_DDATA_EMAW_MASK 0X00018000 + +#define RPU_RPU_CACHE_SYN_DDATA_EMA_SHIFT 12 +#define RPU_RPU_CACHE_SYN_DDATA_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_DDATA_EMA_MASK 0X00007000 + +#define RPU_RPU_CACHE_SYN_ITAG_EMAS_SHIFT 11 +#define RPU_RPU_CACHE_SYN_ITAG_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_ITAG_EMAS_MASK 0X00000800 + +#define RPU_RPU_CACHE_SYN_ITAG_EMAW_SHIFT 9 +#define RPU_RPU_CACHE_SYN_ITAG_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_ITAG_EMAW_MASK 0X00000600 + +#define RPU_RPU_CACHE_SYN_ITAG_EMA_SHIFT 6 +#define RPU_RPU_CACHE_SYN_ITAG_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_ITAG_EMA_MASK 0X000001C0 + +#define RPU_RPU_CACHE_SYN_IDATA_EMAS_SHIFT 5 +#define RPU_RPU_CACHE_SYN_IDATA_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_IDATA_EMAS_MASK 0X00000020 + +#define RPU_RPU_CACHE_SYN_IDATA_EMAW_SHIFT 3 +#define RPU_RPU_CACHE_SYN_IDATA_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_IDATA_EMAW_MASK 0X00000018 + +#define RPU_RPU_CACHE_SYN_IDATA_EMA_SHIFT 0 +#define RPU_RPU_CACHE_SYN_IDATA_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_IDATA_EMA_MASK 0X00000007 + +/** + * Register: RPU_RPU_TCM_DATA + */ +#define RPU_RPU_TCM_DATA ( ( RPU_BASEADDR ) + 0X00000018 ) + +#define RPU_RPU_TCM_DATA_B_EMAS_SHIFT 17 +#define RPU_RPU_TCM_DATA_B_EMAS_WIDTH 1 +#define RPU_RPU_TCM_DATA_B_EMAS_MASK 0X00020000 + +#define RPU_RPU_TCM_DATA_B_EMAW_SHIFT 15 +#define RPU_RPU_TCM_DATA_B_EMAW_WIDTH 2 +#define RPU_RPU_TCM_DATA_B_EMAW_MASK 0X00018000 + +#define RPU_RPU_TCM_DATA_B_EMA_SHIFT 12 +#define RPU_RPU_TCM_DATA_B_EMA_WIDTH 3 +#define RPU_RPU_TCM_DATA_B_EMA_MASK 0X00007000 + +#define RPU_RPU_TCM_DATA_A_EMAS_SHIFT 5 +#define RPU_RPU_TCM_DATA_A_EMAS_WIDTH 1 +#define RPU_RPU_TCM_DATA_A_EMAS_MASK 0X00000020 + +#define RPU_RPU_TCM_DATA_A_EMAW_SHIFT 3 +#define RPU_RPU_TCM_DATA_A_EMAW_WIDTH 2 +#define RPU_RPU_TCM_DATA_A_EMAW_MASK 0X00000018 + +#define RPU_RPU_TCM_DATA_A_EMA_SHIFT 0 +#define RPU_RPU_TCM_DATA_A_EMA_WIDTH 3 +#define RPU_RPU_TCM_DATA_A_EMA_MASK 0X00000007 + +/** + * Register: RPU_RPU_TCM_SYN + */ +#define RPU_RPU_TCM_SYN ( ( RPU_BASEADDR ) + 0X0000001C ) + +#define RPU_RPU_TCM_SYN_B_EMAS_SHIFT 23 +#define RPU_RPU_TCM_SYN_B_EMAS_WIDTH 1 +#define RPU_RPU_TCM_SYN_B_EMAS_MASK 0X00800000 + +#define RPU_RPU_TCM_SYN_B_EMAW_SHIFT 21 +#define RPU_RPU_TCM_SYN_B_EMAW_WIDTH 2 +#define RPU_RPU_TCM_SYN_B_EMAW_MASK 0X00600000 + +#define RPU_RPU_TCM_SYN_B_EMA_SHIFT 18 +#define RPU_RPU_TCM_SYN_B_EMA_WIDTH 3 +#define RPU_RPU_TCM_SYN_B_EMA_MASK 0X001C0000 + +#define RPU_RPU_TCM_SYN_A_EMAS_SHIFT 11 +#define RPU_RPU_TCM_SYN_A_EMAS_WIDTH 1 +#define RPU_RPU_TCM_SYN_A_EMAS_MASK 0X00000800 + +#define RPU_RPU_TCM_SYN_A_EMAW_SHIFT 9 +#define RPU_RPU_TCM_SYN_A_EMAW_WIDTH 2 +#define RPU_RPU_TCM_SYN_A_EMAW_MASK 0X00000600 + +#define RPU_RPU_TCM_SYN_A_EMA_SHIFT 6 +#define RPU_RPU_TCM_SYN_A_EMA_WIDTH 3 +#define RPU_RPU_TCM_SYN_A_EMA_MASK 0X000001C0 + +/** + * Register: RPU_RPU_ERR_INJ + */ +#define RPU_RPU_ERR_INJ ( ( RPU_BASEADDR ) + 0X00000020 ) + +#define RPU_RPU_ERR_INJ_DCCMINP2_SHIFT 8 +#define RPU_RPU_ERR_INJ_DCCMINP2_WIDTH 8 +#define RPU_RPU_ERR_INJ_DCCMINP2_MASK 0X0000FF00 + +#define RPU_RPU_ERR_INJ_DCCMINP_SHIFT 0 +#define RPU_RPU_ERR_INJ_DCCMINP_WIDTH 8 +#define RPU_RPU_ERR_INJ_DCCMINP_MASK 0X000000FF + +/** + * Register: RPU_RPU_CCF_MASK + */ +#define RPU_RPU_CCF_MASK ( ( RPU_BASEADDR ) + 0X00000024 ) + +#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_SHIFT 7 +#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_WIDTH 1 +#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_MASK 0X00000080 + +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_SHIFT 6 +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_WIDTH 1 +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_MASK 0X00000040 + +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_SHIFT 5 +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_WIDTH 1 +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_MASK 0X00000020 + +#define RPU_RPU_CCF_MASK_ISO_SHIFT 4 +#define RPU_RPU_CCF_MASK_ISO_WIDTH 1 +#define RPU_RPU_CCF_MASK_ISO_MASK 0X00000010 + +#define RPU_RPU_CCF_MASK_PGE_SHIFT 3 +#define RPU_RPU_CCF_MASK_PGE_WIDTH 1 +#define RPU_RPU_CCF_MASK_PGE_MASK 0X00000008 + +#define RPU_RPU_CCF_MASK_R50_DBG_RST_SHIFT 2 +#define RPU_RPU_CCF_MASK_R50_DBG_RST_WIDTH 1 +#define RPU_RPU_CCF_MASK_R50_DBG_RST_MASK 0X00000004 + +#define RPU_RPU_CCF_MASK_R50_RST_SHIFT 1 +#define RPU_RPU_CCF_MASK_R50_RST_WIDTH 1 +#define RPU_RPU_CCF_MASK_R50_RST_MASK 0X00000002 + +#define RPU_RPU_CCF_MASK_PGE_RST_SHIFT 0 +#define RPU_RPU_CCF_MASK_PGE_RST_WIDTH 1 +#define RPU_RPU_CCF_MASK_PGE_RST_MASK 0X00000001 + +/** + * Register: RPU_RPU_INTR_0 + */ +#define RPU_RPU_INTR_0 ( ( RPU_BASEADDR ) + 0X00000028 ) + +#define RPU_RPU_INTR_0_SPI_SHIFT 0 +#define RPU_RPU_INTR_0_SPI_WIDTH 32 +#define RPU_RPU_INTR_0_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_1 + */ +#define RPU_RPU_INTR_1 ( ( RPU_BASEADDR ) + 0X0000002C ) + +#define RPU_RPU_INTR_1_SPI_SHIFT 0 +#define RPU_RPU_INTR_1_SPI_WIDTH 32 +#define RPU_RPU_INTR_1_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_2 + */ +#define RPU_RPU_INTR_2 ( ( RPU_BASEADDR ) + 0X00000030 ) + +#define RPU_RPU_INTR_2_SPI_SHIFT 0 +#define RPU_RPU_INTR_2_SPI_WIDTH 32 +#define RPU_RPU_INTR_2_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_3 + */ +#define RPU_RPU_INTR_3 ( ( RPU_BASEADDR ) + 0X00000034 ) + +#define RPU_RPU_INTR_3_SPI_SHIFT 0 +#define RPU_RPU_INTR_3_SPI_WIDTH 32 +#define RPU_RPU_INTR_3_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_4 + */ +#define RPU_RPU_INTR_4 ( ( RPU_BASEADDR ) + 0X00000038 ) + +#define RPU_RPU_INTR_4_SPI_SHIFT 0 +#define RPU_RPU_INTR_4_SPI_WIDTH 32 +#define RPU_RPU_INTR_4_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_MASK_0 + */ +#define RPU_RPU_INTR_MASK_0 ( ( RPU_BASEADDR ) + 0X00000040 ) + +#define RPU_RPU_INTR_MASK_0_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_0_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_0_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_MASK_1 + */ +#define RPU_RPU_INTR_MASK_1 ( ( RPU_BASEADDR ) + 0X00000044 ) + +#define RPU_RPU_INTR_MASK_1_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_1_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_1_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_MASK_2 + */ +#define RPU_RPU_INTR_MASK_2 ( ( RPU_BASEADDR ) + 0X00000048 ) + +#define RPU_RPU_INTR_MASK_2_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_2_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_2_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_MASK_3 + */ +#define RPU_RPU_INTR_MASK_3 ( ( RPU_BASEADDR ) + 0X0000004C ) + +#define RPU_RPU_INTR_MASK_3_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_3_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_3_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_INTR_MASK_4 + */ +#define RPU_RPU_INTR_MASK_4 ( ( RPU_BASEADDR ) + 0X00000050 ) + +#define RPU_RPU_INTR_MASK_4_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_4_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_4_SPI_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_CCF_VAL + */ +#define RPU_RPU_CCF_VAL ( ( RPU_BASEADDR ) + 0X00000054 ) + +#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_SHIFT 7 +#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_WIDTH 1 +#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_MASK 0X00000080 + +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_SHIFT 6 +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_WIDTH 1 +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_MASK 0X00000040 + +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_SHIFT 5 +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_WIDTH 1 +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_MASK 0X00000020 + +#define RPU_RPU_CCF_VAL_ISO_SHIFT 4 +#define RPU_RPU_CCF_VAL_ISO_WIDTH 1 +#define RPU_RPU_CCF_VAL_ISO_MASK 0X00000010 + +#define RPU_RPU_CCF_VAL_PGE_SHIFT 3 +#define RPU_RPU_CCF_VAL_PGE_WIDTH 1 +#define RPU_RPU_CCF_VAL_PGE_MASK 0X00000008 + +#define RPU_RPU_CCF_VAL_R50_DBG_RST_SHIFT 2 +#define RPU_RPU_CCF_VAL_R50_DBG_RST_WIDTH 1 +#define RPU_RPU_CCF_VAL_R50_DBG_RST_MASK 0X00000004 + +#define RPU_RPU_CCF_VAL_R50_RST_SHIFT 1 +#define RPU_RPU_CCF_VAL_R50_RST_WIDTH 1 +#define RPU_RPU_CCF_VAL_R50_RST_MASK 0X00000002 + +#define RPU_RPU_CCF_VAL_PGE_RST_SHIFT 0 +#define RPU_RPU_CCF_VAL_PGE_RST_WIDTH 1 +#define RPU_RPU_CCF_VAL_PGE_RST_MASK 0X00000001 + +/** + * Register: RPU_RPU_SAFETY_CHK + */ +#define RPU_RPU_SAFETY_CHK ( ( RPU_BASEADDR ) + 0X000000F0 ) + +#define RPU_RPU_SAFETY_CHK_VAL_SHIFT 0 +#define RPU_RPU_SAFETY_CHK_VAL_WIDTH 32 +#define RPU_RPU_SAFETY_CHK_VAL_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU + */ +#define RPU_RPU ( ( RPU_BASEADDR ) + 0X000000F4 ) + +#define RPU_RPU_ECO_SHIFT 0 +#define RPU_RPU_ECO_WIDTH 32 +#define RPU_RPU_ECO_MASK 0XFFFFFFFF + +/** + * Register: RPU_RPU_0_CFG + */ +#define RPU_RPU_0_CFG ( ( RPU_BASEADDR ) + 0X00000100 ) + +#define RPU_RPU_0_CFG_CFGNMFI0_SHIFT 3 +#define RPU_RPU_0_CFG_CFGNMFI0_WIDTH 1 +#define RPU_RPU_0_CFG_CFGNMFI0_MASK 0X00000008 + +#define RPU_RPU_0_CFG_VINITHI_SHIFT 2 +#define RPU_RPU_0_CFG_VINITHI_WIDTH 1 +#define RPU_RPU_0_CFG_VINITHI_MASK 0X00000004 + +#define RPU_RPU_0_CFG_COHERENT_SHIFT 1 +#define RPU_RPU_0_CFG_COHERENT_WIDTH 1 +#define RPU_RPU_0_CFG_COHERENT_MASK 0X00000002 + +#define RPU_RPU_0_CFG_NCPUHALT_SHIFT 0 +#define RPU_RPU_0_CFG_NCPUHALT_WIDTH 1 +#define RPU_RPU_0_CFG_NCPUHALT_MASK 0X00000001 + +/** + * Register: RPU_RPU_0_STATUS + */ +#define RPU_RPU_0_STATUS ( ( RPU_BASEADDR ) + 0X00000104 ) + +#define RPU_RPU_0_STATUS_NVALRESET_SHIFT 5 +#define RPU_RPU_0_STATUS_NVALRESET_WIDTH 1 +#define RPU_RPU_0_STATUS_NVALRESET_MASK 0X00000020 + +#define RPU_RPU_0_STATUS_NVALIRQ_SHIFT 4 +#define RPU_RPU_0_STATUS_NVALIRQ_WIDTH 1 +#define RPU_RPU_0_STATUS_NVALIRQ_MASK 0X00000010 + +#define RPU_RPU_0_STATUS_NVALFIQ_SHIFT 3 +#define RPU_RPU_0_STATUS_NVALFIQ_WIDTH 1 +#define RPU_RPU_0_STATUS_NVALFIQ_MASK 0X00000008 + +#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_SHIFT 2 +#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_WIDTH 1 +#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_MASK 0X00000004 + +#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_SHIFT 1 +#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_WIDTH 1 +#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_MASK 0X00000002 + +#define RPU_RPU_0_STATUS_NCLKSTOPPED_SHIFT 0 +#define RPU_RPU_0_STATUS_NCLKSTOPPED_WIDTH 1 +#define RPU_RPU_0_STATUS_NCLKSTOPPED_MASK 0X00000001 + +/** + * Register: RPU_RPU_0_PWRDWN + */ +#define RPU_RPU_0_PWRDWN ( ( RPU_BASEADDR ) + 0X00000108 ) + +#define RPU_RPU_0_PWRDWN_EN_SHIFT 0 +#define RPU_RPU_0_PWRDWN_EN_WIDTH 1 +#define RPU_RPU_0_PWRDWN_EN_MASK 0X00000001 + +/** + * Register: RPU_RPU_0_ISR + */ +#define RPU_RPU_0_ISR ( ( RPU_BASEADDR ) + 0X00000114 ) + +#define RPU_RPU_0_ISR_FPUFC_SHIFT 24 +#define RPU_RPU_0_ISR_FPUFC_WIDTH 1 +#define RPU_RPU_0_ISR_FPUFC_MASK 0X01000000 + +#define RPU_RPU_0_ISR_FPOFC_SHIFT 23 +#define RPU_RPU_0_ISR_FPOFC_WIDTH 1 +#define RPU_RPU_0_ISR_FPOFC_MASK 0X00800000 + +#define RPU_RPU_0_ISR_FPIXC_SHIFT 22 +#define RPU_RPU_0_ISR_FPIXC_WIDTH 1 +#define RPU_RPU_0_ISR_FPIXC_MASK 0X00400000 + +#define RPU_RPU_0_ISR_FPIOC_SHIFT 21 +#define RPU_RPU_0_ISR_FPIOC_WIDTH 1 +#define RPU_RPU_0_ISR_FPIOC_MASK 0X00200000 + +#define RPU_RPU_0_ISR_FPIDC_SHIFT 20 +#define RPU_RPU_0_ISR_FPIDC_WIDTH 1 +#define RPU_RPU_0_ISR_FPIDC_MASK 0X00100000 + +#define RPU_RPU_0_ISR_FPDZC_SHIFT 19 +#define RPU_RPU_0_ISR_FPDZC_WIDTH 1 +#define RPU_RPU_0_ISR_FPDZC_MASK 0X00080000 + +#define RPU_RPU_0_ISR_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_0_ISR_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_ASLV_CE_MASK 0X00040000 + +#define RPU_RPU_0_ISR_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_0_ISR_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_ASLV_FAT_MASK 0X00020000 + +#define RPU_RPU_0_ISR_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_0_ISR_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_LST_CE_MASK 0X00010000 + +#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_MASK 0X00008000 + +#define RPU_RPU_0_ISR_B1TCM_CE_SHIFT 14 +#define RPU_RPU_0_ISR_B1TCM_CE_WIDTH 1 +#define RPU_RPU_0_ISR_B1TCM_CE_MASK 0X00004000 + +#define RPU_RPU_0_ISR_B0TCM_CE_SHIFT 13 +#define RPU_RPU_0_ISR_B0TCM_CE_WIDTH 1 +#define RPU_RPU_0_ISR_B0TCM_CE_MASK 0X00002000 + +#define RPU_RPU_0_ISR_ATCM_CE_SHIFT 12 +#define RPU_RPU_0_ISR_ATCM_CE_WIDTH 1 +#define RPU_RPU_0_ISR_ATCM_CE_MASK 0X00001000 + +#define RPU_RPU_0_ISR_B1TCM_UE_SHIFT 11 +#define RPU_RPU_0_ISR_B1TCM_UE_WIDTH 1 +#define RPU_RPU_0_ISR_B1TCM_UE_MASK 0X00000800 + +#define RPU_RPU_0_ISR_B0TCM_UE_SHIFT 10 +#define RPU_RPU_0_ISR_B0TCM_UE_WIDTH 1 +#define RPU_RPU_0_ISR_B0TCM_UE_MASK 0X00000400 + +#define RPU_RPU_0_ISR_ATCM_UE_SHIFT 9 +#define RPU_RPU_0_ISR_ATCM_UE_WIDTH 1 +#define RPU_RPU_0_ISR_ATCM_UE_MASK 0X00000200 + +#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_MASK 0X00000100 + +#define RPU_RPU_0_ISR_DDATA_FAT_SHIFT 7 +#define RPU_RPU_0_ISR_DDATA_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_DDATA_FAT_MASK 0X00000080 + +#define RPU_RPU_0_ISR_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_0_ISR_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_LST_FAT_MASK 0X00000040 + +#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_MASK 0X00000020 + +#define RPU_RPU_0_ISR_DDATA_CE_SHIFT 4 +#define RPU_RPU_0_ISR_DDATA_CE_WIDTH 1 +#define RPU_RPU_0_ISR_DDATA_CE_MASK 0X00000010 + +#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_MASK 0X00000008 + +#define RPU_RPU_0_ISR_IDATA_CE_SHIFT 2 +#define RPU_RPU_0_ISR_IDATA_CE_WIDTH 1 +#define RPU_RPU_0_ISR_IDATA_CE_MASK 0X00000004 + +#define RPU_RPU_0_ISR_ITAG_CE_SHIFT 1 +#define RPU_RPU_0_ISR_ITAG_CE_WIDTH 1 +#define RPU_RPU_0_ISR_ITAG_CE_MASK 0X00000002 + +#define RPU_RPU_0_ISR_APB_ERR_SHIFT 0 +#define RPU_RPU_0_ISR_APB_ERR_WIDTH 1 +#define RPU_RPU_0_ISR_APB_ERR_MASK 0X00000001 + +/** + * Register: RPU_RPU_0_IMR + */ +#define RPU_RPU_0_IMR ( ( RPU_BASEADDR ) + 0X00000118 ) + +#define RPU_RPU_0_IMR_FPUFC_SHIFT 24 +#define RPU_RPU_0_IMR_FPUFC_WIDTH 1 +#define RPU_RPU_0_IMR_FPUFC_MASK 0X01000000 + +#define RPU_RPU_0_IMR_FPOFC_SHIFT 23 +#define RPU_RPU_0_IMR_FPOFC_WIDTH 1 +#define RPU_RPU_0_IMR_FPOFC_MASK 0X00800000 + +#define RPU_RPU_0_IMR_FPIXC_SHIFT 22 +#define RPU_RPU_0_IMR_FPIXC_WIDTH 1 +#define RPU_RPU_0_IMR_FPIXC_MASK 0X00400000 + +#define RPU_RPU_0_IMR_FPIOC_SHIFT 21 +#define RPU_RPU_0_IMR_FPIOC_WIDTH 1 +#define RPU_RPU_0_IMR_FPIOC_MASK 0X00200000 + +#define RPU_RPU_0_IMR_FPIDC_SHIFT 20 +#define RPU_RPU_0_IMR_FPIDC_WIDTH 1 +#define RPU_RPU_0_IMR_FPIDC_MASK 0X00100000 + +#define RPU_RPU_0_IMR_FPDZC_SHIFT 19 +#define RPU_RPU_0_IMR_FPDZC_WIDTH 1 +#define RPU_RPU_0_IMR_FPDZC_MASK 0X00080000 + +#define RPU_RPU_0_IMR_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_0_IMR_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_ASLV_CE_MASK 0X00040000 + +#define RPU_RPU_0_IMR_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_0_IMR_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_ASLV_FAT_MASK 0X00020000 + +#define RPU_RPU_0_IMR_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_0_IMR_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_LST_CE_MASK 0X00010000 + +#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_MASK 0X00008000 + +#define RPU_RPU_0_IMR_B1TCM_CE_SHIFT 14 +#define RPU_RPU_0_IMR_B1TCM_CE_WIDTH 1 +#define RPU_RPU_0_IMR_B1TCM_CE_MASK 0X00004000 + +#define RPU_RPU_0_IMR_B0TCM_CE_SHIFT 13 +#define RPU_RPU_0_IMR_B0TCM_CE_WIDTH 1 +#define RPU_RPU_0_IMR_B0TCM_CE_MASK 0X00002000 + +#define RPU_RPU_0_IMR_ATCM_CE_SHIFT 12 +#define RPU_RPU_0_IMR_ATCM_CE_WIDTH 1 +#define RPU_RPU_0_IMR_ATCM_CE_MASK 0X00001000 + +#define RPU_RPU_0_IMR_B1TCM_UE_SHIFT 11 +#define RPU_RPU_0_IMR_B1TCM_UE_WIDTH 1 +#define RPU_RPU_0_IMR_B1TCM_UE_MASK 0X00000800 + +#define RPU_RPU_0_IMR_B0TCM_UE_SHIFT 10 +#define RPU_RPU_0_IMR_B0TCM_UE_WIDTH 1 +#define RPU_RPU_0_IMR_B0TCM_UE_MASK 0X00000400 + +#define RPU_RPU_0_IMR_ATCM_UE_SHIFT 9 +#define RPU_RPU_0_IMR_ATCM_UE_WIDTH 1 +#define RPU_RPU_0_IMR_ATCM_UE_MASK 0X00000200 + +#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_MASK 0X00000100 + +#define RPU_RPU_0_IMR_DDATA_FAT_SHIFT 7 +#define RPU_RPU_0_IMR_DDATA_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_DDATA_FAT_MASK 0X00000080 + +#define RPU_RPU_0_IMR_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_0_IMR_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_LST_FAT_MASK 0X00000040 + +#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_MASK 0X00000020 + +#define RPU_RPU_0_IMR_DDATA_CE_SHIFT 4 +#define RPU_RPU_0_IMR_DDATA_CE_WIDTH 1 +#define RPU_RPU_0_IMR_DDATA_CE_MASK 0X00000010 + +#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_MASK 0X00000008 + +#define RPU_RPU_0_IMR_IDATA_CE_SHIFT 2 +#define RPU_RPU_0_IMR_IDATA_CE_WIDTH 1 +#define RPU_RPU_0_IMR_IDATA_CE_MASK 0X00000004 + +#define RPU_RPU_0_IMR_ITAG_CE_SHIFT 1 +#define RPU_RPU_0_IMR_ITAG_CE_WIDTH 1 +#define RPU_RPU_0_IMR_ITAG_CE_MASK 0X00000002 + +#define RPU_RPU_0_IMR_APB_ERR_SHIFT 0 +#define RPU_RPU_0_IMR_APB_ERR_WIDTH 1 +#define RPU_RPU_0_IMR_APB_ERR_MASK 0X00000001 + +/** + * Register: RPU_RPU_0_IEN + */ +#define RPU_RPU_0_IEN ( ( RPU_BASEADDR ) + 0X0000011C ) + +#define RPU_RPU_0_IEN_FPUFC_SHIFT 24 +#define RPU_RPU_0_IEN_FPUFC_WIDTH 1 +#define RPU_RPU_0_IEN_FPUFC_MASK 0X01000000 + +#define RPU_RPU_0_IEN_FPOFC_SHIFT 23 +#define RPU_RPU_0_IEN_FPOFC_WIDTH 1 +#define RPU_RPU_0_IEN_FPOFC_MASK 0X00800000 + +#define RPU_RPU_0_IEN_FPIXC_SHIFT 22 +#define RPU_RPU_0_IEN_FPIXC_WIDTH 1 +#define RPU_RPU_0_IEN_FPIXC_MASK 0X00400000 + +#define RPU_RPU_0_IEN_FPIOC_SHIFT 21 +#define RPU_RPU_0_IEN_FPIOC_WIDTH 1 +#define RPU_RPU_0_IEN_FPIOC_MASK 0X00200000 + +#define RPU_RPU_0_IEN_FPIDC_SHIFT 20 +#define RPU_RPU_0_IEN_FPIDC_WIDTH 1 +#define RPU_RPU_0_IEN_FPIDC_MASK 0X00100000 + +#define RPU_RPU_0_IEN_FPDZC_SHIFT 19 +#define RPU_RPU_0_IEN_FPDZC_WIDTH 1 +#define RPU_RPU_0_IEN_FPDZC_MASK 0X00080000 + +#define RPU_RPU_0_IEN_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_0_IEN_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_ASLV_CE_MASK 0X00040000 + +#define RPU_RPU_0_IEN_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_0_IEN_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_ASLV_FAT_MASK 0X00020000 + +#define RPU_RPU_0_IEN_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_0_IEN_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_LST_CE_MASK 0X00010000 + +#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_MASK 0X00008000 + +#define RPU_RPU_0_IEN_B1TCM_CE_SHIFT 14 +#define RPU_RPU_0_IEN_B1TCM_CE_WIDTH 1 +#define RPU_RPU_0_IEN_B1TCM_CE_MASK 0X00004000 + +#define RPU_RPU_0_IEN_B0TCM_CE_SHIFT 13 +#define RPU_RPU_0_IEN_B0TCM_CE_WIDTH 1 +#define RPU_RPU_0_IEN_B0TCM_CE_MASK 0X00002000 + +#define RPU_RPU_0_IEN_ATCM_CE_SHIFT 12 +#define RPU_RPU_0_IEN_ATCM_CE_WIDTH 1 +#define RPU_RPU_0_IEN_ATCM_CE_MASK 0X00001000 + +#define RPU_RPU_0_IEN_B1TCM_UE_SHIFT 11 +#define RPU_RPU_0_IEN_B1TCM_UE_WIDTH 1 +#define RPU_RPU_0_IEN_B1TCM_UE_MASK 0X00000800 + +#define RPU_RPU_0_IEN_B0TCM_UE_SHIFT 10 +#define RPU_RPU_0_IEN_B0TCM_UE_WIDTH 1 +#define RPU_RPU_0_IEN_B0TCM_UE_MASK 0X00000400 + +#define RPU_RPU_0_IEN_ATCM_UE_SHIFT 9 +#define RPU_RPU_0_IEN_ATCM_UE_WIDTH 1 +#define RPU_RPU_0_IEN_ATCM_UE_MASK 0X00000200 + +#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_MASK 0X00000100 + +#define RPU_RPU_0_IEN_DDATA_FAT_SHIFT 7 +#define RPU_RPU_0_IEN_DDATA_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_DDATA_FAT_MASK 0X00000080 + +#define RPU_RPU_0_IEN_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_0_IEN_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_LST_FAT_MASK 0X00000040 + +#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_MASK 0X00000020 + +#define RPU_RPU_0_IEN_DDATA_CE_SHIFT 4 +#define RPU_RPU_0_IEN_DDATA_CE_WIDTH 1 +#define RPU_RPU_0_IEN_DDATA_CE_MASK 0X00000010 + +#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_MASK 0X00000008 + +#define RPU_RPU_0_IEN_IDATA_CE_SHIFT 2 +#define RPU_RPU_0_IEN_IDATA_CE_WIDTH 1 +#define RPU_RPU_0_IEN_IDATA_CE_MASK 0X00000004 + +#define RPU_RPU_0_IEN_ITAG_CE_SHIFT 1 +#define RPU_RPU_0_IEN_ITAG_CE_WIDTH 1 +#define RPU_RPU_0_IEN_ITAG_CE_MASK 0X00000002 + +#define RPU_RPU_0_IEN_APB_ERR_SHIFT 0 +#define RPU_RPU_0_IEN_APB_ERR_WIDTH 1 +#define RPU_RPU_0_IEN_APB_ERR_MASK 0X00000001 + +/** + * Register: RPU_RPU_0_IDS + */ +#define RPU_RPU_0_IDS ( ( RPU_BASEADDR ) + 0X00000120 ) + +#define RPU_RPU_0_IDS_FPUFC_SHIFT 24 +#define RPU_RPU_0_IDS_FPUFC_WIDTH 1 +#define RPU_RPU_0_IDS_FPUFC_MASK 0X01000000 + +#define RPU_RPU_0_IDS_FPOFC_SHIFT 23 +#define RPU_RPU_0_IDS_FPOFC_WIDTH 1 +#define RPU_RPU_0_IDS_FPOFC_MASK 0X00800000 + +#define RPU_RPU_0_IDS_FPIXC_SHIFT 22 +#define RPU_RPU_0_IDS_FPIXC_WIDTH 1 +#define RPU_RPU_0_IDS_FPIXC_MASK 0X00400000 + +#define RPU_RPU_0_IDS_FPIOC_SHIFT 21 +#define RPU_RPU_0_IDS_FPIOC_WIDTH 1 +#define RPU_RPU_0_IDS_FPIOC_MASK 0X00200000 + +#define RPU_RPU_0_IDS_FPIDC_SHIFT 20 +#define RPU_RPU_0_IDS_FPIDC_WIDTH 1 +#define RPU_RPU_0_IDS_FPIDC_MASK 0X00100000 + +#define RPU_RPU_0_IDS_FPDZC_SHIFT 19 +#define RPU_RPU_0_IDS_FPDZC_WIDTH 1 +#define RPU_RPU_0_IDS_FPDZC_MASK 0X00080000 + +#define RPU_RPU_0_IDS_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_0_IDS_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_ASLV_CE_MASK 0X00040000 + +#define RPU_RPU_0_IDS_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_0_IDS_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_ASLV_FAT_MASK 0X00020000 + +#define RPU_RPU_0_IDS_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_0_IDS_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_LST_CE_MASK 0X00010000 + +#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_MASK 0X00008000 + +#define RPU_RPU_0_IDS_B1TCM_CE_SHIFT 14 +#define RPU_RPU_0_IDS_B1TCM_CE_WIDTH 1 +#define RPU_RPU_0_IDS_B1TCM_CE_MASK 0X00004000 + +#define RPU_RPU_0_IDS_B0TCM_CE_SHIFT 13 +#define RPU_RPU_0_IDS_B0TCM_CE_WIDTH 1 +#define RPU_RPU_0_IDS_B0TCM_CE_MASK 0X00002000 + +#define RPU_RPU_0_IDS_ATCM_CE_SHIFT 12 +#define RPU_RPU_0_IDS_ATCM_CE_WIDTH 1 +#define RPU_RPU_0_IDS_ATCM_CE_MASK 0X00001000 + +#define RPU_RPU_0_IDS_B1TCM_UE_SHIFT 11 +#define RPU_RPU_0_IDS_B1TCM_UE_WIDTH 1 +#define RPU_RPU_0_IDS_B1TCM_UE_MASK 0X00000800 + +#define RPU_RPU_0_IDS_B0TCM_UE_SHIFT 10 +#define RPU_RPU_0_IDS_B0TCM_UE_WIDTH 1 +#define RPU_RPU_0_IDS_B0TCM_UE_MASK 0X00000400 + +#define RPU_RPU_0_IDS_ATCM_UE_SHIFT 9 +#define RPU_RPU_0_IDS_ATCM_UE_WIDTH 1 +#define RPU_RPU_0_IDS_ATCM_UE_MASK 0X00000200 + +#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_MASK 0X00000100 + +#define RPU_RPU_0_IDS_DDATA_FAT_SHIFT 7 +#define RPU_RPU_0_IDS_DDATA_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_DDATA_FAT_MASK 0X00000080 + +#define RPU_RPU_0_IDS_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_0_IDS_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_LST_FAT_MASK 0X00000040 + +#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_MASK 0X00000020 + +#define RPU_RPU_0_IDS_DDATA_CE_SHIFT 4 +#define RPU_RPU_0_IDS_DDATA_CE_WIDTH 1 +#define RPU_RPU_0_IDS_DDATA_CE_MASK 0X00000010 + +#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_MASK 0X00000008 + +#define RPU_RPU_0_IDS_IDATA_CE_SHIFT 2 +#define RPU_RPU_0_IDS_IDATA_CE_WIDTH 1 +#define RPU_RPU_0_IDS_IDATA_CE_MASK 0X00000004 + +#define RPU_RPU_0_IDS_ITAG_CE_SHIFT 1 +#define RPU_RPU_0_IDS_ITAG_CE_WIDTH 1 +#define RPU_RPU_0_IDS_ITAG_CE_MASK 0X00000002 + +#define RPU_RPU_0_IDS_APB_ERR_SHIFT 0 +#define RPU_RPU_0_IDS_APB_ERR_WIDTH 1 +#define RPU_RPU_0_IDS_APB_ERR_MASK 0X00000001 + +/** + * Register: RPU_RPU_0_SLV_BASE + */ +#define RPU_RPU_0_SLV_BASE ( ( RPU_BASEADDR ) + 0X00000124 ) + +#define RPU_RPU_0_SLV_BASE_ADDR_SHIFT 0 +#define RPU_RPU_0_SLV_BASE_ADDR_WIDTH 8 +#define RPU_RPU_0_SLV_BASE_ADDR_MASK 0X000000FF + +/** + * Register: RPU_RPU_0_AXI_OVER + */ +#define RPU_RPU_0_AXI_OVER ( ( RPU_BASEADDR ) + 0X00000128 ) + +#define RPU_RPU_0_AXI_OVER_AWCACHE_SHIFT 6 +#define RPU_RPU_0_AXI_OVER_AWCACHE_WIDTH 4 +#define RPU_RPU_0_AXI_OVER_AWCACHE_MASK 0X000003C0 + +#define RPU_RPU_0_AXI_OVER_ARCACHE_SHIFT 2 +#define RPU_RPU_0_AXI_OVER_ARCACHE_WIDTH 4 +#define RPU_RPU_0_AXI_OVER_ARCACHE_MASK 0X0000003C + +#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_SHIFT 1 +#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_WIDTH 1 +#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_MASK 0X00000002 + +#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_SHIFT 0 +#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_WIDTH 1 +#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_MASK 0X00000001 + +/** + * Register: RPU_RPU_1_CFG + */ +#define RPU_RPU_1_CFG ( ( RPU_BASEADDR ) + 0X00000200 ) + +#define RPU_RPU_1_CFG_CFGNMFI1_SHIFT 3 +#define RPU_RPU_1_CFG_CFGNMFI1_WIDTH 1 +#define RPU_RPU_1_CFG_CFGNMFI1_MASK 0X00000008 + +#define RPU_RPU_1_CFG_VINITHI_SHIFT 2 +#define RPU_RPU_1_CFG_VINITHI_WIDTH 1 +#define RPU_RPU_1_CFG_VINITHI_MASK 0X00000004 + +#define RPU_RPU_1_CFG_COHERENT_SHIFT 1 +#define RPU_RPU_1_CFG_COHERENT_WIDTH 1 +#define RPU_RPU_1_CFG_COHERENT_MASK 0X00000002 + +#define RPU_RPU_1_CFG_NCPUHALT_SHIFT 0 +#define RPU_RPU_1_CFG_NCPUHALT_WIDTH 1 +#define RPU_RPU_1_CFG_NCPUHALT_MASK 0X00000001 + +/** + * Register: RPU_RPU_1_STATUS + */ +#define RPU_RPU_1_STATUS ( ( RPU_BASEADDR ) + 0X00000204 ) + +#define RPU_RPU_1_STATUS_NVALRESET_SHIFT 5 +#define RPU_RPU_1_STATUS_NVALRESET_WIDTH 1 +#define RPU_RPU_1_STATUS_NVALRESET_MASK 0X00000020 + +#define RPU_RPU_1_STATUS_NVALIRQ_SHIFT 4 +#define RPU_RPU_1_STATUS_NVALIRQ_WIDTH 1 +#define RPU_RPU_1_STATUS_NVALIRQ_MASK 0X00000010 + +#define RPU_RPU_1_STATUS_NVALFIQ_SHIFT 3 +#define RPU_RPU_1_STATUS_NVALFIQ_WIDTH 1 +#define RPU_RPU_1_STATUS_NVALFIQ_MASK 0X00000008 + +#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_SHIFT 2 +#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_WIDTH 1 +#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_MASK 0X00000004 + +#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_SHIFT 1 +#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_WIDTH 1 +#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_MASK 0X00000002 + +#define RPU_RPU_1_STATUS_NCLKSTOPPED_SHIFT 0 +#define RPU_RPU_1_STATUS_NCLKSTOPPED_WIDTH 1 +#define RPU_RPU_1_STATUS_NCLKSTOPPED_MASK 0X00000001 + +/** + * Register: RPU_RPU_1_PWRDWN + */ +#define RPU_RPU_1_PWRDWN ( ( RPU_BASEADDR ) + 0X00000208 ) + +#define RPU_RPU_1_PWRDWN_EN_SHIFT 0 +#define RPU_RPU_1_PWRDWN_EN_WIDTH 1 +#define RPU_RPU_1_PWRDWN_EN_MASK 0X00000001 + +/** + * Register: RPU_RPU_1_ISR + */ +#define RPU_RPU_1_ISR ( ( RPU_BASEADDR ) + 0X00000214 ) + +#define RPU_RPU_1_ISR_FPUFC_SHIFT 24 +#define RPU_RPU_1_ISR_FPUFC_WIDTH 1 +#define RPU_RPU_1_ISR_FPUFC_MASK 0X01000000 + +#define RPU_RPU_1_ISR_FPOFC_SHIFT 23 +#define RPU_RPU_1_ISR_FPOFC_WIDTH 1 +#define RPU_RPU_1_ISR_FPOFC_MASK 0X00800000 + +#define RPU_RPU_1_ISR_FPIXC_SHIFT 22 +#define RPU_RPU_1_ISR_FPIXC_WIDTH 1 +#define RPU_RPU_1_ISR_FPIXC_MASK 0X00400000 + +#define RPU_RPU_1_ISR_FPIOC_SHIFT 21 +#define RPU_RPU_1_ISR_FPIOC_WIDTH 1 +#define RPU_RPU_1_ISR_FPIOC_MASK 0X00200000 + +#define RPU_RPU_1_ISR_FPIDC_SHIFT 20 +#define RPU_RPU_1_ISR_FPIDC_WIDTH 1 +#define RPU_RPU_1_ISR_FPIDC_MASK 0X00100000 + +#define RPU_RPU_1_ISR_FPDZC_SHIFT 19 +#define RPU_RPU_1_ISR_FPDZC_WIDTH 1 +#define RPU_RPU_1_ISR_FPDZC_MASK 0X00080000 + +#define RPU_RPU_1_ISR_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_1_ISR_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_ASLV_CE_MASK 0X00040000 + +#define RPU_RPU_1_ISR_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_1_ISR_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_ASLV_FAT_MASK 0X00020000 + +#define RPU_RPU_1_ISR_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_1_ISR_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_LST_CE_MASK 0X00010000 + +#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_MASK 0X00008000 + +#define RPU_RPU_1_ISR_B1TCM_CE_SHIFT 14 +#define RPU_RPU_1_ISR_B1TCM_CE_WIDTH 1 +#define RPU_RPU_1_ISR_B1TCM_CE_MASK 0X00004000 + +#define RPU_RPU_1_ISR_B0TCM_CE_SHIFT 13 +#define RPU_RPU_1_ISR_B0TCM_CE_WIDTH 1 +#define RPU_RPU_1_ISR_B0TCM_CE_MASK 0X00002000 + +#define RPU_RPU_1_ISR_ATCM_CE_SHIFT 12 +#define RPU_RPU_1_ISR_ATCM_CE_WIDTH 1 +#define RPU_RPU_1_ISR_ATCM_CE_MASK 0X00001000 + +#define RPU_RPU_1_ISR_B1TCM_UE_SHIFT 11 +#define RPU_RPU_1_ISR_B1TCM_UE_WIDTH 1 +#define RPU_RPU_1_ISR_B1TCM_UE_MASK 0X00000800 + +#define RPU_RPU_1_ISR_B0TCM_UE_SHIFT 10 +#define RPU_RPU_1_ISR_B0TCM_UE_WIDTH 1 +#define RPU_RPU_1_ISR_B0TCM_UE_MASK 0X00000400 + +#define RPU_RPU_1_ISR_ATCM_UE_SHIFT 9 +#define RPU_RPU_1_ISR_ATCM_UE_WIDTH 1 +#define RPU_RPU_1_ISR_ATCM_UE_MASK 0X00000200 + +#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_MASK 0X00000100 + +#define RPU_RPU_1_ISR_DDATA_FAT_SHIFT 7 +#define RPU_RPU_1_ISR_DDATA_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_DDATA_FAT_MASK 0X00000080 + +#define RPU_RPU_1_ISR_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_1_ISR_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_LST_FAT_MASK 0X00000040 + +#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_MASK 0X00000020 + +#define RPU_RPU_1_ISR_DDATA_CE_SHIFT 4 +#define RPU_RPU_1_ISR_DDATA_CE_WIDTH 1 +#define RPU_RPU_1_ISR_DDATA_CE_MASK 0X00000010 + +#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_MASK 0X00000008 + +#define RPU_RPU_1_ISR_IDATA_CE_SHIFT 2 +#define RPU_RPU_1_ISR_IDATA_CE_WIDTH 1 +#define RPU_RPU_1_ISR_IDATA_CE_MASK 0X00000004 + +#define RPU_RPU_1_ISR_ITAG_CE_SHIFT 1 +#define RPU_RPU_1_ISR_ITAG_CE_WIDTH 1 +#define RPU_RPU_1_ISR_ITAG_CE_MASK 0X00000002 + +#define RPU_RPU_1_ISR_APB_ERR_SHIFT 0 +#define RPU_RPU_1_ISR_APB_ERR_WIDTH 1 +#define RPU_RPU_1_ISR_APB_ERR_MASK 0X00000001 + +/** + * Register: RPU_RPU_1_IMR + */ +#define RPU_RPU_1_IMR ( ( RPU_BASEADDR ) + 0X00000218 ) + +#define RPU_RPU_1_IMR_FPUFC_SHIFT 24 +#define RPU_RPU_1_IMR_FPUFC_WIDTH 1 +#define RPU_RPU_1_IMR_FPUFC_MASK 0X01000000 + +#define RPU_RPU_1_IMR_FPOFC_SHIFT 23 +#define RPU_RPU_1_IMR_FPOFC_WIDTH 1 +#define RPU_RPU_1_IMR_FPOFC_MASK 0X00800000 + +#define RPU_RPU_1_IMR_FPIXC_SHIFT 22 +#define RPU_RPU_1_IMR_FPIXC_WIDTH 1 +#define RPU_RPU_1_IMR_FPIXC_MASK 0X00400000 + +#define RPU_RPU_1_IMR_FPIOC_SHIFT 21 +#define RPU_RPU_1_IMR_FPIOC_WIDTH 1 +#define RPU_RPU_1_IMR_FPIOC_MASK 0X00200000 + +#define RPU_RPU_1_IMR_FPIDC_SHIFT 20 +#define RPU_RPU_1_IMR_FPIDC_WIDTH 1 +#define RPU_RPU_1_IMR_FPIDC_MASK 0X00100000 + +#define RPU_RPU_1_IMR_FPDZC_SHIFT 19 +#define RPU_RPU_1_IMR_FPDZC_WIDTH 1 +#define RPU_RPU_1_IMR_FPDZC_MASK 0X00080000 + +#define RPU_RPU_1_IMR_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_1_IMR_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_ASLV_CE_MASK 0X00040000 + +#define RPU_RPU_1_IMR_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_1_IMR_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_ASLV_FAT_MASK 0X00020000 + +#define RPU_RPU_1_IMR_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_1_IMR_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_LST_CE_MASK 0X00010000 + +#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_MASK 0X00008000 + +#define RPU_RPU_1_IMR_B1TCM_CE_SHIFT 14 +#define RPU_RPU_1_IMR_B1TCM_CE_WIDTH 1 +#define RPU_RPU_1_IMR_B1TCM_CE_MASK 0X00004000 + +#define RPU_RPU_1_IMR_B0TCM_CE_SHIFT 13 +#define RPU_RPU_1_IMR_B0TCM_CE_WIDTH 1 +#define RPU_RPU_1_IMR_B0TCM_CE_MASK 0X00002000 + +#define RPU_RPU_1_IMR_ATCM_CE_SHIFT 12 +#define RPU_RPU_1_IMR_ATCM_CE_WIDTH 1 +#define RPU_RPU_1_IMR_ATCM_CE_MASK 0X00001000 + +#define RPU_RPU_1_IMR_B1TCM_UE_SHIFT 11 +#define RPU_RPU_1_IMR_B1TCM_UE_WIDTH 1 +#define RPU_RPU_1_IMR_B1TCM_UE_MASK 0X00000800 + +#define RPU_RPU_1_IMR_B0TCM_UE_SHIFT 10 +#define RPU_RPU_1_IMR_B0TCM_UE_WIDTH 1 +#define RPU_RPU_1_IMR_B0TCM_UE_MASK 0X00000400 + +#define RPU_RPU_1_IMR_ATCM_UE_SHIFT 9 +#define RPU_RPU_1_IMR_ATCM_UE_WIDTH 1 +#define RPU_RPU_1_IMR_ATCM_UE_MASK 0X00000200 + +#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_MASK 0X00000100 + +#define RPU_RPU_1_IMR_DDATA_FAT_SHIFT 7 +#define RPU_RPU_1_IMR_DDATA_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_DDATA_FAT_MASK 0X00000080 + +#define RPU_RPU_1_IMR_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_1_IMR_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_LST_FAT_MASK 0X00000040 + +#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_MASK 0X00000020 + +#define RPU_RPU_1_IMR_DDATA_CE_SHIFT 4 +#define RPU_RPU_1_IMR_DDATA_CE_WIDTH 1 +#define RPU_RPU_1_IMR_DDATA_CE_MASK 0X00000010 + +#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_MASK 0X00000008 + +#define RPU_RPU_1_IMR_IDATA_CE_SHIFT 2 +#define RPU_RPU_1_IMR_IDATA_CE_WIDTH 1 +#define RPU_RPU_1_IMR_IDATA_CE_MASK 0X00000004 + +#define RPU_RPU_1_IMR_ITAG_CE_SHIFT 1 +#define RPU_RPU_1_IMR_ITAG_CE_WIDTH 1 +#define RPU_RPU_1_IMR_ITAG_CE_MASK 0X00000002 + +#define RPU_RPU_1_IMR_APB_ERR_SHIFT 0 +#define RPU_RPU_1_IMR_APB_ERR_WIDTH 1 +#define RPU_RPU_1_IMR_APB_ERR_MASK 0X00000001 + +/** + * Register: RPU_RPU_1_IEN + */ +#define RPU_RPU_1_IEN ( ( RPU_BASEADDR ) + 0X0000021C ) + +#define RPU_RPU_1_IEN_FPUFC_SHIFT 24 +#define RPU_RPU_1_IEN_FPUFC_WIDTH 1 +#define RPU_RPU_1_IEN_FPUFC_MASK 0X01000000 + +#define RPU_RPU_1_IEN_FPOFC_SHIFT 23 +#define RPU_RPU_1_IEN_FPOFC_WIDTH 1 +#define RPU_RPU_1_IEN_FPOFC_MASK 0X00800000 + +#define RPU_RPU_1_IEN_FPIXC_SHIFT 22 +#define RPU_RPU_1_IEN_FPIXC_WIDTH 1 +#define RPU_RPU_1_IEN_FPIXC_MASK 0X00400000 + +#define RPU_RPU_1_IEN_FPIOC_SHIFT 21 +#define RPU_RPU_1_IEN_FPIOC_WIDTH 1 +#define RPU_RPU_1_IEN_FPIOC_MASK 0X00200000 + +#define RPU_RPU_1_IEN_FPIDC_SHIFT 20 +#define RPU_RPU_1_IEN_FPIDC_WIDTH 1 +#define RPU_RPU_1_IEN_FPIDC_MASK 0X00100000 + +#define RPU_RPU_1_IEN_FPDZC_SHIFT 19 +#define RPU_RPU_1_IEN_FPDZC_WIDTH 1 +#define RPU_RPU_1_IEN_FPDZC_MASK 0X00080000 + +#define RPU_RPU_1_IEN_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_1_IEN_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_ASLV_CE_MASK 0X00040000 + +#define RPU_RPU_1_IEN_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_1_IEN_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_ASLV_FAT_MASK 0X00020000 + +#define RPU_RPU_1_IEN_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_1_IEN_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_LST_CE_MASK 0X00010000 + +#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_MASK 0X00008000 + +#define RPU_RPU_1_IEN_B1TCM_CE_SHIFT 14 +#define RPU_RPU_1_IEN_B1TCM_CE_WIDTH 1 +#define RPU_RPU_1_IEN_B1TCM_CE_MASK 0X00004000 + +#define RPU_RPU_1_IEN_B0TCM_CE_SHIFT 13 +#define RPU_RPU_1_IEN_B0TCM_CE_WIDTH 1 +#define RPU_RPU_1_IEN_B0TCM_CE_MASK 0X00002000 + +#define RPU_RPU_1_IEN_ATCM_CE_SHIFT 12 +#define RPU_RPU_1_IEN_ATCM_CE_WIDTH 1 +#define RPU_RPU_1_IEN_ATCM_CE_MASK 0X00001000 + +#define RPU_RPU_1_IEN_B1TCM_UE_SHIFT 11 +#define RPU_RPU_1_IEN_B1TCM_UE_WIDTH 1 +#define RPU_RPU_1_IEN_B1TCM_UE_MASK 0X00000800 + +#define RPU_RPU_1_IEN_B0TCM_UE_SHIFT 10 +#define RPU_RPU_1_IEN_B0TCM_UE_WIDTH 1 +#define RPU_RPU_1_IEN_B0TCM_UE_MASK 0X00000400 + +#define RPU_RPU_1_IEN_ATCM_UE_SHIFT 9 +#define RPU_RPU_1_IEN_ATCM_UE_WIDTH 1 +#define RPU_RPU_1_IEN_ATCM_UE_MASK 0X00000200 + +#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_MASK 0X00000100 + +#define RPU_RPU_1_IEN_DDATA_FAT_SHIFT 7 +#define RPU_RPU_1_IEN_DDATA_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_DDATA_FAT_MASK 0X00000080 + +#define RPU_RPU_1_IEN_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_1_IEN_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_LST_FAT_MASK 0X00000040 + +#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_MASK 0X00000020 + +#define RPU_RPU_1_IEN_DDATA_CE_SHIFT 4 +#define RPU_RPU_1_IEN_DDATA_CE_WIDTH 1 +#define RPU_RPU_1_IEN_DDATA_CE_MASK 0X00000010 + +#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_MASK 0X00000008 + +#define RPU_RPU_1_IEN_IDATA_CE_SHIFT 2 +#define RPU_RPU_1_IEN_IDATA_CE_WIDTH 1 +#define RPU_RPU_1_IEN_IDATA_CE_MASK 0X00000004 + +#define RPU_RPU_1_IEN_ITAG_CE_SHIFT 1 +#define RPU_RPU_1_IEN_ITAG_CE_WIDTH 1 +#define RPU_RPU_1_IEN_ITAG_CE_MASK 0X00000002 + +#define RPU_RPU_1_IEN_APB_ERR_SHIFT 0 +#define RPU_RPU_1_IEN_APB_ERR_WIDTH 1 +#define RPU_RPU_1_IEN_APB_ERR_MASK 0X00000001 + +/** + * Register: RPU_RPU_1_IDS + */ +#define RPU_RPU_1_IDS ( ( RPU_BASEADDR ) + 0X00000220 ) + +#define RPU_RPU_1_IDS_FPUFC_SHIFT 24 +#define RPU_RPU_1_IDS_FPUFC_WIDTH 1 +#define RPU_RPU_1_IDS_FPUFC_MASK 0X01000000 + +#define RPU_RPU_1_IDS_FPOFC_SHIFT 23 +#define RPU_RPU_1_IDS_FPOFC_WIDTH 1 +#define RPU_RPU_1_IDS_FPOFC_MASK 0X00800000 + +#define RPU_RPU_1_IDS_FPIXC_SHIFT 22 +#define RPU_RPU_1_IDS_FPIXC_WIDTH 1 +#define RPU_RPU_1_IDS_FPIXC_MASK 0X00400000 + +#define RPU_RPU_1_IDS_FPIOC_SHIFT 21 +#define RPU_RPU_1_IDS_FPIOC_WIDTH 1 +#define RPU_RPU_1_IDS_FPIOC_MASK 0X00200000 + +#define RPU_RPU_1_IDS_FPIDC_SHIFT 20 +#define RPU_RPU_1_IDS_FPIDC_WIDTH 1 +#define RPU_RPU_1_IDS_FPIDC_MASK 0X00100000 + +#define RPU_RPU_1_IDS_FPDZC_SHIFT 19 +#define RPU_RPU_1_IDS_FPDZC_WIDTH 1 +#define RPU_RPU_1_IDS_FPDZC_MASK 0X00080000 + +#define RPU_RPU_1_IDS_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_1_IDS_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_ASLV_CE_MASK 0X00040000 + +#define RPU_RPU_1_IDS_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_1_IDS_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_ASLV_FAT_MASK 0X00020000 + +#define RPU_RPU_1_IDS_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_1_IDS_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_LST_CE_MASK 0X00010000 + +#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_MASK 0X00008000 + +#define RPU_RPU_1_IDS_B1TCM_CE_SHIFT 14 +#define RPU_RPU_1_IDS_B1TCM_CE_WIDTH 1 +#define RPU_RPU_1_IDS_B1TCM_CE_MASK 0X00004000 + +#define RPU_RPU_1_IDS_B0TCM_CE_SHIFT 13 +#define RPU_RPU_1_IDS_B0TCM_CE_WIDTH 1 +#define RPU_RPU_1_IDS_B0TCM_CE_MASK 0X00002000 + +#define RPU_RPU_1_IDS_ATCM_CE_SHIFT 12 +#define RPU_RPU_1_IDS_ATCM_CE_WIDTH 1 +#define RPU_RPU_1_IDS_ATCM_CE_MASK 0X00001000 + +#define RPU_RPU_1_IDS_B1TCM_UE_SHIFT 11 +#define RPU_RPU_1_IDS_B1TCM_UE_WIDTH 1 +#define RPU_RPU_1_IDS_B1TCM_UE_MASK 0X00000800 + +#define RPU_RPU_1_IDS_B0TCM_UE_SHIFT 10 +#define RPU_RPU_1_IDS_B0TCM_UE_WIDTH 1 +#define RPU_RPU_1_IDS_B0TCM_UE_MASK 0X00000400 + +#define RPU_RPU_1_IDS_ATCM_UE_SHIFT 9 +#define RPU_RPU_1_IDS_ATCM_UE_WIDTH 1 +#define RPU_RPU_1_IDS_ATCM_UE_MASK 0X00000200 + +#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_MASK 0X00000100 + +#define RPU_RPU_1_IDS_DDATA_FAT_SHIFT 7 +#define RPU_RPU_1_IDS_DDATA_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_DDATA_FAT_MASK 0X00000080 + +#define RPU_RPU_1_IDS_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_1_IDS_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_LST_FAT_MASK 0X00000040 + +#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_MASK 0X00000020 + +#define RPU_RPU_1_IDS_DDATA_CE_SHIFT 4 +#define RPU_RPU_1_IDS_DDATA_CE_WIDTH 1 +#define RPU_RPU_1_IDS_DDATA_CE_MASK 0X00000010 + +#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_MASK 0X00000008 + +#define RPU_RPU_1_IDS_IDATA_CE_SHIFT 2 +#define RPU_RPU_1_IDS_IDATA_CE_WIDTH 1 +#define RPU_RPU_1_IDS_IDATA_CE_MASK 0X00000004 + +#define RPU_RPU_1_IDS_ITAG_CE_SHIFT 1 +#define RPU_RPU_1_IDS_ITAG_CE_WIDTH 1 +#define RPU_RPU_1_IDS_ITAG_CE_MASK 0X00000002 + +#define RPU_RPU_1_IDS_APB_ERR_SHIFT 0 +#define RPU_RPU_1_IDS_APB_ERR_WIDTH 1 +#define RPU_RPU_1_IDS_APB_ERR_MASK 0X00000001 + +/** + * Register: RPU_RPU_1_SLV_BASE + */ +#define RPU_RPU_1_SLV_BASE ( ( RPU_BASEADDR ) + 0X00000224 ) + +#define RPU_RPU_1_SLV_BASE_ADDR_SHIFT 0 +#define RPU_RPU_1_SLV_BASE_ADDR_WIDTH 8 +#define RPU_RPU_1_SLV_BASE_ADDR_MASK 0X000000FF + +/** + * Register: RPU_RPU_1_AXI_OVER + */ +#define RPU_RPU_1_AXI_OVER ( ( RPU_BASEADDR ) + 0X00000228 ) + +#define RPU_RPU_1_AXI_OVER_AWCACHE_SHIFT 6 +#define RPU_RPU_1_AXI_OVER_AWCACHE_WIDTH 4 +#define RPU_RPU_1_AXI_OVER_AWCACHE_MASK 0X000003C0 + +#define RPU_RPU_1_AXI_OVER_ARCACHE_SHIFT 2 +#define RPU_RPU_1_AXI_OVER_ARCACHE_WIDTH 4 +#define RPU_RPU_1_AXI_OVER_ARCACHE_MASK 0X0000003C + +#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_SHIFT 1 +#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_WIDTH 1 +#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_MASK 0X00000002 + +#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_SHIFT 0 +#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_WIDTH 1 +#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_MASK 0X00000001 + +#ifdef __cplusplus +} +#endif + + +#endif /* _PM_RPU_H_ */