diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c
index cd8a4454..f0735ce0 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c
+++ b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c
@@ -380,121 +380,123 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -730,9 +732,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -740,7 +742,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -824,8 +826,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_phy_idle_local_odt = 0x3
     // .. .. ==> 0XF8006048[17:16] = 0x00000003U
     // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
     // .. .. reg_phy_rd_cmd_to_data = 0x0
     // .. .. ==> 0XF8006050[3:0] = 0x00000000U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
@@ -1987,9 +1995,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. reserved_REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -2000,7 +2008,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -3693,8 +3701,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -3787,221 +3793,349 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
     // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -4111,6 +4245,8 @@ unsigned long ps7_post_config_3_0[] = {
     // .. .. FINISH: AFI2 REGISTERS
     // .. .. START: AFI3 REGISTERS
     // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
     // .. FINISH: AFI REGISTERS
     // .. START: LOCK IT BACK
     // .. LOCK_KEY = 0X767B
@@ -4498,121 +4634,123 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -4872,9 +5010,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -4882,7 +5020,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -6269,9 +6407,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -6282,7 +6420,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -7978,8 +8116,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -8078,221 +8214,349 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
     // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -8783,121 +9047,123 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -9157,9 +9423,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -9167,7 +9433,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -12196,8 +12462,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -12296,221 +12560,349 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
     // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -12692,7 +13084,7 @@ ps7GetSiliconVersion () {
 }
 
 void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         *addr = ( val & mask ) | ( *addr & ~mask);
         //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
 }
@@ -12712,7 +13104,7 @@ int mask_poll(unsigned long add , unsigned long mask ) {
 }
 
 unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         unsigned long val = (*addr & mask);
         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
         return val;
diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.c b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.c
index 3e81e5bb..a14e6403 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.c
+++ b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init_gpl.c
@@ -19,13 +19,13 @@
 /****************************************************************************/
 /**
 *
-* @file ps7_init.c
+* @file ps7_init_gpl.c
 *
 * This file is automatically generated 
 *
 *****************************************************************************/
 
-#include "ps7_init.h"
+#include "ps7_init_gpl.h"
 
 unsigned long ps7_pll_init_data_3_0[] = {
     // START: top
@@ -367,121 +367,123 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -717,9 +719,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -727,7 +729,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -811,8 +813,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_phy_idle_local_odt = 0x3
     // .. .. ==> 0XF8006048[17:16] = 0x00000003U
     // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
     // .. .. reg_phy_rd_cmd_to_data = 0x0
     // .. .. ==> 0XF8006050[3:0] = 0x00000000U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
@@ -1974,9 +1982,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. reserved_REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -1987,7 +1995,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -3680,8 +3688,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -3774,221 +3780,349 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
     // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -4098,6 +4232,8 @@ unsigned long ps7_post_config_3_0[] = {
     // .. .. FINISH: AFI2 REGISTERS
     // .. .. START: AFI3 REGISTERS
     // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
     // .. FINISH: AFI REGISTERS
     // .. START: LOCK IT BACK
     // .. LOCK_KEY = 0X767B
@@ -4485,121 +4621,123 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -4859,9 +4997,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -4869,7 +5007,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -6256,9 +6394,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -6269,7 +6407,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -7965,8 +8103,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -8065,221 +8201,349 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
     // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -8770,121 +9034,123 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -9144,9 +9410,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -9154,7 +9420,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -12183,8 +12449,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -12283,221 +12547,349 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. DIRECTION_0 = 0x2880
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_0 = 0x2880
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
     // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -12679,7 +13071,7 @@ ps7GetSiliconVersion () {
 }
 
 void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         *addr = ( val & mask ) | ( *addr & ~mask);
         //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
 }
@@ -12699,7 +13091,7 @@ int mask_poll(unsigned long add , unsigned long mask ) {
 }
 
 unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         unsigned long val = (*addr & mask);
         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
         return val;
diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h b/lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h
index 9e9588e2..f33f1653 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h
+++ b/lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h
@@ -39,6 +39,14 @@
 #define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 23809523
 
 
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
+
+
 /******************************************************************/
 
 /* Definitions for driver DEVCFG */
@@ -144,16 +152,6 @@
 #define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
 
 
-/* Definitions for peripheral PS7_CORESIGHT_COMP_0 */
-#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_BASEADDR 0xF8800000
-#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_HIGHADDR 0xF88FFFFF
-
-
-/* Definitions for peripheral PS7_DDR_0 */
-#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
-#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
-
-
 /* Definitions for peripheral PS7_DDRC_0 */
 #define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
 #define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
@@ -291,8 +289,6 @@
 
 /******************************************************************/
 
-
-/***Definitions for Core_nIRQ/nFIQ interrupts ****/
 /* Definitions for driver SCUGIC */
 #define XPAR_XSCUGIC_NUM_INSTANCES 1
 
@@ -360,6 +356,8 @@
 #define XPAR_PS7_SD_0_BASEADDR 0xE0100000
 #define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
 #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_SD_0_HAS_CD 1
+#define XPAR_PS7_SD_0_HAS_WP 1
 
 
 /******************************************************************/
@@ -369,6 +367,8 @@
 #define XPAR_XSDPS_0_BASEADDR 0xE0100000
 #define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
 
 
 /******************************************************************/
diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c
index 1b4dc657..1af8d3b4 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c
+++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c
@@ -349,121 +349,123 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -699,9 +701,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -709,7 +711,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -793,8 +795,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_phy_idle_local_odt = 0x3
     // .. .. ==> 0XF8006048[17:16] = 0x00000003U
     // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
     // .. .. reg_phy_rd_cmd_to_data = 0x0
     // .. .. ==> 0XF8006050[3:0] = 0x00000000U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
@@ -1956,9 +1964,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. reserved_REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -1969,7 +1977,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -3662,8 +3670,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -3756,221 +3762,349 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -4080,6 +4214,8 @@ unsigned long ps7_post_config_3_0[] = {
     // .. .. FINISH: AFI2 REGISTERS
     // .. .. START: AFI3 REGISTERS
     // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
     // .. FINISH: AFI REGISTERS
     // .. START: LOCK IT BACK
     // .. LOCK_KEY = 0X767B
@@ -4436,121 +4572,123 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -4810,9 +4948,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -4820,7 +4958,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -6207,9 +6345,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -6220,7 +6358,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -7916,8 +8054,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -8016,221 +8152,349 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -8690,121 +8954,123 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -9064,9 +9330,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -9074,7 +9340,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -12103,8 +12369,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -12203,221 +12467,349 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -12599,7 +12991,7 @@ ps7GetSiliconVersion () {
 }
 
 void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         *addr = ( val & mask ) | ( *addr & ~mask);
         //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
 }
@@ -12619,7 +13011,7 @@ int mask_poll(unsigned long add , unsigned long mask ) {
 }
 
 unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         unsigned long val = (*addr & mask);
         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
         return val;
diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.c b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.c
index f5449ed4..749651a5 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.c
+++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.c
@@ -19,13 +19,13 @@
 /****************************************************************************/
 /**
 *
-* @file ps7_init.c
+* @file ps7_init_gpl.c
 *
 * This file is automatically generated 
 *
 *****************************************************************************/
 
-#include "ps7_init.h"
+#include "ps7_init_gpl.h"
 
 unsigned long ps7_pll_init_data_3_0[] = {
     // START: top
@@ -336,121 +336,123 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -686,9 +688,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -696,7 +698,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -780,8 +782,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_phy_idle_local_odt = 0x3
     // .. .. ==> 0XF8006048[17:16] = 0x00000003U
     // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
     // .. .. reg_phy_rd_cmd_to_data = 0x0
     // .. .. ==> 0XF8006050[3:0] = 0x00000000U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
@@ -1943,9 +1951,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. reserved_REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -1956,7 +1964,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -3649,8 +3657,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -3743,221 +3749,349 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -4067,6 +4201,8 @@ unsigned long ps7_post_config_3_0[] = {
     // .. .. FINISH: AFI2 REGISTERS
     // .. .. START: AFI3 REGISTERS
     // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
     // .. FINISH: AFI REGISTERS
     // .. START: LOCK IT BACK
     // .. LOCK_KEY = 0X767B
@@ -4423,121 +4559,123 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -4797,9 +4935,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -4807,7 +4945,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -6194,9 +6332,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -6207,7 +6345,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -7903,8 +8041,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -8003,221 +8139,349 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -8677,121 +8941,123 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -9051,9 +9317,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -9061,7 +9327,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -12090,8 +12356,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -12190,221 +12454,349 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. DIRECTION_1 = 0xc000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. OP_ENABLE_1 = 0xc000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0xc000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
     EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -12586,7 +12978,7 @@ ps7GetSiliconVersion () {
 }
 
 void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         *addr = ( val & mask ) | ( *addr & ~mask);
         //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
 }
@@ -12606,7 +12998,7 @@ int mask_poll(unsigned long add , unsigned long mask ) {
 }
 
 unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         unsigned long val = (*addr & mask);
         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
         return val;
diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h b/lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h
index 73ad834a..a8cb66c1 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h
+++ b/lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h
@@ -18,6 +18,14 @@
 #define STDIN_BASEADDRESS 0xE0001000
 #define STDOUT_BASEADDRESS 0xE0001000
 
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
+
+
 /******************************************************************/
 
 /* Definitions for driver DEVCFG */
@@ -123,16 +131,6 @@
 #define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
 
 
-/* Definitions for peripheral PS7_CORESIGHT_COMP_0 */
-#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_BASEADDR 0xF8800000
-#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_HIGHADDR 0xF88FFFFF
-
-
-/* Definitions for peripheral PS7_DDR_0 */
-#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
-#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
-
-
 /* Definitions for peripheral PS7_DDRC_0 */
 #define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
 #define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
@@ -182,7 +180,7 @@
 
 /* Definitions for peripheral PS7_QSPI_LINEAR_0 */
 #define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFDFFFFFF
 
 
 /* Definitions for peripheral PS7_RAM_0 */
@@ -270,8 +268,6 @@
 
 /******************************************************************/
 
-
-/***Definitions for Core_nIRQ/nFIQ interrupts ****/
 /* Definitions for driver SCUGIC */
 #define XPAR_XSCUGIC_NUM_INSTANCES 1
 
@@ -339,6 +335,8 @@
 #define XPAR_PS7_SD_0_BASEADDR 0xE0100000
 #define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
 #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_SD_0_HAS_CD 1
+#define XPAR_PS7_SD_0_HAS_WP 1
 
 
 /******************************************************************/
@@ -348,6 +346,8 @@
 #define XPAR_XSDPS_0_BASEADDR 0xE0100000
 #define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
 
 
 /******************************************************************/
diff --git a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c
index e7f0900c..b80190cb 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c
+++ b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init.c
@@ -349,121 +349,123 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x7
+    // .. .. ==> 0XF8000180[13:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -699,9 +701,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -709,7 +711,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -793,8 +795,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_phy_idle_local_odt = 0x3
     // .. .. ==> 0XF8006048[17:16] = 0x00000003U
     // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
     // .. .. reg_phy_rd_cmd_to_data = 0x0
     // .. .. ==> 0XF8006050[3:0] = 0x00000000U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
@@ -1948,9 +1956,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. reserved_REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -1961,7 +1969,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -2272,9 +2280,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000720[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
     // .. L1_SEL = 0
     // .. ==> 0XF8000720[2:2] = 0x00000000U
     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
@@ -2297,7 +2305,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF8000720[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000724[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -3463,9 +3471,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007C8[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -3491,10 +3499,10 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF80007C8[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007CC[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -3520,7 +3528,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF80007CC[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF80007D0[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -3654,8 +3662,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -3748,119 +3754,247 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -3970,6 +4104,8 @@ unsigned long ps7_post_config_3_0[] = {
     // .. .. FINISH: AFI2 REGISTERS
     // .. .. START: AFI3 REGISTERS
     // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
     // .. FINISH: AFI REGISTERS
     // .. START: LOCK IT BACK
     // .. LOCK_KEY = 0X767B
@@ -4326,121 +4462,123 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x7
+    // .. .. ==> 0XF8000180[13:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -4700,9 +4838,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -4710,7 +4848,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -6083,9 +6221,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -6096,7 +6234,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -6410,9 +6548,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000720[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
     // .. L1_SEL = 0
     // .. ==> 0XF8000720[2:2] = 0x00000000U
     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
@@ -6435,7 +6573,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF8000720[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000724[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -7601,9 +7739,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007C8[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -7629,10 +7767,10 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF80007C8[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007CC[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -7658,7 +7796,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF80007CC[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF80007D0[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -7792,8 +7930,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -7892,119 +8028,247 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -8464,121 +8728,123 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x7
+    // .. .. ==> 0XF8000180[13:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -8838,9 +9104,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -8848,7 +9114,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -10481,9 +10747,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000720[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
     // .. L1_SEL = 0
     // .. ==> 0XF8000720[2:2] = 0x00000000U
     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
@@ -10506,7 +10772,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // .. ==> 0XF8000720[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000724[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -11672,9 +11938,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007C8[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -11700,10 +11966,10 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // .. ==> 0XF80007C8[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007CC[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -11729,7 +11995,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // .. ==> 0XF80007CC[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF80007D0[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -11863,8 +12129,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -11963,119 +12227,247 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -12257,7 +12649,7 @@ ps7GetSiliconVersion () {
 }
 
 void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         *addr = ( val & mask ) | ( *addr & ~mask);
         //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
 }
@@ -12277,7 +12669,7 @@ int mask_poll(unsigned long add , unsigned long mask ) {
 }
 
 unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         unsigned long val = (*addr & mask);
         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
         return val;
diff --git a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c
index 8b367be6..4ceef4c8 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c
+++ b/lib/sw_apps/zynq_fsbl/misc/zed/ps7_init_gpl.c
@@ -19,13 +19,13 @@
 /****************************************************************************/
 /**
 *
-* @file ps7_init.c
+* @file ps7_init_gpl.c
 *
 * This file is automatically generated 
 *
 *****************************************************************************/
 
-#include "ps7_init.h"
+#include "ps7_init_gpl.h"
 
 unsigned long ps7_pll_init_data_3_0[] = {
     // START: top
@@ -336,121 +336,123 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x7
+    // .. .. ==> 0XF8000180[13:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -686,9 +688,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -696,7 +698,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -780,8 +782,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
     // .. .. reg_phy_idle_local_odt = 0x3
     // .. .. ==> 0XF8006048[17:16] = 0x00000003U
     // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
     // .. .. reg_phy_rd_cmd_to_data = 0x0
     // .. .. ==> 0XF8006050[3:0] = 0x00000000U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
@@ -1935,9 +1943,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. reserved_REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -1948,7 +1956,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -2259,9 +2267,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000720[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
     // .. L1_SEL = 0
     // .. ==> 0XF8000720[2:2] = 0x00000000U
     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
@@ -2284,7 +2292,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF8000720[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000724[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -3450,9 +3458,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007C8[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -3478,10 +3486,10 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF80007C8[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007CC[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -3507,7 +3515,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
     // .. ==> 0XF80007CC[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF80007D0[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -3641,8 +3649,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -3735,119 +3741,247 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -3957,6 +4091,8 @@ unsigned long ps7_post_config_3_0[] = {
     // .. .. FINISH: AFI2 REGISTERS
     // .. .. START: AFI3 REGISTERS
     // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
     // .. FINISH: AFI REGISTERS
     // .. START: LOCK IT BACK
     // .. LOCK_KEY = 0X767B
@@ -4313,121 +4449,123 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x7
+    // .. .. ==> 0XF8000180[13:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -4687,9 +4825,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -4697,7 +4835,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -6070,9 +6208,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. REFIO_EN = 0x1
     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
     // .. REFIO_PULLUP_EN = 0x0
     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
@@ -6083,7 +6221,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
     // .. .. START: ASSERT RESET
     // .. .. RESET = 1
     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
@@ -6397,9 +6535,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000720[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
     // .. L1_SEL = 0
     // .. ==> 0XF8000720[2:2] = 0x00000000U
     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
@@ -6422,7 +6560,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF8000720[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000724[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -7588,9 +7726,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007C8[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -7616,10 +7754,10 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF80007C8[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007CC[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -7645,7 +7783,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
     // .. ==> 0XF80007CC[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF80007D0[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -7779,8 +7917,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -7879,119 +8015,247 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -8451,121 +8715,123 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
     // .. 
     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. ..
     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0xa
+    // .. .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x7
+    // .. .. ==> 0XF8000180[13:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000190[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. ..
     EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. ..
     EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
     // .. START: THIS SHOULD BE BLANK
@@ -8825,9 +9091,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. reg_ddrc_burst_rdwr = 0x4
     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
     // .. .. reg_ddrc_post_cke_x1024 = 0x1
     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
@@ -8835,7 +9101,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
     // .. .. reg_ddrc_force_low_pri_n = 0x0
     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -10468,9 +10734,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000720[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
     // .. L1_SEL = 0
     // .. ==> 0XF8000720[2:2] = 0x00000000U
     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
@@ -10493,7 +10759,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // .. ==> 0XF8000720[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF8000724[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -11659,9 +11925,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
     EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007C8[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -11687,10 +11953,10 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // .. ==> 0XF80007C8[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
     // .. L0_SEL = 0
     // .. ==> 0XF80007CC[1:1] = 0x00000000U
     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
@@ -11716,7 +11982,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
     // .. ==> 0XF80007CC[13:13] = 0x00000000U
     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
     // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
     // .. TRI_ENABLE = 0
     // .. ==> 0XF80007D0[0:0] = 0x00000000U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
@@ -11850,8 +12116,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: TRACE CURRENT PORT SIZE
-    // .. FINISH: TRACE CURRENT PORT SIZE
     // .. START: UART REGISTERS
     // .. BDIV = 0x6
     // .. ==> 0XE0001034[7:0] = 0x00000006U
@@ -11950,119 +12214,247 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. .. START: NOR CS1 BASE ADDRESS
     // .. .. FINISH: NOR CS1 BASE ADDRESS
     // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
     // .. .. FINISH: USB RESET
     // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
     // .. .. FINISH: ENET RESET
     // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. 
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
     EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
     // FINISH: top
     //
@@ -12244,7 +12636,7 @@ ps7GetSiliconVersion () {
 }
 
 void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         *addr = ( val & mask ) | ( *addr & ~mask);
         //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
 }
@@ -12264,7 +12656,7 @@ int mask_poll(unsigned long add , unsigned long mask ) {
 }
 
 unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
+        volatile unsigned long *addr = (volatile unsigned long*) add;
         unsigned long val = (*addr & mask);
         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
         return val;
diff --git a/lib/sw_apps/zynq_fsbl/misc/zed/xparameters.h b/lib/sw_apps/zynq_fsbl/misc/zed/xparameters.h
index def21696..eee86e37 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zed/xparameters.h
+++ b/lib/sw_apps/zynq_fsbl/misc/zed/xparameters.h
@@ -18,6 +18,14 @@
 #define STDIN_BASEADDRESS 0xE0001000
 #define STDOUT_BASEADDRESS 0xE0001000
 
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
+
+
 /******************************************************************/
 
 /* Definitions for driver DEVCFG */
@@ -123,16 +131,6 @@
 #define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
 
 
-/* Definitions for peripheral PS7_CORESIGHT_COMP_0 */
-#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_BASEADDR 0xF8800000
-#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_HIGHADDR 0xF88FFFFF
-
-
-/* Definitions for peripheral PS7_DDR_0 */
-#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
-#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
-
-
 /* Definitions for peripheral PS7_DDRC_0 */
 #define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
 #define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
@@ -249,8 +247,6 @@
 
 /******************************************************************/
 
-
-/***Definitions for Core_nIRQ/nFIQ interrupts ****/
 /* Definitions for driver SCUGIC */
 #define XPAR_XSCUGIC_NUM_INSTANCES 1
 
@@ -318,6 +314,8 @@
 #define XPAR_PS7_SD_0_BASEADDR 0xE0100000
 #define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
 #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_SD_0_HAS_CD 1
+#define XPAR_PS7_SD_0_HAS_WP 1
 
 
 /******************************************************************/
@@ -327,6 +325,8 @@
 #define XPAR_XSDPS_0_BASEADDR 0xE0100000
 #define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
 
 
 /******************************************************************/