diff --git a/ThirdParty/sw_services/xilopenamp/data/xilopenamp.tcl b/ThirdParty/sw_services/xilopenamp/data/xilopenamp.tcl index 1675884c..0cb08bc7 100755 --- a/ThirdParty/sw_services/xilopenamp/data/xilopenamp.tcl +++ b/ThirdParty/sw_services/xilopenamp/data/xilopenamp.tcl @@ -46,8 +46,8 @@ proc openamp_drc {libhandle} { set hw_processor [common::get_property HW_INSTANCE $proc_instance] set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]]; - if { $proc_type != "psu_cortexr5" } { - error "ERROR: This library is supported only for CortexR5 processors."; + if { ( $proc_type != "psu_cortexr5" ) && ( $proc_type != "ps7_cortexa9" ) } { + error "ERROR: This library is supported only for CortexR5 and CortexA9 processors."; return; } } diff --git a/ThirdParty/sw_services/xilopenamp/src/remoteproc.c b/ThirdParty/sw_services/xilopenamp/src/remoteproc.c index c5e4725e..4a7a81d3 100644 --- a/ThirdParty/sw_services/xilopenamp/src/remoteproc.c +++ b/ThirdParty/sw_services/xilopenamp/src/remoteproc.c @@ -135,13 +135,16 @@ int remoteproc_resource_deinit(struct remote_proc *rproc) { env_deinit(); - /* Disable the caches - This is required if master boots firmwares - * multiple times without hard reset on same core. If caches are - * not invalidated at this point in time then subsequent firmware - * boots on the same core may experience cache inconsistencies. - * + /* + * Flush and Invalidate the caches - When the application is built with + * Xilinx Standalone BSP, caches are invalidated as part of boot process. + * Even if the master boots firmware multiple times without hard reset on + * same core, caches are flushed and invalidated at the end of + * remoteproc_resource_deinit for this run and caches would be again + * invalidated before starting the main thread of the application on next + * run to avoid any cache inconsistencies. */ - env_disable_cache(); + platform_cache_all_flush_invalidate(); return RPROC_SUCCESS; }