diff --git a/XilinxProcessorIPLib/drivers/dptx/data/dptx_0.mdd b/XilinxProcessorIPLib/drivers/dptx/data/dptx_0.mdd new file mode 100644 index 00000000..04d42a48 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/data/dptx_0.mdd @@ -0,0 +1,41 @@ +##****************************************************************************** +## +## Copyright (C) 2014 Xilinx, Inc. All rights reserved. +## +## Permission is hereby granted, free of charge, to any person obtaining a copy +## of this software and associated documentation files (the "Software"), to deal +## in the Software without restriction, including without limitation the rights +## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +## copies of the Software, and to permit persons to whom the Software is +## furnished to do so, subject to the following conditions: +## +## The above copyright notice and this permission notice shall be included in +## all copies or substantial portions of the Software. +## +## Use of the Software is limited solely to applications: +## (a) running on a Xilinx device, or +## (b) that interact with a Xilinx device through a bus or interconnect. +## +## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +## XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +## WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +## OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +## SOFTWARE. +## +## Except as contained in this notice, the name of the Xilinx shall not be used +## in advertising or otherwise to promote the sale, use or other dealings in +## this Software without prior written authorization from Xilinx. +## +##*****************************************************************************/ + +OPTION psf_version = 2.1; + +BEGIN driver dptx + OPTION supported_peripherals = (displayport); + OPTION driver_state = ACTIVE; + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = dptx; +END driver diff --git a/XilinxProcessorIPLib/drivers/dptx/data/dptx_0.tcl b/XilinxProcessorIPLib/drivers/dptx/data/dptx_0.tcl new file mode 100644 index 00000000..b23e575c --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/data/dptx_0.tcl @@ -0,0 +1,186 @@ +##****************************************************************************** +## +## Copyright (C) 2014 Xilinx, Inc. All rights reserved. +## +## Permission is hereby granted, free of charge, to any person obtaining a copy +## of this software and associated documentation files (the "Software"), to deal +## in the Software without restriction, including without limitation the rights +## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +## copies of the Software, and to permit persons to whom the Software is +## furnished to do so, subject to the following conditions: +## +## The above copyright notice and this permission notice shall be included in +## all copies or substantial portions of the Software. +## +## Use of the Software is limited solely to applications: +## (a) running on a Xilinx device, or +## (b) that interact with a Xilinx device through a bus or interconnect. +## +## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +## XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +## WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +## OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +## SOFTWARE. +## +## Except as contained in this notice, the name of the Xilinx shall not be used +## in advertising or otherwise to promote the sale, use or other dealings in +## this Software without prior written authorization from Xilinx. +## +##*****************************************************************************/ +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "S_AXI_ACLK" + xdefine_config_file $drv_handle "xdptx_g.c" "XDptx" "DEVICE_ID" "C_BASEADDR" "S_AXI_ACLK" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" + xdefine_canonical_xpars $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "S_AXI_ACLK" +} + +# +# Given a list of arguments, define them all in an include file. +# Handles IP model/user parameters, as well as the special parameters NUM_INSTANCES, +# DEVICE_ID +# Will not work for a processor. +# +proc xdefine_include_file {drv_handle file_name drv_string args} { + set args [get_exact_arg_list $args] + # Open include file + set file_handle [xopen_include_file $file_name] + + # Get all peripherals connected to this driver + set periphs [xget_sw_iplist_for_driver $drv_handle] + + # Handle special cases + set arg "NUM_INSTANCES" + set posn [lsearch -exact $args $arg] + if {$posn > -1} { + puts $file_handle "/* Definitions for driver [string toupper [get_property name $drv_handle]] */" + # Define NUM_INSTANCES + puts $file_handle "#define [xget_dname $drv_string $arg] [llength $periphs]" + set args [lreplace $args $posn $posn] + } + + # Check if it is a driver parameter + lappend newargs + foreach arg $args { + set value [get_property CONFIG.$arg $drv_handle] + if {[llength $value] == 0} { + lappend newargs $arg + } else { + puts $file_handle "#define [xget_dname $drv_string $arg] [get_property $arg $drv_handle]" + } + } + set args $newargs + + # Print all parameters for all peripherals + set device_id 0 + foreach periph $periphs { + puts $file_handle "" + puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */" + + foreach arg $args { + if {[string compare -nocase "DEVICE_ID" $arg] == 0} { + set value $device_id + incr device_id + } elseif {[string compare -nocase "S_AXI_ACLK" $arg] == 0} { + set freq [xget_ip_clk_pin_freq $periph $arg] + if {[llength $freq] == 0} { + set freq 0 + puts "WARNING: Clock frequency information is not available in the design, \ + for peripheral $periph_name. This will not work." + } + set value $freq + } else { + set value [get_property CONFIG.$arg $periph] + } + if {[llength $value] == 0} { + set value 0 + } + set value [xformat_addr_string $value $arg] + if {[string compare -nocase "HW_VER" $arg] == 0} { + puts $file_handle "#define [xget_name $periph $arg] \"$value\"" + } else { + puts $file_handle "#define [xget_name $periph $arg] $value" + } + } + puts $file_handle "" + } + puts $file_handle "\n/******************************************************************/\n" + close $file_handle +} + +# +# xdefine_canonical_xpars - Used to print out canonical defines for a driver. +# Given a list of arguments, define each as a canonical constant name, using +# the driver name, in an include file. +# +proc xdefine_canonical_xpars {drv_handle file_name drv_string args} { + set args [get_exact_arg_list $args] + # Open include file + set file_handle [xopen_include_file $file_name] + + # Get all the peripherals connected to this driver + set periphs [xget_sw_iplist_for_driver $drv_handle] + + # Get the names of all the peripherals connected to this driver + foreach periph $periphs { + set peripheral_name [string toupper [get_property NAME $periph]] + lappend peripherals $peripheral_name + } + + # Get possible canonical names for all the peripherals connected to this + # driver + set device_id 0 + foreach periph $periphs { + set canonical_name [string toupper [format "%s_%s" $drv_string $device_id]] + lappend canonicals $canonical_name + + # Create a list of IDs of the peripherals whose hardware instance name + # doesn't match the canonical name. These IDs can be used later to + # generate canonical definitions + if { [lsearch $peripherals $canonical_name] < 0 } { + lappend indices $device_id + } + incr device_id + } + + set i 0 + foreach periph $periphs { + set periph_name [string toupper [get_property NAME $periph]] + + # Generate canonical definitions only for the peripherals whose + # canonical name is not the same as hardware instance name + if { [lsearch $canonicals $periph_name] < 0 } { + puts $file_handle "/* Canonical definitions for peripheral $periph_name */" + set canonical_name [format "%s_%s" $drv_string [lindex $indices $i]] + + foreach arg $args { + set lvalue [xget_dname $canonical_name $arg] + + # The commented out rvalue is the name of the instance-specific constant + # set rvalue [xget_name $periph $arg] + # The rvalue set below is the actual value of the parameter + if {[string compare -nocase "S_AXI_ACLK" $arg] == 0} { + set freq [xget_ip_clk_pin_freq $periph $arg] + if {[llength $freq] == 0} { + set freq 0 + puts "WARNING: Clock frequency information is not available in the design, \ + for peripheral $periph_name. This will not work." + } + set rvalue $freq + } else { + set rvalue [xget_param_value $periph $arg] + if {[llength $rvalue] == 0} { + set rvalue 0 + } + set rvalue [xformat_addr_string $rvalue $arg] + } + puts $file_handle "#define $lvalue $rvalue" + } + puts $file_handle "" + incr i + } + } + + puts $file_handle "\n/******************************************************************/\n" + close $file_handle +} diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/annotated.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/annotated.html new file mode 100644 index 00000000..53d0c8d7 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/annotated.html @@ -0,0 +1,33 @@ + + + + + Data Structures + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

Data Structures

Here are the data structures with brief descriptions: + + + + + + + +
XDptx
XDptx_AuxTransaction
XDptx_Config
XDptx_DmtMode
XDptx_LinkConfig
XDptx_MainStreamAttributes
XDptx_SinkConfig
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/doxygen.png b/XilinxProcessorIPLib/drivers/dptx/doc/html/doxygen.png new file mode 100644 index 00000000..f0a274bb Binary files /dev/null and b/XilinxProcessorIPLib/drivers/dptx/doc/html/doxygen.png differ diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/driver_api_doxygen.css b/XilinxProcessorIPLib/drivers/dptx/doc/html/driver_api_doxygen.css new file mode 100644 index 00000000..8b5d35bb --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/driver_api_doxygen.css @@ -0,0 +1,334 @@ +BODY { + background-color: #FFFFFF; + font-family: Verdana, Arial, Helvetica, Sans-serif; +} + +H1 { + margin-bottom: 0em; + font-size: 2.00em; + font-style: normal; + color: #990033; +} + +H2 { + font-size: 1.05em; + font-style: normal; + color: #666666; +} + +H3 { + font-size: 1.00em; + font-style: normal; + color: #000000; +} + +H4 { + font-size: .90em; + font-style: italic; + color: #000000; +} + +H5 { + font-size: .90em; + font-style: italic; + color: #000000; +} + +H6 { + font-size: .90em; + font-style: italic; + color: #000000; +} + +OL { +} + +UL { +} + +LI { +} + +P { + color: #000000; +} + +P.Caution { + color: #990033; +} + +P.Code { + font-family: Courier New, Courier, Mono; + color: #003399; +} + +P.HeadingDBox { + font-weight: bold; +} + +P.HeadingGlossary { + font-weight: bold; +} + +P.LinkGlossary { + margin-bottom: .50em; +} + +P.Note { +} + +P.SysInOut { + font-family: Courier New, Courier, Mono; +} + +P.TableFootnote { + font-size: .80em; + margin-bottom: .70em; +} + +P.TableHeading { + font-weight: bold; + color: #FFFFFF; +} + +P.TableTitle { + font-style: italic; + font-weight: bold; +} + +SPAN.aEmphasis { + font-style: italic; +} + +SPAN.aFilename { + font-family: Courier New, Courier, Mono; +} + + +SPAN.aGUISysIn { + font-family: Verdana, Arial, Helvetica, Sans-serif; + font-weight: bold; +} + +SPAN.aReference { + font-style: italic; +} + +SPAN.aSysIn { + font-family: Courier New, Courier, Monospace; + font-weight: bold; +} + +SPAN.aSysOut { + font-family: Courier New, Courier, Monospace; +} + +SPAN.aSymbol { + font-family: Symbol; +} + +CAPTION { font-weight: bold } +DIV.qindex { + width: 100%; + background-color: #eeeeff; + border: 1px solid #B0B0B0; + text-align: center; + margin: 2px; + padding: 2px; +} +A.qindex { + text-decoration: none; + font-weight: bold; + color: #1A419D; + padding: 2px; +} +A.qindex:visited { + text-decoration: none; + font-weight: bold; + color: #1A419D + padding: 2px; +} +A.qindex:hover { + text-decoration: none; + background-color: #ddddff; + padding: 2px; +} +A.qindexHL { + text-decoration: none; + font-weight: bold; + background-color: #6666cc; + color: #ffffff; + padding: 2 6px; + border: 1px double #9295C2; + } +A.qindexHL:hover { + text-decoration: none; + background-color: #6666cc; + color: #ffffff; + padding: 2px 6px; +} +A.qindexHL:visited { text-decoration: none; background-color: #6666cc; color: #ffffff } +A.el { text-decoration: none; font-weight: bold } +A.elRef { font-weight: bold } +A.code { text-decoration: none; font-weight: normal; color: #1A419D} +A.codeRef { font-weight: normal; color: #1A419D} +A:hover { text-decoration: none; background-color: #f2f2ff } +DL.el { margin-left: -1cm } +PRE.fragment { + border: 1px solid #CCCCCC; + background-color: #f5f5f5; + margin-top: 4px; + margin-bottom: 4px; + margin-left: 2px; + margin-right: 8px; + padding-left: 6px; + padding-right: 6px; + padding-top: 4px; + padding-bottom: 4px; +} +DIV.fragment { + border: 1px solid #CCCCCC; + background-color: #f5f5f5; + padding: 6px; +} +DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } +TD.md { background-color: #F4F4FB; font-weight: bold; } +TD.mdname1 { background-color: #F4F4FB; font-weight: bold; color: #602020; } +TD.mdname { background-color: #F4F4FB; font-weight: bold; color: #602020; width: 600px; } +DIV.groupHeader { margin-left: 16px; margin-top: 12px; margin-bottom: 6px; font-weight: bold } +DIV.groupText { margin-left: 16px; font-style: italic; font-size: smaller } +BODY { + background: white; + color: black; + margin-right: 20px; + margin-left: 20px; +} +TD.indexkey { + background-color: #eeeeff; + font-weight: bold; + padding-right : 10px; + padding-top : 2px; + padding-left : 10px; + padding-bottom : 2px; + margin-left : 0px; + margin-right : 0px; + margin-top : 2px; + margin-bottom : 2px; + border: 1px solid #CCCCCC; +} +TD.indexvalue { + background-color: #eeeeff; + font-style: italic; + padding-right : 10px; + padding-top : 2px; + padding-left : 10px; + padding-bottom : 2px; + margin-left : 0px; + margin-right : 0px; + margin-top : 2px; + margin-bottom : 2px; + border: 1px solid #CCCCCC; +} +TR.memlist { + background-color: #f0f0f0; +} +P.formulaDsp { text-align: center; } +IMG.formulaDsp { } +IMG.formulaInl { vertical-align: middle; } +SPAN.keyword { color: #008000 } +SPAN.keywordtype { color: #604020 } +SPAN.keywordflow { color: #e08000 } +SPAN.comment { color: #800000 } +SPAN.preprocessor { color: #806020 } +SPAN.stringliteral { color: #002080 } +SPAN.charliteral { color: #008080 } +.mdTable { + border: 1px solid #868686; + background-color: #F4F4FB; +} +.mdRow { + padding: 8px 10px; +} +.mdescLeft { + font-size: smaller; + font-family: Verdana, Arial, Helvetica, sans-serif; + background-color: #FAFAFA; + padding-left: 8px; + border-top: 1px none #E0E0E0; + border-right: 1px none #E0E0E0; + border-bottom: 1px none #E0E0E0; + border-left: 1px none #E0E0E0; + margin: 0px; +} +.mdescRight { + font-size: smaller; + font-family: Verdana, Arial, Helvetica, sans-serif; + font-style: italic; + background-color: #FAFAFA; + padding-left: 4px; + border-top: 1px none #E0E0E0; + border-right: 1px none #E0E0E0; + border-bottom: 1px none #E0E0E0; + border-left: 1px none #E0E0E0; + margin: 0px; + padding-bottom: 0px; + padding-right: 8px; +} +.memItemLeft { + padding: 1px 0px 0px 8px; + margin: 4px; + border-top-width: 1px; + border-right-width: 1px; + border-bottom-width: 1px; + border-left-width: 1px; + border-top-style: solid; + border-top-color: #E0E0E0; + border-right-color: #E0E0E0; + border-bottom-color: #E0E0E0; + border-left-color: #E0E0E0; + border-right-style: none; + border-bottom-style: none; + border-left-style: none; + background-color: #FAFAFA; + font-family: Verdana, Arial, Helvetica, sans-serif; + font-size: 12px; +} +.memItemRight { + padding: 1px 0px 0px 8px; + margin: 4px; + border-top-width: 1px; + border-right-width: 1px; + border-bottom-width: 1px; + border-left-width: 1px; + border-top-style: solid; + border-top-color: #E0E0E0; + border-right-color: #E0E0E0; + border-bottom-color: #E0E0E0; + border-left-color: #E0E0E0; + border-right-style: none; + border-bottom-style: none; + border-left-style: none; + background-color: #FAFAFA; + font-family: Verdana, Arial, Helvetica, sans-serif; + font-size: 13px; +} +.search { color: #003399; + font-weight: bold; +} +FORM.search { + margin-bottom: 0px; + margin-top: 0px; +} +INPUT.search { font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #eeeeff; +} +TD.tiny { font-size: 75%; +} +a { + color: #252E78; +} +a:visited { + color: #3D2185; +} diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/files.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/files.html new file mode 100644 index 00000000..0a45029a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/files.html @@ -0,0 +1,33 @@ + + + + + File Index + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

File List

Here is a list of all documented files with brief descriptions: + + + + + + + +
xdptx.c
xdptx_hw.h
xdptx_intr.c
xdptx_selftest.c
xdptx_sinit.c
xdptx_spm.c
xdptx_vidmodetable.c
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/functions.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/functions.html new file mode 100644 index 00000000..83759396 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/functions.html @@ -0,0 +1,140 @@ + + + + + Data Fields + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+
+ +
+
+ +
+ +

+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +

+

- b -

+

- c -

+

- d -

+

- e -

+

- h -

+

- i -

+

- l -

+

- m -

+

- p -

+

- q -

+

- r -

+

- s -

+

- t -

+

- u -

+

- v -

+

- y -

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/functions_vars.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/functions_vars.html new file mode 100644 index 00000000..da34597c --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/functions_vars.html @@ -0,0 +1,140 @@ + + + + + Data Fields - Variables + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+
+ +
+
+ +
+ +

+  +

+

- b -

+

- c -

+

- d -

+

- e -

+

- h -

+

- i -

+

- l -

+

- m -

+

- p -

+

- q -

+

- r -

+

- s -

+

- t -

+

- u -

+

- v -

+

- y -

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals.html new file mode 100644 index 00000000..2d05ec67 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals.html @@ -0,0 +1,365 @@ + + + + + Data Fields + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+
+ +
+
+ +
+ +

+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +

+

- x -

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_defs.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_defs.html new file mode 100644 index 00000000..d5866ed2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_defs.html @@ -0,0 +1,328 @@ + + + + + Data Fields + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+
+ +
+
+ +
+ +

+  +

+

- x -

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_enum.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_enum.html new file mode 100644 index 00000000..ce4c0956 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_enum.html @@ -0,0 +1,38 @@ + + + + + Data Fields + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+
+ +
+  +

+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_func.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_func.html new file mode 100644 index 00000000..10c83545 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_func.html @@ -0,0 +1,78 @@ + + + + + Data Fields + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+
+ +
+
+ +
+ +

+  +

+

- x -

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_type.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_type.html new file mode 100644 index 00000000..02022fc0 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_type.html @@ -0,0 +1,41 @@ + + + + + Data Fields + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+
+ +
+  +

+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_vars.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_vars.html new file mode 100644 index 00000000..c341087b --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_vars.html @@ -0,0 +1,39 @@ + + + + + Data Fields + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+
+ +
+  +

+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/index.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/index.html new file mode 100644 index 00000000..0a2875e7 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/index.html @@ -0,0 +1,28 @@ + + + + + Main Page + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+

+

+The Xilinx DisplayPort transmitter (TX) driver.

+The driver currently supports single-stream transport (SST) functionality.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx-members.html new file mode 100644 index 00000000..4e36e4c9 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx-members.html @@ -0,0 +1,38 @@ + + + + + Member List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx Member List

This is the complete list of members for XDptx, including all inherited members.

+ + + + + + + + + + + + + +
HasRedriverInPathXDptx
HpdEventCallbackRefXDptx
HpdEventHandlerXDptx
HpdPulseCallbackRefXDptx
HpdPulseHandlerXDptx
IsReadyXDptx
LinkConfigXDptx
MsaConfigXDptx
RxConfigXDptx
TrainAdaptiveXDptx
TxConfigXDptx
UserTimerPtrXDptx
UserTimerWaitUsXDptx
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx.html new file mode 100644 index 00000000..cda60e73 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx.html @@ -0,0 +1,257 @@ + + + + + XDptx Struct Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx Struct Reference

#include <xdptx.h> +

+

Detailed Description

+The XDptx driver instance data. The user is required to allocate a variable of this type for every XDptx device in the system. A pointer to a variable of this type is then passed to the driver API functions. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

u32 IsReady
u8 TrainAdaptive
u8 HasRedriverInPath
XDptx_Config TxConfig
XDptx_SinkConfig RxConfig
XDptx_LinkConfig LinkConfig
XDptx_MainStreamAttributes MsaConfig
XDptx_TimerHandler UserTimerWaitUs
void * UserTimerPtr
XDptx_HpdEventHandler HpdEventHandler
void * HpdEventCallbackRef
XDptx_HpdPulseHandler HpdPulseHandler
void * HpdPulseCallbackRef
+

Field Documentation

+ +
+
+ + + + +
u8 XDptx::HasRedriverInPath
+
+
+ +

+Redriver in path requires different voltage swing and pre-emphasis. +

+

+ +

+
+ + + + +
void* XDptx::HpdEventCallbackRef
+
+
+ +

+A pointer to the user data passed to the HPD event callback function. +

+

+ +

+
+ + + + +
XDptx_HpdEventHandler XDptx::HpdEventHandler
+
+
+ +

+Callback function for hot- plug-detect event interrupts. +

+

+ +

+
+ + + + +
void* XDptx::HpdPulseCallbackRef
+
+
+ +

+A pointer to the user data passed to the HPD pulse callback function. +

+

+ +

+
+ + + + +
XDptx_HpdPulseHandler XDptx::HpdPulseHandler
+
+
+ +

+Callback function for hot- plug-detect pulse interrupts. +

+

+ +

+
+ + + + +
u32 XDptx::IsReady
+
+
+ +

+Device is initialized and ready. +

+

+ +

+
+ + + + +
XDptx_LinkConfig XDptx::LinkConfig
+
+
+ +

+Configuration structure for the main link. +

+

+ +

+
+ + + + +
XDptx_MainStreamAttributes XDptx::MsaConfig
+
+
+ +

+Configuration structure for the main stream attributes. +

+

+ +

+
+ + + + +
XDptx_SinkConfig XDptx::RxConfig
+
+
+ +

+Configuration structure for the sink. +

+

+ +

+
+ + + + +
u8 XDptx::TrainAdaptive
+
+
+ +

+Downshift lane count and link rate if necessary during training. +

+

+ +

+
+ + + + +
XDptx_Config XDptx::TxConfig
+
+
+ +

+Configuration structure for the core. +

+

+ +

+
+ + + + +
void* XDptx::UserTimerPtr
+
+
+ +

+Pointer to a timer instance used by the custom user delay/sleep function. +

+

+ +

+
+ + + + +
XDptx_TimerHandler XDptx::UserTimerWaitUs
+
+
+ +

+Custom user function for delay/sleep. +

+

+

The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction-members.html new file mode 100644 index 00000000..fe1a190e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction-members.html @@ -0,0 +1,25 @@ + + + + + Member List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_AuxTransaction Member List

This is the complete list of members for XDptx_AuxTransaction, including all inherited members.

+
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction.html new file mode 100644 index 00000000..5471bf32 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction.html @@ -0,0 +1,32 @@ + + + + + XDptx_AuxTransaction Struct Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_AuxTransaction Struct Reference

Detailed Description

+This typedef describes an AUX transaction. +

+ + +
+

The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config-members.html new file mode 100644 index 00000000..7dfe9cbe --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config-members.html @@ -0,0 +1,35 @@ + + + + + Member List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_Config Member List

This is the complete list of members for XDptx_Config, including all inherited members.

+ + + + + + + + + + +
BaseAddrXDptx_Config
DeviceIdXDptx_Config
DualPixelEnXDptx_Config
MaxBitsPerColorXDptx_Config
MaxLaneCountXDptx_Config
MaxLinkRateXDptx_Config
QuadPixelEnXDptx_Config
SAxiClkHzXDptx_Config
YCrCbEnXDptx_Config
YOnlyEnXDptx_Config
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config.html new file mode 100644 index 00000000..4ffe0721 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config.html @@ -0,0 +1,206 @@ + + + + + XDptx_Config Struct Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_Config Struct Reference

#include <xdptx.h> +

+

Detailed Description

+This typedef contains configuration information for the DisplayPort TX core. +

+ + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

u16 DeviceId
u32 BaseAddr
u32 SAxiClkHz
u8 MaxLaneCount
u8 MaxLinkRate
u8 MaxBitsPerColor
u8 QuadPixelEn
u8 DualPixelEn
u8 YOnlyEn
u8 YCrCbEn
+

Field Documentation

+ +
+
+ + + + +
u32 XDptx_Config::BaseAddr
+
+
+ +

+The base address of the core. +

+

+ +

+
+ + + + +
u16 XDptx_Config::DeviceId
+
+
+ +

+Device instance ID. +

+

+ +

+
+ + + + +
u8 XDptx_Config::DualPixelEn
+
+
+ +

+Dual pixel support by this core's instance. +

+

+ +

+
+ + + + +
u8 XDptx_Config::MaxBitsPerColor
+
+
+ +

+The maximum bits/color supported by this core's instance +

+

+ +

+
+ + + + +
u8 XDptx_Config::MaxLaneCount
+
+
+ +

+The maximum lane count supported by this core's instance. +

+

+ +

+
+ + + + +
u8 XDptx_Config::MaxLinkRate
+
+
+ +

+The maximum link rate supported by this core's instance. +

+

+ +

+
+ + + + +
u8 XDptx_Config::QuadPixelEn
+
+
+ +

+Quad pixel support by this core's instance. +

+

+ +

+
+ + + + +
u32 XDptx_Config::SAxiClkHz
+
+
+ +

+The clock frequency of the core's S_AXI_ACLK port. +

+

+ +

+
+ + + + +
u8 XDptx_Config::YCrCbEn
+
+
+ +

+YCrCb format support by this core's instance. +

+

+ +

+
+ + + + +
u8 XDptx_Config::YOnlyEn
+
+
+ +

+YOnly format support by this core's instance. +

+

+

The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode-members.html new file mode 100644 index 00000000..d0a940d4 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode-members.html @@ -0,0 +1,39 @@ + + + + + Member List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_DmtMode Member List

This is the complete list of members for XDptx_DmtMode, including all inherited members.

+ + + + + + + + + + + + + + +
DmtIdXDptx_DmtMode
HBackPorchXDptx_DmtMode
HFrontPorchXDptx_DmtMode
HResolutionXDptx_DmtMode
HSyncPolarityXDptx_DmtMode
HSyncPulseWidthXDptx_DmtMode
PixelClkKhzXDptx_DmtMode
ScanXDptx_DmtMode
VBackPorchXDptx_DmtMode
VFrontPorchXDptx_DmtMode
VideoModeXDptx_DmtMode
VResolutionXDptx_DmtMode
VSyncPolarityXDptx_DmtMode
VSyncPulseWidthXDptx_DmtMode
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode.html new file mode 100644 index 00000000..be7bfb71 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode.html @@ -0,0 +1,274 @@ + + + + + XDptx_DmtMode Struct Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_DmtMode Struct Reference

#include <xdptx.h> +

+

Detailed Description

+This typedef contains the display monitor timing attributes for a video mode. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

XDptx_VideoMode VideoMode
u8 DmtId
u16 HResolution
u16 VResolution
u32 PixelClkKhz
u8 Scan
u8 HSyncPolarity
u8 VSyncPolarity
u32 HFrontPorch
u32 HSyncPulseWidth
u32 HBackPorch
u32 VFrontPorch
u32 VSyncPulseWidth
u32 VBackPorch
+

Field Documentation

+ +
+
+ + + + +
u8 XDptx_DmtMode::DmtId
+
+
+ +

+Standard DMT ID number. +

+

+ +

+
+ + + + +
u32 XDptx_DmtMode::HBackPorch
+
+
+ +

+Horizontal back porch. +

+

+ +

+
+ + + + +
u32 XDptx_DmtMode::HFrontPorch
+
+
+ +

+Horizontal front porch. +

+

+ +

+
+ + + + +
u16 XDptx_DmtMode::HResolution
+
+
+ +

+Horizontal resolution. +

+

+ +

+
+ + + + +
u8 XDptx_DmtMode::HSyncPolarity
+
+
+ +

+Horizontal polarity. +

+

+ +

+
+ + + + +
u32 XDptx_DmtMode::HSyncPulseWidth
+
+
+ +

+Horizontal synchronization pulse width. +

+

+ +

+
+ + + + +
u32 XDptx_DmtMode::PixelClkKhz
+
+
+ +

+Pixel frequency (in KHz). +

+

+ +

+
+ + + + +
u8 XDptx_DmtMode::Scan
+
+
+ +

+Interlaced/non-interlaced. +

+

+ +

+
+ + + + +
u32 XDptx_DmtMode::VBackPorch
+
+
+ +

+Vertical back porch. +

+

+ +

+
+ + + + +
u32 XDptx_DmtMode::VFrontPorch
+
+
+ +

+Vertical front porch. +

+

+ +

+
+ + + + +
XDptx_VideoMode XDptx_DmtMode::VideoMode
+
+
+ +

+Enumerated key. +

+

+ +

+
+ + + + +
u16 XDptx_DmtMode::VResolution
+
+
+ +

+Vertical resolution. +

+

+ +

+
+ + + + +
u8 XDptx_DmtMode::VSyncPolarity
+
+
+ +

+Vertical polarity. +

+

+ +

+
+ + + + +
u32 XDptx_DmtMode::VSyncPulseWidth
+
+
+ +

+Vertical synchronization pulse width. +

+

+

The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config-members.html new file mode 100644 index 00000000..1339fb3a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config-members.html @@ -0,0 +1,41 @@ + + + + + Member List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_LinkConfig Member List

This is the complete list of members for XDptx_LinkConfig, including all inherited members.

+ + + + + + + + + + + + + + + + +
ComponentFormatXDptx_LinkConfig
DownspreadControlXDptx_LinkConfig
DynamicRangeXDptx_LinkConfig
EnhancedFramingModeXDptx_LinkConfig
LaneCountXDptx_LinkConfig
LinkRateXDptx_LinkConfig
MaxLaneCountXDptx_LinkConfig
MaxLinkRateXDptx_LinkConfig
PatternXDptx_LinkConfig
PeLevelXDptx_LinkConfig
ScramblerEnXDptx_LinkConfig
SupportDownspreadControlXDptx_LinkConfig
SupportEnhancedFramingModeXDptx_LinkConfig
SynchronousClockModeXDptx_LinkConfig
VsLevelXDptx_LinkConfig
YCbCrColorimetryXDptx_LinkConfig
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config.html new file mode 100644 index 00000000..59f4d1d8 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config.html @@ -0,0 +1,308 @@ + + + + + XDptx_LinkConfig Struct Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_LinkConfig Struct Reference

#include <xdptx.h> +

+

Detailed Description

+This typedef contains configuration information about the main link settings. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

u8 LaneCount
u8 LinkRate
u8 ScramblerEn
u8 EnhancedFramingMode
u8 DownspreadControl
u8 MaxLaneCount
u8 MaxLinkRate
u8 SupportEnhancedFramingMode
u8 SupportDownspreadControl
u8 VsLevel
u8 PeLevel
u8 ComponentFormat
u8 DynamicRange
u8 YCbCrColorimetry
u8 SynchronousClockMode
u8 Pattern
+

Field Documentation

+ +
+
+ + + + +
u8 XDptx_LinkConfig::ComponentFormat
+
+
+ +

+The component format currently in use over the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::DownspreadControl
+
+
+ +

+Downspread control is currently in use over the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::DynamicRange
+
+
+ +

+The dynamic range currently in use over the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::EnhancedFramingMode
+
+
+ +

+Enhanced frame mode is currently in use over the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::LaneCount
+
+
+ +

+The current lane count of the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::LinkRate
+
+
+ +

+The current link rate of the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::MaxLaneCount
+
+
+ +

+The maximum lane count of the source-sink main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::MaxLinkRate
+
+
+ +

+The maximum link rate of the source-sink main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::Pattern
+
+
+ +

+The current pattern currently in use over the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::PeLevel
+
+
+ +

+The current pre-emphasis/cursor level for each lane. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::ScramblerEn
+
+
+ +

+Symbol scrambling is currently in use over the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::SupportDownspreadControl
+
+
+ +

+Downspread control is supported by the receiver. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::SupportEnhancedFramingMode
+
+
+ +

+Enhanced frame mode is supported by the receiver. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::SynchronousClockMode
+
+
+ +

+Synchronous clock mode is currently in use over the main link. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::VsLevel
+
+
+ +

+The current voltage swing level for each lane. +

+

+ +

+
+ + + + +
u8 XDptx_LinkConfig::YCbCrColorimetry
+
+
+ +

+The YCbCr colorimetry currently in use over the main link. +

+

+

The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes-members.html new file mode 100644 index 00000000..36fece81 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes-members.html @@ -0,0 +1,25 @@ + + + + + Member List + + + +

Xilinx Processor IP Library

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+ +
+
+
+
+

XDptx_MainStreamAttributes Member List

This is the complete list of members for XDptx_MainStreamAttributes, including all inherited members.

+
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes.html new file mode 100644 index 00000000..d52ddc4c --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes.html @@ -0,0 +1,34 @@ + + + + + XDptx_MainStreamAttributes Struct Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_MainStreamAttributes Struct Reference

#include <xdptx.h> +

+

Detailed Description

+This typedef contains the main stream attributes which determine how the video will be displayed. +

+ + +
+

The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config-members.html new file mode 100644 index 00000000..7741d4b9 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config-members.html @@ -0,0 +1,27 @@ + + + + + Member List + + + +

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+ +
+
+
+
+

XDptx_SinkConfig Member List

This is the complete list of members for XDptx_SinkConfig, including all inherited members.

+ + +
DpcdRxCapsFieldXDptx_SinkConfig
EdidXDptx_SinkConfig
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config.html new file mode 100644 index 00000000..293121e8 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config.html @@ -0,0 +1,87 @@ + + + + + XDptx_SinkConfig Struct Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

XDptx_SinkConfig Struct Reference

#include <xdptx.h> +

+

Detailed Description

+This typedef contains configuration information about the sink. +

+ + + + + + + + + +

Data Fields

u8 DpcdRxCapsField [256]
u8 Edid [128]
u8 LaneStatusAdjReqs [6]
+

Field Documentation

+ +
+
+ + + + +
u8 XDptx_SinkConfig::DpcdRxCapsField[256]
+
+
+ +

+The raw capabilities field of the sink's DPCD. +

+

+ +

+
+ + + + +
u8 XDptx_SinkConfig::Edid[128]
+
+
+ +

+The sink's raw EDID. +

+

+ +

+
+ + + + +
u8 XDptx_SinkConfig::LaneStatusAdjReqs[6]
+
+
+ +

+This is a raw read of the receiver DPCD's status registers. The first 4 bytes correspond to the lane status from the receiver's DPCD associated with clock recovery, channel equalization, symbol lock, and interlane alignment. The 2 remaining bytes represent the adjustments requested by the DPCD. +

+

+

The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_b.gif b/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_b.gif new file mode 100644 index 00000000..0d623483 Binary files /dev/null and b/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_b.gif differ diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_l.gif b/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_l.gif new file mode 100644 index 00000000..9b1e6337 Binary files /dev/null and b/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_l.gif differ diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_r.gif b/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_r.gif new file mode 100644 index 00000000..ce9dd9f5 Binary files /dev/null and b/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_r.gif differ diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/tabs.css b/XilinxProcessorIPLib/drivers/dptx/doc/html/tabs.css new file mode 100644 index 00000000..a61552a6 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/tabs.css @@ -0,0 +1,102 @@ +/* tabs styles, based on http://www.alistapart.com/articles/slidingdoors */ + +DIV.tabs +{ + float : left; + width : 100%; + background : url("tab_b.gif") repeat-x bottom; + margin-bottom : 4px; +} + +DIV.tabs UL +{ + margin : 0px; + padding-left : 10px; + list-style : none; +} + +DIV.tabs LI, DIV.tabs FORM +{ + display : inline; + margin : 0px; + padding : 0px; +} + +DIV.tabs FORM +{ + float : right; +} + +DIV.tabs A +{ + float : left; + background : url("tab_r.gif") no-repeat right top; + border-bottom : 1px solid #84B0C7; + font-size : x-small; + font-weight : bold; + text-decoration : none; +} + +DIV.tabs A:hover +{ + background-position: 100% -150px; +} + +DIV.tabs A:link, DIV.tabs A:visited, +DIV.tabs A:active, DIV.tabs A:hover +{ + color: #1A419D; +} + +DIV.tabs SPAN +{ + float : left; + display : block; + background : url("tab_l.gif") no-repeat left top; + padding : 5px 9px; + white-space : nowrap; +} + +DIV.tabs INPUT +{ + float : right; + display : inline; + font-size : 1em; +} + +DIV.tabs TD +{ + font-size : x-small; + font-weight : bold; + text-decoration : none; +} + + + +/* Commented Backslash Hack hides rule from IE5-Mac \*/ +DIV.tabs SPAN {float : none;} +/* End IE5-Mac hack */ + +DIV.tabs A:hover SPAN +{ + background-position: 0% -150px; +} + +DIV.tabs LI#current A +{ + background-position: 100% -150px; + border-width : 0px; +} + +DIV.tabs LI#current SPAN +{ + background-position: 0% -150px; + padding-bottom : 6px; +} + +DIV.nav +{ + background : none; + border : none; + border-bottom : 1px solid #84B0C7; +} diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8c.html new file mode 100644 index 00000000..3031b35e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8c.html @@ -0,0 +1,996 @@ + + + + + xdptx.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

xdptx.c File Reference

Detailed Description

+Contains a minimal wset of functions for the XDptx driver that allow access to all the DisplayPort transmitter's functionality. See xdptx.h for a detailed description of the driver.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
+

+#include "xdptx.h"
+#include "xstatus.h"
+#include "xenv.h"
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  XDptx_AuxTransaction

Enumerations

enum  XDptx_TrainingState

Functions

u32 XDptx_InitializeTx (XDptx *InstancePtr)
void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr)
u32 XDptx_GetSinkCapabilities (XDptx *InstancePtr)
u32 XDptx_GetEdid (XDptx *InstancePtr)
u32 XDptx_CfgMainLinkMax (XDptx *InstancePtr)
u32 XDptx_EstablishLink (XDptx *InstancePtr)
u32 XDptx_CheckLinkStatus (XDptx *InstancePtr, u8 LaneCount)
void XDptx_EnableTrainAdaptive (XDptx *InstancePtr, u8 Enable)
void XDptx_SetHasRedriverInPath (XDptx *InstancePtr, u8 Set)
u32 XDptx_AuxRead (XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
u32 XDptx_AuxWrite (XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, u8 *DataBuffer)
u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, u8 *DataBuffer)
u32 XDptx_SetDownspread (XDptx *InstancePtr, u8 Enable)
u32 XDptx_SetEnhancedFrameMode (XDptx *InstancePtr, u8 Enable)
u32 XDptx_SetLaneCount (XDptx *InstancePtr, u8 LaneCount)
u32 XDptx_SetLinkRate (XDptx *InstancePtr, u8 LinkRate)
u32 XDptx_SetScrambler (XDptx *InstancePtr, u8 Enable)
void XDptx_EnableMainLink (XDptx *InstancePtr)
void XDptx_DisableMainLink (XDptx *InstancePtr)
void XDptx_ResetPhy (XDptx *InstancePtr, u32 Reset)
void XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef)
void XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds)
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum XDptx_TrainingState
+
+
+ +

+This typedef enumerates the list of training states used in the state machine during the link training process. +

+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
u32 XDptx_AuxRead (XDptx *  InstancePtr,
u32  Address,
u32  NumBytes,
void *  Data 
)
+
+
+ +

+This function issues a read request over the AUX channel.

+

Parameters:
+ + + + + +
InstancePtr is a pointer to the XDptx instance.
Address is the starting address to read from the receiver.
NumBytes is the number of bytes to read from the receiver.
Data is a pointer to the data buffer that will be filled with read data.
+
+
Returns:
    +
  • XST_SUCCESS if the AUX read request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_NO_DATA if no data was provided.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
u32 XDptx_AuxWrite (XDptx *  InstancePtr,
u32  Address,
u32  NumBytes,
void *  Data 
)
+
+
+ +

+This function issues a write request over the AUX channel.

+

Parameters:
+ + + + + +
InstancePtr is a pointer to the XDptx instance.
Address is the starting address to write to the receiver.
NumBytes is the number of bytes to write to the receiver.
Data is a pointer to the data buffer that contains the data to be written to the receiver.
+
+
Returns:
    +
  • XST_SUCCESS if AUX write request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_NO_DATA if no data was provided.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_CfgInitialize (XDptx *  InstancePtr,
XDptx_Config *  ConfigPtr,
u32  EffectiveAddr 
)
+
+
+ +

+This function retrieves the configuration for this DisplayPort TX instance and fills in the InstancePtr->TxConfig structure.

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
ConfigPtr is a pointer to the configuration structure that will be used to copy the settings from.
EffectiveAddr is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.
+
+
Note:
Unexpected errors may occur if the address mapping is changed after this function is invoked.
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_CfgMainLinkMax (XDptx *  InstancePtr  ) 
+
+
+ +

+This function determines the common capabilities between the DisplayPort TX core and the receiver.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS if main link settings were successfully set.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the specified link configuration specifies a link rate or lane count that isn't valid.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_CheckLinkStatus (XDptx *  InstancePtr,
u8  LaneCount 
)
+
+
+ +

+This function checks if the reciever's DPCD indicates the reciever has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
LaneCount is the number of lanes to check.
+
+
Returns:
    +
  • XST_SUCCESS if the receiver has maintained clock recovery, channel equalization, symbol lock, and interlane alignment.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the number of lanes to check does not match 1, 2, or 4 lanes.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_DisableMainLink (XDptx *  InstancePtr  ) 
+
+
+ +

+This function disables the main link.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_EnableMainLink (XDptx *  InstancePtr  ) 
+
+
+ +

+This function enables the main link.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void XDptx_EnableTrainAdaptive (XDptx *  InstancePtr,
u8  Enable 
)
+
+
+ +

+This function enables or disables downshifting during the training process.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Enable controls the downshift feature in the training process.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_EstablishLink (XDptx *  InstancePtr  ) 
+
+
+ +

+This function determines the common capabilities between the DisplayPort TX core and the receiver.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS was either already trained, or has been trained successfully.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the current link rate or lane count isn't valid.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_GetEdid (XDptx *  InstancePtr  ) 
+
+
+ +

+This function retrieves the receiver's EDID.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_GetSinkCapabilities (XDptx *  InstancePtr  ) 
+
+
+ +

+This function retrieves sink device capabilities from the receiver's DPCD.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS if the DPCD was read successfully.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
u32 XDptx_IicRead (XDptx *  InstancePtr,
u8  IicAddress,
u8  RegStartAddress,
u8  NumBytes,
u8 *  DataBuffer 
)
+
+
+ +

+This function performs an I2C read over the AUX channel.

+

Parameters:
+ + + + + + +
InstancePtr is a pointer to the XDptx instance.
IicAddress is the address on the I2C bus of the target device.
RegStartAddress is the subaddress of the targeted I2C device that the read will start from.
NumBytes is the number of bytes to read.
DataBuffer is a pointer to a buffer that will be filled with the I2C read data.
+
+
Returns:
    +
  • XST_SUCCESS if the I2C read has successfully completed with no errors.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
u32 XDptx_IicWrite (XDptx *  InstancePtr,
u8  IicAddress,
u8  RegStartAddress,
u8  NumBytes,
u8 *  DataBuffer 
)
+
+
+ +

+This function performs an I2C write over the AUX channel.

+

Parameters:
+ + + + + + +
InstancePtr is a pointer to the XDptx instance.
IicAddress is the address on the I2C bus of the target device.
RegStartAddress is the sub-address of the targeted I2C device that the write will start at.
NumBytes is the number of bytes to write.
DataBuffer is a pointer to a buffer which will be used as the data source for the write.
+
+
Returns:
    +
  • XST_SUCCESS if the I2C write has successfully completed with no errors.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_InitializeTx (XDptx *  InstancePtr  ) 
+
+
+ +

+This function prepares the DisplayPort TX core for use.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS if the DisplayPort TX core was successfully initialized.
  • XST_INVALID_PARAM if the supplied link rate does not correspond to either 1.62, 2.70, or 5.40 Gbps.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void XDptx_ResetPhy (XDptx *  InstancePtr,
u32  Reset 
)
+
+
+ +

+This function does a PHY reset.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance. &
Reset is the type of reset to assert.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetDownspread (XDptx *  InstancePtr,
u8  Enable 
)
+
+
+ +

+This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Enable will enable or disable down-spread control.
+
+
Returns:
    +
  • XST_SUCCESS if setting the downspread control enable was successful.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetEnhancedFrameMode (XDptx *  InstancePtr,
u8  Enable 
)
+
+
+ +

+This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Enable will enable or disable enhanced frame mode.
+
+
Returns:
    +
  • XST_SUCCESS if setting the enhanced frame mode enable was successful.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void XDptx_SetHasRedriverInPath (XDptx *  InstancePtr,
u8  Set 
)
+
+
+ +

+This function sets a software switch that signifies whether or not a redriver exists on the DisplayPort output path. XDptx_SetVswingPreemp uses this switch to determine which set of voltage swing and pre-emphasis values to use in the TX core.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Set establishes that a redriver exists in the DisplayPort output path.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetLaneCount (XDptx *  InstancePtr,
u8  LaneCount 
)
+
+
+ +

+This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
LaneCount is the number of lanes to be used over the main link.
+
+
Returns:
    +
  • XST_SUCCESS if setting the new lane count was successful.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the supplied lane count is not either 1, 2, or 4 lanes.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetLinkRate (XDptx *  InstancePtr,
u8  LinkRate 
)
+
+
+ +

+This function sets the data rate to be used by the main link for both the DisplayPort TX core and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
LinkRate is the link rate to be used over the main link based on one of the following selects:
    +
  • XDPTX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate)
  • XDPTX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate)
  • XDPTX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate)
+
+
+
Returns:
    +
  • XST_SUCCESS if setting the new link rate was successful.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the supplied link rate does not correspond to either 1.62, 2.70, or 5.40 Gbps.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetScrambler (XDptx *  InstancePtr,
u8  Enable 
)
+
+
+ +

+This function enables or disables scrambling of symbols for both the DisplayPort and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Enable will enable or disable scrambling.
+
+
Returns:
    +
  • XST_SUCCESS if setting the scrambling enable was successful.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_SetUserTimerHandler (XDptx *  InstancePtr,
XDptx_TimerHandler  CallbackFunc,
void *  CallbackRef 
)
+
+
+ +

+This function installs a custom delay/sleep function to be used by the XDdptx driver.

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
CallbackFunc is the address to the callback function.
CallbackRef is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void XDptx_WaitUs (XDptx *  InstancePtr,
u32  MicroSeconds 
)
+
+
+ +

+This function is the delay/sleep function for the XDptx driver. For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
MicroSeconds is the number of microseconds to delay/sleep for.
+
+ +
+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8h.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8h.html new file mode 100644 index 00000000..f012d52d --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8h.html @@ -0,0 +1,1535 @@ + + + + + xdptx.h File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

xdptx.h File Reference

Detailed Description

+The Xilinx DisplayPort transmitter (TX) driver.

+The driver currently supports single-stream transport (SST) functionality.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
+

+#include "xdptx_hw.h"
+#include "xil_assert.h"
+#include "xil_types.h"
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  XDptx_DmtMode
struct  XDptx_Config
struct  XDptx_SinkConfig
struct  XDptx_LinkConfig
struct  XDptx_MainStreamAttributes
struct  XDptx

Defines

#define XDptx_IsConnected(InstancePtr)

Typedefs

typedef void(*) XDptx_TimerHandler (void *InstancePtr, u32 MicroSeconds)
typedef void(*) XDptx_HpdEventHandler (void *InstancePtr)
typedef void(*) XDptx_HpdPulseHandler (void *InstancePtr)

Enumerations

enum  XDptx_VideoMode

Functions

u32 XDptx_InitializeTx (XDptx *InstancePtr)
void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr)
u32 XDptx_GetSinkCapabilities (XDptx *InstancePtr)
u32 XDptx_GetEdid (XDptx *InstancePtr)
u32 XDptx_CfgMainLinkMax (XDptx *InstancePtr)
u32 XDptx_EstablishLink (XDptx *InstancePtr)
u32 XDptx_CheckLinkStatus (XDptx *InstancePtr, u8 LaneCount)
void XDptx_EnableTrainAdaptive (XDptx *InstancePtr, u8 Enable)
void XDptx_SetHasRedriverInPath (XDptx *InstancePtr, u8 Set)
u32 XDptx_AuxRead (XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
u32 XDptx_AuxWrite (XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, u8 *DataBuffer)
u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, u8 *DataBuffer)
u32 XDptx_SetDownspread (XDptx *InstancePtr, u8 Enable)
u32 XDptx_SetEnhancedFrameMode (XDptx *InstancePtr, u8 Enable)
u32 XDptx_SetLaneCount (XDptx *InstancePtr, u8 LaneCount)
u32 XDptx_SetLinkRate (XDptx *InstancePtr, u8 LinkRate)
u32 XDptx_SetScrambler (XDptx *InstancePtr, u8 Enable)
void XDptx_EnableMainLink (XDptx *InstancePtr)
void XDptx_DisableMainLink (XDptx *InstancePtr)
void XDptx_ResetPhy (XDptx *InstancePtr, u32 Reset)
void XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds)
void XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef)
void XDptx_CfgMsaRecalculate (XDptx *InstancePtr)
u32 XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, XDptx_VideoMode VideoMode)
void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr)
void XDptx_CfgMsaUseCustom (XDptx *InstancePtr, XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
u32 XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 BitsPerColor)
void XDptx_SetVideoMode (XDptx *InstancePtr)
void XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
void XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
void XDptx_HpdInterruptHandler (XDptx *InstancePtr)
u32 XDptx_SelfTest (XDptx *InstancePtr)
XDptx_Config * XDptx_LookupConfig (u16 DeviceId)

Variables

XDptx_DmtMode XDptx_DmtModes []
+

Define Documentation

+ +
+
+ + + + + + + + + +
#define XDptx_IsConnected (InstancePtr   ) 
+
+
+ +

+Value:

(XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, \
+        XDPTX_INTERRUPT_SIG_STATE) & 0x1)
+
This macro checks if there is a connected sink.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • TRUE if there is a connection.
  • FALSE if there is no connection.
+
+
Note:
C-style signature: void XDptx_IsConnected(XDptx *InstancePtr)
+ +
+

+

Typedef Documentation

+ +
+
+ + + + +
typedef void(*) XDptx_HpdEventHandler(void *InstancePtr)
+
+
+ +

+Callback type which represents the handler for a hot-plug-detect event interrupt.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + +
typedef void(*) XDptx_HpdPulseHandler(void *InstancePtr)
+
+
+ +

+Callback type which represents the handler for a hot-plug-detect pulse interrupt.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + +
typedef void(*) XDptx_TimerHandler(void *InstancePtr, u32 MicroSeconds)
+
+
+ +

+Callback type which represents a custom timer wait handler. This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
MicroSeconds is the number of microseconds to be passed to the timer function.
+
+ +
+

+

Enumeration Type Documentation

+ +
+
+ + + + +
enum XDptx_VideoMode
+
+
+ +

+This typedef enumerates the list of available standard display monitor timings as specified in the mode_table.c file. The naming format is:

+XDPTX_VM_<RESOLUTION>_<REFRESH RATE (HZ)>_<P|RB>

+Where RB stands for reduced blanking. +

+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
u32 XDptx_AuxRead (XDptx *  InstancePtr,
u32  Address,
u32  NumBytes,
void *  Data 
)
+
+
+ +

+This function issues a read request over the AUX channel.

+

Parameters:
+ + + + + +
InstancePtr is a pointer to the XDptx instance.
Address is the starting address to read from the receiver.
NumBytes is the number of bytes to read from the receiver.
Data is a pointer to the data buffer that will be filled with read data.
+
+
Returns:
    +
  • XST_SUCCESS if the AUX read request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_NO_DATA if no data was provided.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
u32 XDptx_AuxWrite (XDptx *  InstancePtr,
u32  Address,
u32  NumBytes,
void *  Data 
)
+
+
+ +

+This function issues a write request over the AUX channel.

+

Parameters:
+ + + + + +
InstancePtr is a pointer to the XDptx instance.
Address is the starting address to write to the receiver.
NumBytes is the number of bytes to write to the receiver.
Data is a pointer to the data buffer that contains the data to be written to the receiver.
+
+
Returns:
    +
  • XST_SUCCESS if AUX write request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_NO_DATA if no data was provided.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_CfgInitialize (XDptx *  InstancePtr,
XDptx_Config *  ConfigPtr,
u32  EffectiveAddr 
)
+
+
+ +

+This function retrieves the configuration for this DisplayPort TX instance and fills in the InstancePtr->TxConfig structure.

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
ConfigPtr is a pointer to the configuration structure that will be used to copy the settings from.
EffectiveAddr is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.
+
+
Note:
Unexpected errors may occur if the address mapping is changed after this function is invoked.
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_CfgMainLinkMax (XDptx *  InstancePtr  ) 
+
+
+ +

+This function determines the common capabilities between the DisplayPort TX core and the receiver.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS if main link settings were successfully set.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the specified link configuration specifies a link rate or lane count that isn't valid.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_CfgMsaRecalculate (XDptx *  InstancePtr  ) 
+
+
+ +

+This function calculates the following main stream attributes:

+

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Note:
The MsaConfig structure is modified with the new, calculated values. The main stream attributes that were used to derive the calculated values are untouched in the MsaConfig structure.
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_CfgMsaSetBpc (XDptx *  InstancePtr,
u8  BitsPerColor 
)
+
+
+ +

+This function sets the bits per color value of the video stream.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance
BitsPerColor is the new number of bits per color to use.
+
+
Note:
The InstancePtr->MsaConfig structure is modified to reflect the new main stream attributes associated with a new bits per color value.
+
Returns:
    +
  • XST_INVALID_PARAM if the supplied bits per color value is not either 6, 8, 10, 12, or 16.
  • XST_SUCCESS otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_CfgMsaUseCustom (XDptx *  InstancePtr,
XDptx_MainStreamAttributes *  MsaConfigCustom,
u8  Recalculate 
)
+
+
+ +

+This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes that must be contained in the MsaConfigCustom structure are:

+

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
MsaConfigCustom is the structure that will be used to copy the main stream attributes from (into InstancePtr->MsaConfig).
Recalculate is a boolean enable that determines whether or not the main stream attributes should be recalculated.
+
+
Note:
The InstancePtr-> MsaConfig structure is modified with the new values.
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *  InstancePtr  ) 
+
+
+ +

+This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. This preferred timing information is stored in the sink's extended display identification data (EDID).

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance
+
+
Note:
The InstancePtr->MsaConfig structure is modified to reflect the main stream attribute values associated to the preferred timing of the sink monitor.
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_CfgMsaUseStandardVideoMode (XDptx *  InstancePtr,
XDptx_VideoMode  VideoMode 
)
+
+
+ +

+This function sets the main stream attribute values in the configuration structure to match one of the standard display mode timings from the XDptx_DmtModes[] table. THe XDptx_VideoMode enumeration in xdptx.h lists the available video modes.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
VideoMode is one of the enumerated standard video modes that is used to determine the main stream attributes to be used.
+
+
Returns:
    +
  • XST_INVALID_PARAM if the supplied video mode isn't in the DMT table.
  • XST_SUCCESS otherwise.
+
+
Note:
The InstancePtr->MsaConfig structure is modified to reflect the main stream attribute values associated to the specified video mode.
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_CheckLinkStatus (XDptx *  InstancePtr,
u8  LaneCount 
)
+
+
+ +

+This function checks if the reciever's DPCD indicates the reciever has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
LaneCount is the number of lanes to check.
+
+
Returns:
    +
  • XST_SUCCESS if the receiver has maintained clock recovery, channel equalization, symbol lock, and interlane alignment.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the number of lanes to check does not match 1, 2, or 4 lanes.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_DisableMainLink (XDptx *  InstancePtr  ) 
+
+
+ +

+This function disables the main link.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_EnableMainLink (XDptx *  InstancePtr  ) 
+
+
+ +

+This function enables the main link.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void XDptx_EnableTrainAdaptive (XDptx *  InstancePtr,
u8  Enable 
)
+
+
+ +

+This function enables or disables downshifting during the training process.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Enable controls the downshift feature in the training process.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_EstablishLink (XDptx *  InstancePtr  ) 
+
+
+ +

+This function determines the common capabilities between the DisplayPort TX core and the receiver.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS was either already trained, or has been trained successfully.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the current link rate or lane count isn't valid.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_GetEdid (XDptx *  InstancePtr  ) 
+
+
+ +

+This function retrieves the receiver's EDID.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_GetSinkCapabilities (XDptx *  InstancePtr  ) 
+
+
+ +

+This function retrieves sink device capabilities from the receiver's DPCD.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS if the DPCD was read successfully.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_HpdInterruptHandler (XDptx *  InstancePtr  ) 
+
+
+ +

+This function is the interrupt handler for the XDptx driver.

+When an interrupt happens, it first detects what kind of interrupt happened, then decides which callback function to invoke.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
u32 XDptx_IicRead (XDptx *  InstancePtr,
u8  IicAddress,
u8  RegStartAddress,
u8  NumBytes,
u8 *  DataBuffer 
)
+
+
+ +

+This function performs an I2C read over the AUX channel.

+

Parameters:
+ + + + + + +
InstancePtr is a pointer to the XDptx instance.
IicAddress is the address on the I2C bus of the target device.
RegStartAddress is the subaddress of the targeted I2C device that the read will start from.
NumBytes is the number of bytes to read.
DataBuffer is a pointer to a buffer that will be filled with the I2C read data.
+
+
Returns:
    +
  • XST_SUCCESS if the I2C read has successfully completed with no errors.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
u32 XDptx_IicWrite (XDptx *  InstancePtr,
u8  IicAddress,
u8  RegStartAddress,
u8  NumBytes,
u8 *  DataBuffer 
)
+
+
+ +

+This function performs an I2C write over the AUX channel.

+

Parameters:
+ + + + + + +
InstancePtr is a pointer to the XDptx instance.
IicAddress is the address on the I2C bus of the target device.
RegStartAddress is the sub-address of the targeted I2C device that the write will start at.
NumBytes is the number of bytes to write.
DataBuffer is a pointer to a buffer which will be used as the data source for the write.
+
+
Returns:
    +
  • XST_SUCCESS if the I2C write has successfully completed with no errors.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_InitializeTx (XDptx *  InstancePtr  ) 
+
+
+ +

+This function prepares the DisplayPort TX core for use.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS if the DisplayPort TX core was successfully initialized.
  • XST_INVALID_PARAM if the supplied link rate does not correspond to either 1.62, 2.70, or 5.40 Gbps.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + +
XDptx_Config* XDptx_LookupConfig (u16  DeviceId  ) 
+
+
+ +

+This function looks for the device configuration based on the unique device ID. The table XDptx_ConfigTable[] contains the configuration information for each device in the system.

+

Parameters:
+ + +
DeviceId is the unique device ID of the device being looked up.
+
+
Returns:
A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void XDptx_ResetPhy (XDptx *  InstancePtr,
u32  Reset 
)
+
+
+ +

+This function does a PHY reset.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance. &
Reset is the type of reset to assert.
+
+ +
+

+ +

+
+ + + + + + + + + +
u32 XDptx_SelfTest (XDptx *  InstancePtr  ) 
+
+
+ +

+This function runs a self-test on the XDptx driver/device. The test attempts to intialize the DisplayPort TX core, train the main link at the highest common capabilities between the core and the sink, and checks the status of the link after training.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS if the self-test passed. The main link has been trained and established successfully.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetDownspread (XDptx *  InstancePtr,
u8  Enable 
)
+
+
+ +

+This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Enable will enable or disable down-spread control.
+
+
Returns:
    +
  • XST_SUCCESS if setting the downspread control enable was successful.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetEnhancedFrameMode (XDptx *  InstancePtr,
u8  Enable 
)
+
+
+ +

+This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Enable will enable or disable enhanced frame mode.
+
+
Returns:
    +
  • XST_SUCCESS if setting the enhanced frame mode enable was successful.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void XDptx_SetHasRedriverInPath (XDptx *  InstancePtr,
u8  Set 
)
+
+
+ +

+This function sets a software switch that signifies whether or not a redriver exists on the DisplayPort output path. XDptx_SetVswingPreemp uses this switch to determine which set of voltage swing and pre-emphasis values to use in the TX core.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Set establishes that a redriver exists in the DisplayPort output path.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_SetHpdEventHandler (XDptx *  InstancePtr,
XDptx_HpdEventHandler  CallbackFunc,
void *  CallbackRef 
)
+
+
+ +

+This function installs a callback function for when a hot-plug-detect event interrupt occurs.

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
CallbackFunc is the address to the callback function.
CallbackRef is the user data item that will be passed to the callback function when it is invoked.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_SetHpdPulseHandler (XDptx *  InstancePtr,
XDptx_HpdPulseHandler  CallbackFunc,
void *  CallbackRef 
)
+
+
+ +

+This function installs a callback function for when a hot-plug-detect pulse interrupt occurs.

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
CallbackFunc is the address to the callback function.
CallbackRef is the user data item that will be passed to the callback function when it is invoked.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetLaneCount (XDptx *  InstancePtr,
u8  LaneCount 
)
+
+
+ +

+This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
LaneCount is the number of lanes to be used over the main link.
+
+
Returns:
    +
  • XST_SUCCESS if setting the new lane count was successful.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the supplied lane count is not either 1, 2, or 4 lanes.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetLinkRate (XDptx *  InstancePtr,
u8  LinkRate 
)
+
+
+ +

+This function sets the data rate to be used by the main link for both the DisplayPort TX core and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
LinkRate is the link rate to be used over the main link based on one of the following selects:
    +
  • XDPTX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate)
  • XDPTX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate)
  • XDPTX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate)
+
+
+
Returns:
    +
  • XST_SUCCESS if setting the new link rate was successful.
  • XST_DEVICE_NOT_FOUND if no receiver is connected.
  • XST_INVALID_PARAM if the supplied link rate does not correspond to either 1.62, 2.70, or 5.40 Gbps.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_SetScrambler (XDptx *  InstancePtr,
u8  Enable 
)
+
+
+ +

+This function enables or disables scrambling of symbols for both the DisplayPort and the sink device.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
Enable will enable or disable scrambling.
+
+
Returns:
    +
  • XST_SUCCESS if setting the scrambling enable was successful.
  • XST_FAILURE otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_SetUserTimerHandler (XDptx *  InstancePtr,
XDptx_TimerHandler  CallbackFunc,
void *  CallbackRef 
)
+
+
+ +

+This function installs a custom delay/sleep function to be used by the XDdptx driver.

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
CallbackFunc is the address to the callback function.
CallbackRef is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked.
+
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_SetVideoMode (XDptx *  InstancePtr  ) 
+
+
+ +

+This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void XDptx_WaitUs (XDptx *  InstancePtr,
u32  MicroSeconds 
)
+
+
+ +

+This function is the delay/sleep function for the XDptx driver. For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
MicroSeconds is the number of microseconds to delay/sleep for.
+
+ +
+

+

Variable Documentation

+ +
+
+ + + + +
XDptx_DmtMode XDptx_DmtModes[]
+
+
+ +

+This table contains the main stream attributes for various standard resolutions. +

+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__hw_8h.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__hw_8h.html new file mode 100644 index 00000000..659d6a78 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__hw_8h.html @@ -0,0 +1,4916 @@ + + + + + xdptx_hw.h File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

xdptx_hw.h File Reference

Detailed Description

+This header file contains the identifiers and low-level driver functions (or macros) that can be used to access the device. High-level driver functions are defined in xdptx.h.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
+

+#include "xil_io.h"
+#include "xil_types.h"
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

DPTX core registers: Link configuration field.

#define XDPTX_LINK_BW_SET   0x0000
#define XDPTX_LANE_COUNT_SET   0x0004
#define XDPTX_ENHANCED_FRAME_EN   0x0008
#define XDPTX_TRAINING_PATTERN_SET   0x000C
#define XDPTX_LINK_QUAL_PATTERN_SET   0x0010
#define XDPTX_SCRAMBLING_DISABLE   0x0014
#define XDPTX_DOWNSPREAD_CTRL   0x0018
#define XDPTX_SOFT_RESET   0x001C

DPTX core registers: Core enables.

#define XDPTX_ENABLE   0x0080
#define XDPTX_ENABLE_MAIN_STREAM   0x0084
#define XDPTX_ENABLE_SEC_STREAM   0x0088
#define XDPTX_FORCE_SCRAMBLER_RESET   0x00C0
#define XDPTX_TX_MST_CONFIG   0x00D0

DPTX core registers: Core ID.

#define XDPTX_VERSION   0x00F8
#define XDPTX_CORE_ID   0x00FC

DPTX core registers: AUX channel interface.

#define XDPTX_AUX_CMD   0x0100
#define XDPTX_AUX_WRITE_FIFO   0x0104
#define XDPTX_AUX_ADDRESS   0x0108
#define XDPTX_AUX_CLK_DIVIDER   0x010C
#define XDPTX_TX_USER_FIFO_OVERFLOW   0x0110
#define XDPTX_INTERRUPT_SIG_STATE   0x0130
#define XDPTX_AUX_REPLY_DATA   0x0134
#define XDPTX_AUX_REPLY_CODE   0x0138
#define XDPTX_AUX_REPLY_COUNT   0x013C
#define XDPTX_INTERRUPT_STATUS   0x0140
#define XDPTX_INTERRUPT_MASK   0x0144
#define XDPTX_REPLY_DATA_COUNT   0x0148
#define XDPTX_REPLY_STATUS   0x014C
#define XDPTX_HPD_DURATION   0x0150

DPTX core registers: Main stream attributes for SST / MST STREAM1.

#define XDPTX_MAIN_STREAM_HTOTAL   0x0180
#define XDPTX_MAIN_STREAM_VTOTAL   0x0184
#define XDPTX_MAIN_STREAM_POLARITY   0x0188
#define XDPTX_MAIN_STREAM_HSWIDTH   0x018C
#define XDPTX_MAIN_STREAM_VSWIDTH   0x0190
#define XDPTX_MAIN_STREAM_HRES   0x0194
#define XDPTX_MAIN_STREAM_VRES   0x0198
#define XDPTX_MAIN_STREAM_HSTART   0x019C
#define XDPTX_MAIN_STREAM_VSTART   0x01A0
#define XDPTX_MAIN_STREAM_MISC0   0x01A4
#define XDPTX_MAIN_STREAM_MISC1   0x01A8
#define XDPTX_M_VID   0x01AC
#define XDPTX_TU_SIZE   0x01B0
#define XDPTX_N_VID   0x01B4
#define XDPTX_USER_PIXEL_WIDTH   0x01B8
#define XDPTX_USER_DATA_COUNT_PER_LANE   0x01BC
#define XDPTX_MAIN_STREAM_INTERLACED   0x01C0
#define XDPTX_MIN_BYTES_PER_TU   0x01C4
#define XDPTX_FRAC_BYTES_PER_TU   0x01C8
#define XDPTX_INIT_WAIT   0x01CC
#define XDPTX_STREAM0   0x01D0
#define XDPTX_STREAM1   0x01D4
#define XDPTX_STREAM2   0x01D8
#define XDPTX_STREAM3   0x01DC

DPTX core registers: PHY configuration status.

#define XDPTX_PHY_CONFIG   0x0200
#define XDPTX_PHY_VOLTAGE_DIFF_LANE_0   0x0220
#define XDPTX_PHY_VOLTAGE_DIFF_LANE_1   0x0224
#define XDPTX_PHY_VOLTAGE_DIFF_LANE_2   0x0228
#define XDPTX_PHY_VOLTAGE_DIFF_LANE_3   0x022C
#define XDPTX_PHY_TRANSMIT_PRBS7   0x0230
#define XDPTX_PHY_CLOCK_SELECT   0x0234
#define XDPTX_TX_PHY_POWER_DOWN   0x0238
#define XDPTX_PHY_PRECURSOR_LANE_0   0x023C
#define XDPTX_PHY_PRECURSOR_LANE_1   0x0240
#define XDPTX_PHY_PRECURSOR_LANE_2   0x0244
#define XDPTX_PHY_PRECURSOR_LANE_3   0x0248
#define XDPTX_PHY_POSTCURSOR_LANE_0   0x024C
#define XDPTX_PHY_POSTCURSOR_LANE_1   0x0250
#define XDPTX_PHY_POSTCURSOR_LANE_2   0x0254
#define XDPTX_PHY_POSTCURSOR_LANE_3   0x0258
#define XDPTX_PHY_STATUS   0x0280
#define XDPTX_GT_DRP_COMMAND   0x02A0
#define XDPTX_GT_DRP_READ_DATA   0x02A4
#define XDPTX_GT_DRP_CHANNEL_STATUS   0x02A8

DPTX core registers: DisplayPort audio.

#define XDPTX_TX_AUDIO_CONTROL   0x0300
#define XDPTX_TX_AUDIO_CHANNELS   0x0304
#define XDPTX_TX_AUDIO_INFO_DATA   0x0308
#define XDPTX_TX_AUDIO_MAUD   0x0328
#define XDPTX_TX_AUDIO_NAUD   0x032C
#define XDPTX_TX_AUDIO_EXT_DATA   0x0330

DPTX core registers: Main stream attributes for MST STREAM2.

#define XDPTX_MAIN_STREAM2_HTOTAL   0x0500
#define XDPTX_MAIN_STREAM2_VTOTAL   0x0504
#define XDPTX_MAIN_STREAM2_POLARITY   0x0508
#define XDPTX_MAIN_STREAM2_HSWIDTH   0x050C
#define XDPTX_MAIN_STREAM2_VSWIDTH   0x0510
#define XDPTX_MAIN_STREAM2_HRES   0x0514
#define XDPTX_MAIN_STREAM2_VRES   0x0518
#define XDPTX_MAIN_STREAM2_HSTART   0x051C
#define XDPTX_MAIN_STREAM2_VSTART   0x0520
#define XDPTX_MAIN_STREAM2_MISC0   0x0524
#define XDPTX_MAIN_STREAM2_MISC1   0x0528
#define XDPTX_M_VID_STREAM2   0x052C
#define XDPTX_TU_SIZE_STREAM2   0x0530
#define XDPTX_N_VID_STREAM2   0x0534
#define XDPTX_USER_PIXEL_WIDTH_STREAM2   0x0538
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2   0x053C
#define XDPTX_MAIN_STREAM2_INTERLACED   0x0540
#define XDPTX_MIN_BYTES_PER_TU_STREAM2   0x0544
#define XDPTX_FRAC_BYTES_PER_TU_STREAM2   0x0548
#define XDPTX_INIT_WAIT_STREAM2   0x054C

DPTX core registers: Main stream attributes for MST STREAM3.

#define XDPTX_MAIN_STREAM3_HTOTAL   0x0550
#define XDPTX_MAIN_STREAM3_VTOTAL   0x0554
#define XDPTX_MAIN_STREAM3_POLARITY   0x0558
#define XDPTX_MAIN_STREAM3_HSWIDTH   0x055C
#define XDPTX_MAIN_STREAM3_VSWIDTH   0x0560
#define XDPTX_MAIN_STREAM3_HRES   0x0564
#define XDPTX_MAIN_STREAM3_VRES   0x0568
#define XDPTX_MAIN_STREAM3_HSTART   0x056C
#define XDPTX_MAIN_STREAM3_VSTART   0x0570
#define XDPTX_MAIN_STREAM3_MISC0   0x0574
#define XDPTX_MAIN_STREAM3_MISC1   0x0578
#define XDPTX_M_VID_STREAM3   0x057C
#define XDPTX_TU_SIZE_STREAM3   0x0580
#define XDPTX_N_VID_STREAM3   0x0584
#define XDPTX_USER_PIXEL_WIDTH_STREAM3   0x0588
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3   0x058C
#define XDPTX_MAIN_STREAM3_INTERLACED   0x0590
#define XDPTX_MIN_BYTES_PER_TU_STREAM3   0x0594
#define XDPTX_FRAC_BYTES_PER_TU_STREAM3   0x0598
#define XDPTX_INIT_WAIT_STREAM3   0x059C

DPTX core registers: Main stream attributes for MST STREAM4.

#define XDPTX_MAIN_STREAM4_HTOTAL   0x05A0
#define XDPTX_MAIN_STREAM4_VTOTAL   0x05A4
#define XDPTX_MAIN_STREAM4_POLARITY   0x05A8
#define XDPTX_MAIN_STREAM4_HSWIDTH   0x05AC
#define XDPTX_MAIN_STREAM4_VSWIDTH   0x05B0
#define XDPTX_MAIN_STREAM4_HRES   0x05B4
#define XDPTX_MAIN_STREAM4_VRES   0x05B8
#define XDPTX_MAIN_STREAM4_HSTART   0x05BC
#define XDPTX_MAIN_STREAM4_VSTART   0x05C0
#define XDPTX_MAIN_STREAM4_MISC0   0x05C4
#define XDPTX_MAIN_STREAM4_MISC1   0x05C8
#define XDPTX_M_VID_STREAM4   0x05CC
#define XDPTX_TU_SIZE_STREAM4   0x05D0
#define XDPTX_N_VID_STREAM4   0x05D4
#define XDPTX_USER_PIXEL_WIDTH_STREAM4   0x05D8
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4   0x05DC
#define XDPTX_MAIN_STREAM4_INTERLACED   0x05E0
#define XDPTX_MIN_BYTES_PER_TU_STREAM4   0x05E4
#define XDPTX_FRAC_BYTES_PER_TU_STREAM4   0x05E8
#define XDPTX_INIT_WAIT_STREAM4   0x05EC

DPTX core masks, shifts, and register values.

#define XDPTX_LINK_BW_SET_162GBPS   0x06
#define XDPTX_LINK_BW_SET_270GBPS   0x0A
#define XDPTX_LINK_BW_SET_540GBPS   0x14
#define XDPTX_TRAINING_PATTERN_SET_OFF   0x0
#define XDPTX_TRAINING_PATTERN_SET_TP1   0x1
#define XDPTX_TRAINING_PATTERN_SET_TP2   0x2
#define XDPTX_TRAINING_PATTERN_SET_TP3   0x3
#define XDPTX_LINK_QUAL_PATTERN_SET_OFF   0x0
#define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1
#define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES   0x2
#define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7   0x3
#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001
#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002
#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004
#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008
#define XDPTX_SOFT_RESET_AUX_MASK   0x00000080
#define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F
#define XDPTX_TX_MST_CONFIG_MST_EN_MASK   0x00000001
#define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002
#define XDPTX_VERSION_INTER_REV_MASK   0x0000000F
#define XDPTX_VERSION_CORE_PATCH_MASK   0x00000030
#define XDPTX_VERSION_CORE_PATCH_SHIFT   8
#define XDPTX_VERSION_CORE_VER_REV_MASK   0x000000C0
#define XDPTX_VERSION_CORE_VER_REV_SHIFT   12
#define XDPTX_VERSION_CORE_VER_MNR_MASK   0x00000F00
#define XDPTX_VERSION_CORE_VER_MNR_SHIFT   16
#define XDPTX_VERSION_CORE_VER_MJR_MASK   0x0000F000
#define XDPTX_VERSION_CORE_VER_MJR_SHIFT   24
#define XDPTX_CORE_ID_TYPE_MASK   0x0000000F
#define XDPTX_CORE_ID_TYPE_TX   0x0
#define XDPTX_CORE_ID_TYPE_RX   0x1
#define XDPTX_CORE_ID_DP_REV_MASK   0x000000F0
#define XDPTX_CORE_ID_DP_REV_SHIFT   8
#define XDPTX_CORE_ID_DP_MNR_VER_MASK   0x00000F00
#define XDPTX_CORE_ID_DP_MNR_VER_SHIFT   16
#define XDPTX_CORE_ID_DP_MJR_VER_MASK   0x0000F000
#define XDPTX_CORE_ID_DP_MJR_VER_SHIFT   24
#define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F
#define XDPTX_AUX_CMD_MASK   0x00000F00
#define XDPTX_AUX_CMD_SHIFT   8
#define XDPTX_AUX_CMD_I2C_WRITE   0x0
#define XDPTX_AUX_CMD_I2C_READ   0x1
#define XDPTX_AUX_CMD_I2C_WRITE_STATUS   0x2
#define XDPTX_AUX_CMD_I2C_WRITE_MOT   0x4
#define XDPTX_AUX_CMD_I2C_READ_MOT   0x5
#define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6
#define XDPTX_AUX_CMD_WRITE   0x8
#define XDPTX_AUX_CMD_READ   0x9
#define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000
#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK   0x0000000F
#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0x00000F00
#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8
#define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001
#define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002
#define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004
#define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008
#define XDPTX_AUX_REPLY_CODE_ACK   0x0
#define XDPTX_AUX_REPLY_CODE_I2C_ACK   0x0
#define XDPTX_AUX_REPLY_CODE_NACK   0x1
#define XDPTX_AUX_REPLY_CODE_DEFER   0x2
#define XDPTX_AUX_REPLY_CODE_I2C_NACK   0x4
#define XDPTX_AUX_REPLY_CODE_I2C_DEFER   0x8
#define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001
#define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002
#define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004
#define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008
#define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010
#define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020
#define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001
#define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002
#define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004
#define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008
#define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010
#define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020
#define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001
#define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002
#define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004
#define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008
#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0
#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4
#define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001
#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002
#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1
#define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1
#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008
#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3
#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010
#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4
#define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0
#define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT   5
#define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001
#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006
#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1
#define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0010000
#define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0010001
#define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0010002
#define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0010100
#define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0010200
#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0010400
#define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0011000
#define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x001E000
#define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0010003
#define XDPTX_PHY_CLOCK_SELECT_162GBPS   0x1
#define XDPTX_PHY_CLOCK_SELECT_270GBPS   0x3
#define XDPTX_PHY_CLOCK_SELECT_540GBPS   0x5
#define XDPTX_VS_LEVEL_0   0x2
#define XDPTX_VS_LEVEL_1   0x5
#define XDPTX_VS_LEVEL_2   0x8
#define XDPTX_VS_LEVEL_3   0xF
#define XDPTX_VS_LEVEL_OFFSET   0x4
#define XDPTX_PE_LEVEL_0   0x00
#define XDPTX_PE_LEVEL_1   0x0E
#define XDPTX_PE_LEVEL_2   0x14
#define XDPTX_PE_LEVEL_3   0x1B
#define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003
#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C
#define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010
#define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020
#define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000020
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30
#define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F
#define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F
#define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080
#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00
#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16

Defines

#define XDPTX_VC_PAYLOAD_BUFFER_ADDR   0x0800
#define XDptx_ReadReg(BaseAddress, RegOffset)   XDptx_In32((BaseAddress) + (RegOffset))
#define XDptx_WriteReg(BaseAddress, RegOffset, Data)   XDptx_Out32((BaseAddress) + (RegOffset), (Data))
+

Define Documentation

+ +
+
+ + + + +
#define XDPTX_AUX_ADDRESS   0x0108
+
+
+ +

+Specifies the address of current AUX command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CLK_DIVIDER   0x010C
+
+
+ +

+Clock divider value for generating the internal 1MHz clock. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0x00000F00
+
+
+ +

+AUX (noise) signal width filter. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8
+
+
+ +

+Shift bits for AUX signal width filter. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK   0x0000000F
+
+
+ +

+Clock divider value. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD   0x0100
+
+
+ +

+Initiates AUX commands. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000
+
+
+ +

+Address only transfer enable (STOP will be sent after command). +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_I2C_READ   0x1
+
+
+ +

+I2C-over-AUX read command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_I2C_READ_MOT   0x5
+
+
+ +

+I2C-over-AUX read MOT (middle-of-transaction) command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_I2C_WRITE   0x0
+
+
+ +

+I2C-over-AUX write command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_I2C_WRITE_MOT   0x4
+
+
+ +

+I2C-over-AUX write MOT (middle-of-transaction) command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_I2C_WRITE_STATUS   0x2
+
+
+ +

+I2C-over-AUX write status command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6
+
+
+ +

+I2C-over-AUX write status MOT (middle-of- transaction) command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_MASK   0x00000F00
+
+
+ +

+AUX command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F
+
+
+ +

+Number of bytes to transfer with the current AUX command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_READ   0x9
+
+
+ +

+AUX read command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_SHIFT   8
+
+
+ +

+Shift bits for command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_CMD_WRITE   0x8
+
+
+ +

+AUX write command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_CODE   0x0138
+
+
+ +

+Reply code received from the most recent AUX command. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_CODE_ACK   0x0
+
+
+ +

+AUX command ACKed. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_CODE_DEFER   0x2
+
+
+ +

+AUX command deferred. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_CODE_I2C_ACK   0x0
+
+
+ +

+I2C-over-AUX command not ACKed. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_CODE_I2C_DEFER   0x8
+
+
+ +

+I2C-over-AUX command deferred. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_CODE_I2C_NACK   0x4
+
+
+ +

+I2C-over-AUX command not ACKed. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_CODE_NACK   0x1
+
+
+ +

+AUX command not ACKed. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_COUNT   0x013C
+
+
+ +

+Number of reply transactions receieved over AUX. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_REPLY_DATA   0x0134
+
+
+ +

+Reply data received during the AUX reply. +

+

+ +

+
+ + + + +
#define XDPTX_AUX_WRITE_FIFO   0x0104
+
+
+ +

+Write data for the current AUX command. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID   0x00FC
+
+
+ +

+DisplayPort revision. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_DP_MJR_VER_MASK   0x0000F000
+
+
+ +

+DisplayPort protocol major version. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_DP_MJR_VER_SHIFT   24
+
+
+ +

+Shift bits for DisplayPort protocol major version. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_DP_MNR_VER_MASK   0x00000F00
+
+
+ +

+DisplayPort protocol minor version. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_DP_MNR_VER_SHIFT   16
+
+
+ +

+Shift bits for DisplayPort protocol major version. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_DP_REV_MASK   0x000000F0
+
+
+ +

+DisplayPort protocol revision. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_DP_REV_SHIFT   8
+
+
+ +

+Shift bits for DisplayPort protocol revision. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_TYPE_MASK   0x0000000F
+
+
+ +

+Core type. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_TYPE_RX   0x1
+
+
+ +

+Core is a receiver. +

+

+ +

+
+ + + + +
#define XDPTX_CORE_ID_TYPE_TX   0x0
+
+
+ +

+Core is a transmitter. +

+

+ +

+
+ + + + +
#define XDPTX_DOWNSPREAD_CTRL   0x0018
+
+
+ +

+Enable a 0.5% spreading of the clock. +

+

+ +

+
+ + + + +
#define XDPTX_ENABLE   0x0080
+
+
+ +

+Enable the basic operations of the transmitter or output stuffing symbols if disabled. +

+

+ +

+
+ + + + +
#define XDPTX_ENABLE_MAIN_STREAM   0x0084
+
+
+ +

+Enable transmission of main link video info. +

+

+ +

+
+ + + + +
#define XDPTX_ENABLE_SEC_STREAM   0x0088
+
+
+ +

+Enable the transmission of secondary link info. +

+

+ +

+
+ + + + +
#define XDPTX_ENHANCED_FRAME_EN   0x0008
+
+
+ +

+Enable enhanced framing symbol sequence. +

+

+ +

+
+ + + + +
#define XDPTX_FORCE_SCRAMBLER_RESET   0x00C0
+
+
+ +

+Force a scrambler reset. +

+

+ +

+
+ + + + +
#define XDPTX_FRAC_BYTES_PER_TU   0x01C8
+
+
+ +

+The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. +

+

+ +

+
+ + + + +
#define XDPTX_FRAC_BYTES_PER_TU_STREAM2   0x0548
+
+
+ +

+The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. +

+

+ +

+
+ + + + +
#define XDPTX_FRAC_BYTES_PER_TU_STREAM3   0x0598
+
+
+ +

+The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. +

+

+ +

+
+ + + + +
#define XDPTX_FRAC_BYTES_PER_TU_STREAM4   0x05E8
+
+
+ +

+The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. +

+

+ +

+
+ + + + +
#define XDPTX_GT_DRP_CHANNEL_STATUS   0x02A8
+
+
+ +

+Provides access to GT DRP channel status. +

+

+ +

+
+ + + + +
#define XDPTX_GT_DRP_COMMAND   0x02A0
+
+
+ +

+Provides acces to the GT DRP ports. +

+

+ +

+
+ + + + +
#define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F
+
+
+ +

+DRP address. +

+

+ +

+
+ + + + +
#define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080
+
+
+ +

+DRP read/write command (Read=0, Write=1). +

+

+ +

+
+ + + + +
#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00
+
+
+ +

+DRP write data. +

+

+ +

+
+ + + + +
#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16
+
+
+ +

+Shift bits for DRP write data. +

+

+ +

+
+ + + + +
#define XDPTX_GT_DRP_READ_DATA   0x02A4
+
+
+ +

+Provides access to GT DRP read data. +

+

+ +

+
+ + + + +
#define XDPTX_HPD_DURATION   0x0150
+
+
+ +

+Duration of the HPD pulse in microseconds. +

+

+ +

+
+ + + + +
#define XDPTX_INIT_WAIT   0x01CC
+
+
+ +

+Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. +

+

+ +

+
+ + + + +
#define XDPTX_INIT_WAIT_STREAM2   0x054C
+
+
+ +

+Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. +

+

+ +

+
+ + + + +
#define XDPTX_INIT_WAIT_STREAM3   0x059C
+
+
+ +

+Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. +

+

+ +

+
+ + + + +
#define XDPTX_INIT_WAIT_STREAM4   0x05EC
+
+
+ +

+Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_MASK   0x0144
+
+
+ +

+Masks the specified interrupt sources. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020
+
+
+ +

+Mask extended packet transmit interrupt. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002
+
+
+ +

+Mask HPD event interrupt. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001
+
+
+ +

+Mask HPD IRQ interrupt. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010
+
+
+ +

+Mask HPD pulse detected interrupt. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004
+
+
+ +

+Mask reply received interrupt. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008
+
+
+ +

+Mask reply received interrupt. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_SIG_STATE   0x0130
+
+
+ +

+The raw signal values for interupt events. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001
+
+
+ +

+Raw state of the HPD pin on the DP connector. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004
+
+
+ +

+A reply is currently being received. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008
+
+
+ +

+A reply timeout has occurred. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002
+
+
+ +

+A request is currently being sent. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_STATUS   0x0140
+
+
+ +

+Status for interrupt events. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020
+
+
+ +

+Extended packet has been transmitted and the core is ready to accept a new packet. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002
+
+
+ +

+Detected the presence of the HPD signal. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001
+
+
+ +

+Detected an IRQ framed with the proper timing on the HPD signal. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010
+
+
+ +

+A pulse on the HPD line was detected. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004
+
+
+ +

+An AUX reply transaction has been detected. +

+

+ +

+
+ + + + +
#define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008
+
+
+ +

+A reply timeout has occurred. +

+

+ +

+
+ + + + +
#define XDPTX_LANE_COUNT_SET   0x0004
+
+
+ +

+Set lane count setting. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_BW_SET   0x0000
+
+
+ +

+Set main link bandwidth setting. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_BW_SET_162GBPS   0x06
+
+
+ +

+1.62 Gbps link rate. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_BW_SET_270GBPS   0x0A
+
+
+ +

+2.70 Gbps link rate. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_BW_SET_540GBPS   0x14
+
+
+ +

+5.40 Gbps link rate. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_QUAL_PATTERN_SET   0x0010
+
+
+ +

+Transmit the link quality pattern. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1
+
+
+ +

+D10.2 unscrambled test pattern transmitted. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_QUAL_PATTERN_SET_OFF   0x0
+
+
+ +

+Link quality test pattern not transmitted. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7   0x3
+
+
+ +

+Pseudo random bit sequence 7 transmitted. +

+

+ +

+
+ + + + +
#define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES   0x2
+
+
+ +

+Symbol error rate measurement pattern transmitted. +

+

+ +

+
+ + + + +
#define XDPTX_M_VID   0x01AC
+
+
+ +

+M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +

+

+ +

+
+ + + + +
#define XDPTX_M_VID_STREAM2   0x052C
+
+
+ +

+M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +

+

+ +

+
+ + + + +
#define XDPTX_M_VID_STREAM3   0x057C
+
+
+ +

+M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +

+

+ +

+
+ + + + +
#define XDPTX_M_VID_STREAM4   0x05CC
+
+
+ +

+M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_HRES   0x0514
+
+
+ +

+Number of active pixels per line (the horizontal resolution). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_HSTART   0x051C
+
+
+ +

+Number of clocks between the leading edge of the horizontal sync and the start of active data. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_HSWIDTH   0x050C
+
+
+ +

+Width of the horizontal sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_HTOTAL   0x0500
+
+
+ +

+Total number of clocks in the horizontal framing period. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_INTERLACED   0x0540
+
+
+ +

+Video is interlaced. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_MISC0   0x0524
+
+
+ +

+Miscellaneous stream attributes. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_MISC1   0x0528
+
+
+ +

+Miscellaneous stream attributes. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_POLARITY   0x0508
+
+
+ +

+Polarity for the video sync signals. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_VRES   0x0518
+
+
+ +

+Number of active lines (the vertical resolution). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_VSTART   0x0520
+
+
+ +

+Number of lines between the leading edge of the vertical sync and the first line of active data. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_VSWIDTH   0x0510
+
+
+ +

+Width of the vertical sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM2_VTOTAL   0x0504
+
+
+ +

+Total number of lines in the video frame. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_HRES   0x0564
+
+
+ +

+Number of active pixels per line (the horizontal resolution). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_HSTART   0x056C
+
+
+ +

+Number of clocks between the leading edge of the horizontal sync and the start of active data. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_HSWIDTH   0x055C
+
+
+ +

+Width of the horizontal sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_HTOTAL   0x0550
+
+
+ +

+Total number of clocks in the horizontal framing period. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_INTERLACED   0x0590
+
+
+ +

+Video is interlaced. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_MISC0   0x0574
+
+
+ +

+Miscellaneous stream attributes. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_MISC1   0x0578
+
+
+ +

+Miscellaneous stream attributes. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_POLARITY   0x0558
+
+
+ +

+Polarity for the video sync signals. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_VRES   0x0568
+
+
+ +

+Number of active lines (the vertical resolution). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_VSTART   0x0570
+
+
+ +

+Number of lines between the leading edge of the vertical sync and the first line of active data. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_VSWIDTH   0x0560
+
+
+ +

+Width of the vertical sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM3_VTOTAL   0x0554
+
+
+ +

+Total number of lines in the video frame. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_HRES   0x05B4
+
+
+ +

+Number of active pixels per line (the horizontal resolution). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_HSTART   0x05BC
+
+
+ +

+Number of clocks between the leading edge of the horizontal sync and the start of active data. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_HSWIDTH   0x05AC
+
+
+ +

+Width of the horizontal sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_HTOTAL   0x05A0
+
+
+ +

+Total number of clocks in the horizontal framing period. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_INTERLACED   0x05E0
+
+
+ +

+Video is interlaced. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_MISC0   0x05C4
+
+
+ +

+Miscellaneous stream attributes. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_MISC1   0x05C8
+
+
+ +

+Miscellaneous stream attributes. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_POLARITY   0x05A8
+
+
+ +

+Polarity for the video sync signals. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_VRES   0x05B8
+
+
+ +

+Number of active lines (the vertical resolution). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_VSTART   0x05C0
+
+
+ +

+Number of lines between the leading edge of the vertical sync and the first line of active data. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_VSWIDTH   0x05B0
+
+
+ +

+Width of the vertical sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM4_VTOTAL   0x05A4
+
+
+ +

+Total number of lines in the video frame. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_HRES   0x0194
+
+
+ +

+Number of active pixels per line (the horizontal resolution). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_HSTART   0x019C
+
+
+ +

+Number of clocks between the leading edge of the horizontal sync and the start of active data. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_HSWIDTH   0x018C
+
+
+ +

+Width of the horizontal sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_HTOTAL   0x0180
+
+
+ +

+Total number of clocks in the horizontal framing period. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_INTERLACED   0x01C0
+
+
+ +

+Video is interlaced. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_MISC0   0x01A4
+
+
+ +

+Miscellaneous stream attributes. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_MISC1   0x01A8
+
+
+ +

+Miscellaneous stream attributes. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_POLARITY   0x0188
+
+
+ +

+Polarity for the video sync signals. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_VRES   0x0198
+
+
+ +

+Number of active lines (the vertical resolution). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_VSTART   0x01A0
+
+
+ +

+Number of lines between the leading edge of the vertical sync and the first line of active data. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_VSWIDTH   0x0190
+
+
+ +

+Width of the vertical sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAM_VTOTAL   0x0184
+
+
+ +

+Total number of lines in the video frame. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0
+
+
+ +

+Bit depth per color component (BDC). +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT   5
+
+
+ +

+Shift bits for BDC. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006
+
+
+ +

+Component format. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1
+
+
+ +

+Shift bits for component format. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008
+
+
+ +

+Dynamic range. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3
+
+
+ +

+Shift bits for dynamic range. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001
+
+
+ +

+Synchronous clock. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010
+
+
+ +

+YCbCr colorimetry. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4
+
+
+ +

+Shift bits for YCbCr colorimetry. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001
+
+
+ +

+Interlaced vertical total even. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006
+
+
+ +

+Stereo video attribute. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1
+
+
+ +

+Shift bits for stereo video attribute. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001
+
+
+ +

+Polarity of the horizontal sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002
+
+
+ +

+Polarity of the vertical sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1
+
+
+ +

+Shift bits for polarity of the vertical sync pulse. +

+

+ +

+
+ + + + +
#define XDPTX_MIN_BYTES_PER_TU   0x01C4
+
+
+ +

+The minimum number of bytes per transfer unit. +

+

+ +

+
+ + + + +
#define XDPTX_MIN_BYTES_PER_TU_STREAM2   0x0544
+
+
+ +

+The minimum number of bytes per transfer unit. +

+

+ +

+
+ + + + +
#define XDPTX_MIN_BYTES_PER_TU_STREAM3   0x0594
+
+
+ +

+The minimum number of bytes per transfer unit. +

+

+ +

+
+ + + + +
#define XDPTX_MIN_BYTES_PER_TU_STREAM4   0x05E4
+
+
+ +

+The minimum number of bytes per transfer unit. +

+

+ +

+
+ + + + +
#define XDPTX_N_VID   0x01B4
+
+
+ +

+N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +

+

+ +

+
+ + + + +
#define XDPTX_N_VID_STREAM2   0x0534
+
+
+ +

+N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +

+

+ +

+
+ + + + +
#define XDPTX_N_VID_STREAM3   0x0584
+
+
+ +

+N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +

+

+ +

+
+ + + + +
#define XDPTX_N_VID_STREAM4   0x05D4
+
+
+ +

+N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +

+

+ +

+
+ + + + +
#define XDPTX_PE_LEVEL_0   0x00
+
+
+ +

+Pre-emphasis level 0. +

+

+ +

+
+ + + + +
#define XDPTX_PE_LEVEL_1   0x0E
+
+
+ +

+Pre-emphasis level 1. +

+

+ +

+
+ + + + +
#define XDPTX_PE_LEVEL_2   0x14
+
+
+ +

+Pre-emphasis level 2. +

+

+ +

+
+ + + + +
#define XDPTX_PE_LEVEL_3   0x1B
+
+
+ +

+Pre-emphasis level 3. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CLOCK_SELECT   0x0234
+
+
+ +

+Instructs the PHY PLL to generate the proper clock frequency for the required link rate. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CLOCK_SELECT_162GBPS   0x1
+
+
+ +

+1.62 Gbps link. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CLOCK_SELECT_270GBPS   0x3
+
+
+ +

+2.70 Gbps link. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CLOCK_SELECT_540GBPS   0x5
+
+
+ +

+5.40 Gbps link. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG   0x0200
+
+
+ +

+Transceiver PHY reset and configuration. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0010003
+
+
+ +

+Rest GT and PHY. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0010002
+
+
+ +

+Hold GTTXRESET in reset. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0010000
+
+
+ +

+Release reset. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0010001
+
+
+ +

+Hold the PHY in reset. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x001E000
+
+
+ +

+Set TX_PHY_LOOPBACK. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0010200
+
+
+ +

+HOLD TX_PHY_PCS reset. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0010100
+
+
+ +

+Hold TX_PHY_PMA reset. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0010400
+
+
+ +

+Set TX_PHY_POLARITY. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0011000
+
+
+ +

+Set TX_PHY_PRBSFORCEERR. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_POSTCURSOR_LANE_0   0x024C
+
+
+ +

+Controls the post-cursor level. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_POSTCURSOR_LANE_1   0x0250
+
+
+ +

+Controls the post-cursor level. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_POSTCURSOR_LANE_2   0x0254
+
+
+ +

+Controls the post-cursor level. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_POSTCURSOR_LANE_3   0x0258
+
+
+ +

+Controls the post-cursor level. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_PRECURSOR_LANE_0   0x023C
+
+
+ +

+Controls the pre-cursor level. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_PRECURSOR_LANE_1   0x0240
+
+
+ +

+Controls the pre-cursor level. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_PRECURSOR_LANE_2   0x0244
+
+
+ +

+Controls the pre-cursor level. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_PRECURSOR_LANE_3   0x0248
+
+
+ +

+Controls the pre-cursor level. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS   0x0280
+
+
+ +

+Current PHY status. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F
+
+
+ +

+All lanes are ready. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000020
+
+
+ +

+FPGA fabric clock PLL locked. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010
+
+
+ +

+PLL locked for lanes 0 and 1. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020
+
+
+ +

+PLL locked for lanes 2 and 3. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003
+
+
+ +

+Reset done for lanes 0 and 1. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C
+
+
+ +

+Reset done for lanes 2 and 3. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000
+
+
+ +

+TX buffer status lane 0. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16
+
+
+ +

+Shift bits for TX buffer status lane 0. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000
+
+
+ +

+TX buffer status lane 1. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20
+
+
+ +

+Shift bits for TX buffer status lane 1. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000
+
+
+ +

+TX buffer status lane 2. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24
+
+
+ +

+Shift bits for TX buffer status lane 2. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000
+
+
+ +

+TX buffer status lane 3. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28
+
+
+ +

+Shift bits for TX buffer status lane 3. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000
+
+
+ +

+TX error on lane 0. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18
+
+
+ +

+Shift bits for TX error on lane 0. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000
+
+
+ +

+TX error on lane 1. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22
+
+
+ +

+Shift bits for TX error on lane 1. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000
+
+
+ +

+TX error on lane 2. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26
+
+
+ +

+Shift bits for TX error on lane 2. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000
+
+
+ +

+TX error on lane 3. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30
+
+
+ +

+Shift bits for TX error on lane 3. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_TRANSMIT_PRBS7   0x0230
+
+
+ +

+Enable pseudo random bit sequence 7 pattern transmission for link quality assessment. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_VOLTAGE_DIFF_LANE_0   0x0220
+
+
+ +

+Controls the differential voltage swing. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_VOLTAGE_DIFF_LANE_1   0x0224
+
+
+ +

+Controls the differential voltage swing. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_VOLTAGE_DIFF_LANE_2   0x0228
+
+
+ +

+Controls the differential voltage swing. +

+

+ +

+
+ + + + +
#define XDPTX_PHY_VOLTAGE_DIFF_LANE_3   0x022C
+
+
+ +

+Controls the differential voltage swing. +

+

+ +

+
+ + + + + + + + + + + + +
#define XDptx_ReadReg (BaseAddress,
RegOffset   )    XDptx_In32((BaseAddress) + (RegOffset))
+
+
+ +

+This is a low-level function that reads from the specified register.

+

Parameters:
+ + + +
BaseAddress is the base address of the device.
RegOffset is the register offset to be read from.
+
+
Returns:
The 32-bit value of the specified register.
+
Note:
C-style signature: u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset)
+ +
+

+ +

+
+ + + + +
#define XDPTX_REPLY_DATA_COUNT   0x0148
+
+
+ +

+Total number of data bytes actually received during a transaction. +

+

+ +

+
+ + + + +
#define XDPTX_REPLY_STATUS   0x014C
+
+
+ +

+Reply status of most recent AUX transaction. +

+

+ +

+
+ + + + +
#define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008
+
+
+ +

+Detected an error in the AUX reply of the most recent transaction. +

+

+ +

+
+ + + + +
#define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002
+
+
+ +

+AUX reply is currently being received. +

+

+ +

+
+ + + + +
#define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001
+
+
+ +

+AUX transaction is complete and a valid reply transaction received. +

+

+ +

+
+ + + + +
#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0
+
+
+ +

+Internal AUX reply state machine status bits. +

+

+ +

+
+ + + + +
#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4
+
+
+ +

+Shift bits for the internal AUX reply state machine status. +

+

+ +

+
+ + + + +
#define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004
+
+
+ +

+AUX request is currently being transmitted. +

+

+ +

+
+ + + + +
#define XDPTX_SCRAMBLING_DISABLE   0x0014
+
+
+ +

+Disable scrambler and transmit all symbols. +

+

+ +

+
+ + + + +
#define XDPTX_SOFT_RESET   0x001C
+
+
+ +

+Software reset. +

+

+ +

+
+ + + + +
#define XDPTX_SOFT_RESET_AUX_MASK   0x00000080
+
+
+ +

+Reset AUX logic. +

+

+ +

+
+ + + + +
#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001
+
+
+ +

+Reset video logic. +

+

+ +

+
+ + + + +
#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002
+
+
+ +

+Reset video logic. +

+

+ +

+
+ + + + +
#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004
+
+
+ +

+Reset video logic. +

+

+ +

+
+ + + + +
#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008
+
+
+ +

+Reset video logic. +

+

+ +

+
+ + + + +
#define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F
+
+
+ +

+Reset video logic for all streams. +

+

+ +

+
+ + + + +
#define XDPTX_STREAM0   0x01D0
+
+
+ +

+Average stream symbol timeslots per MTP config. +

+

+ +

+
+ + + + +
#define XDPTX_STREAM1   0x01D4
+
+
+ +

+Average stream symbol timeslots per MTP config. +

+

+ +

+
+ + + + +
#define XDPTX_STREAM2   0x01D8
+
+
+ +

+Average stream symbol timeslots per MTP config. +

+

+ +

+
+ + + + +
#define XDPTX_STREAM3   0x01DC
+
+
+ +

+Average stream symbol timeslots per MTP config. +

+

+ +

+
+ + + + +
#define XDPTX_TRAINING_PATTERN_SET   0x000C
+
+
+ +

+Set the link training pattern. +

+

+ +

+
+ + + + +
#define XDPTX_TRAINING_PATTERN_SET_OFF   0x0
+
+
+ +

+Training off. +

+

+ +

+
+ + + + +
#define XDPTX_TRAINING_PATTERN_SET_TP1   0x1
+
+
+ +

+Training pattern 1 used for clock recovery. +

+

+ +

+
+ + + + +
#define XDPTX_TRAINING_PATTERN_SET_TP2   0x2
+
+
+ +

+Training pattern 2 used for channel equalization. +

+

+ +

+
+ + + + +
#define XDPTX_TRAINING_PATTERN_SET_TP3   0x3
+
+
+ +

+Training pattern 3 used for channel equalization for cores with DP v1.2. +

+

+ +

+
+ + + + +
#define XDPTX_TU_SIZE   0x01B0
+
+
+ +

+Size of a transfer unit in the framing logic. +

+

+ +

+
+ + + + +
#define XDPTX_TU_SIZE_STREAM2   0x0530
+
+
+ +

+Size of a transfer unit in the framing logic. +

+

+ +

+
+ + + + +
#define XDPTX_TU_SIZE_STREAM3   0x0580
+
+
+ +

+Size of a transfer unit in the framing logic. +

+

+ +

+
+ + + + +
#define XDPTX_TU_SIZE_STREAM4   0x05D0
+
+
+ +

+Size of a transfer unit in the framing logic. +

+

+ +

+
+ + + + +
#define XDPTX_TX_AUDIO_CHANNELS   0x0304
+
+
+ +

+Used to input active channel count. +

+

+ +

+
+ + + + +
#define XDPTX_TX_AUDIO_CONTROL   0x0300
+
+
+ +

+Enables audio stream packets in main link and buffer control. +

+

+ +

+
+ + + + +
#define XDPTX_TX_AUDIO_EXT_DATA   0x0330
+
+
+ +

+Word formatted as per extension packet. +

+

+ +

+
+ + + + +
#define XDPTX_TX_AUDIO_INFO_DATA   0x0308
+
+
+ +

+Word formatted as per CEA 861-C info frame. +

+

+ +

+
+ + + + +
#define XDPTX_TX_AUDIO_MAUD   0x0328
+
+
+ +

+M value of audio stream as computed by the transmitter when audio clock and link clock are synchronous. +

+

+ +

+
+ + + + +
#define XDPTX_TX_AUDIO_NAUD   0x032C
+
+
+ +

+N value of audio stream as computed by the transmitter when audio clock and link clock are synchronous. +

+

+ +

+
+ + + + +
#define XDPTX_TX_MST_CONFIG   0x00D0
+
+
+ +

+Enable MST. +

+

+ +

+
+ + + + +
#define XDPTX_TX_MST_CONFIG_MST_EN_MASK   0x00000001
+
+
+ +

+Enable MST. +

+

+ +

+
+ + + + +
#define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002
+
+
+ +

+The VC payload has been updated in the sink. +

+

+ +

+
+ + + + +
#define XDPTX_TX_PHY_POWER_DOWN   0x0238
+
+
+ +

+Controls PHY power down. +

+

+ +

+
+ + + + +
#define XDPTX_TX_USER_FIFO_OVERFLOW   0x0110
+
+
+ +

+Indicates an overflow in user FIFO. +

+

+ +

+
+ + + + +
#define XDPTX_USER_DATA_COUNT_PER_LANE   0x01BC
+
+
+ +

+Used to translate the number of pixels per line to the native internal 16-bit datapath. +

+

+ +

+
+ + + + +
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2   0x053C
+
+
+ +

+Used to translate the number of pixels per line to the native internal 16-bit datapath. +

+

+ +

+
+ + + + +
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3   0x058C
+
+
+ +

+Used to translate the number of pixels per line to the native internal 16-bit datapath. +

+

+ +

+
+ + + + +
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4   0x05DC
+
+
+ +

+Used to translate the number of pixels per line to the native internal 16-bit datapath. +

+

+ +

+
+ + + + +
#define XDPTX_USER_PIXEL_WIDTH   0x01B8
+
+
+ +

+Selects the width of the user data input port. +

+

+ +

+
+ + + + +
#define XDPTX_USER_PIXEL_WIDTH_STREAM2   0x0538
+
+
+ +

+Selects the width of the user data input port. +

+

+ +

+
+ + + + +
#define XDPTX_USER_PIXEL_WIDTH_STREAM3   0x0588
+
+
+ +

+Selects the width of the user data input port. +

+

+ +

+
+ + + + +
#define XDPTX_USER_PIXEL_WIDTH_STREAM4   0x05D8
+
+
+ +

+Selects the width of the user data input port. +

+

+ +

+
+ + + + +
#define XDPTX_VC_PAYLOAD_BUFFER_ADDR   0x0800
+
+
+ +

+Virtual channel payload table (0xFF bytes). +

+

+ +

+
+ + + + +
#define XDPTX_VERSION   0x00F8
+
+
+ +

+Core version. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_CORE_PATCH_MASK   0x00000030
+
+
+ +

+Core patch details. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_CORE_PATCH_SHIFT   8
+
+
+ +

+Shift bits for core patch details. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_CORE_VER_MJR_MASK   0x0000F000
+
+
+ +

+Core major version. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_CORE_VER_MJR_SHIFT   24
+
+
+ +

+Shift bits for core major version. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_CORE_VER_MNR_MASK   0x00000F00
+
+
+ +

+Core minor version. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_CORE_VER_MNR_SHIFT   16
+
+
+ +

+Shift bits for core minor version. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_CORE_VER_REV_MASK   0x000000C0
+
+
+ +

+Core version revision. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_CORE_VER_REV_SHIFT   12
+
+
+ +

+Shift bits for core version revision. +

+

+ +

+
+ + + + +
#define XDPTX_VERSION_INTER_REV_MASK   0x0000000F
+
+
+ +

+Internal revision. +

+

+ +

+
+ + + + +
#define XDPTX_VS_LEVEL_0   0x2
+
+
+ +

+Voltage swing level 0. +

+

+ +

+
+ + + + +
#define XDPTX_VS_LEVEL_1   0x5
+
+
+ +

+Voltage swing level 1. +

+

+ +

+
+ + + + +
#define XDPTX_VS_LEVEL_2   0x8
+
+
+ +

+Voltage swing level 2. +

+

+ +

+
+ + + + +
#define XDPTX_VS_LEVEL_3   0xF
+
+
+ +

+Voltage swing level 3. +

+

+ +

+
+ + + + +
#define XDPTX_VS_LEVEL_OFFSET   0x4
+
+
+ +

+Voltage swing compensation offset used when there's no redriver in display path. +

+

+ +

+
+ + + + + + + + + + + + + + + +
#define XDptx_WriteReg (BaseAddress,
RegOffset,
Data   )    XDptx_Out32((BaseAddress) + (RegOffset), (Data))
+
+
+ +

+This is a low-level function that writes to the specified register.

+

Parameters:
+ + + + +
BaseAddress is the base address of the device.
RegOffset is the register offset to write to.
Data is the 32-bit data to write to the specified register.
+
+
Note:
C-style signature: void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+ +
+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__intr_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__intr_8c.html new file mode 100644 index 00000000..0b2b49e0 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__intr_8c.html @@ -0,0 +1,158 @@ + + + + + xdptx_intr.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

xdptx_intr.c File Reference

Detailed Description

+This file contains functions related to XDptx interrupt handling.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
+

+#include "xdptx.h"
+ + + + + + + + + +

Functions

void XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
void XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
void XDptx_HpdInterruptHandler (XDptx *InstancePtr)
+

Function Documentation

+ +
+
+ + + + + + + + + +
void XDptx_HpdInterruptHandler (XDptx *  InstancePtr  ) 
+
+
+ +

+This function is the interrupt handler for the XDptx driver.

+When an interrupt happens, it first detects what kind of interrupt happened, then decides which callback function to invoke.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_SetHpdEventHandler (XDptx *  InstancePtr,
XDptx_HpdEventHandler  CallbackFunc,
void *  CallbackRef 
)
+
+
+ +

+This function installs a callback function for when a hot-plug-detect event interrupt occurs.

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
CallbackFunc is the address to the callback function.
CallbackRef is the user data item that will be passed to the callback function when it is invoked.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_SetHpdPulseHandler (XDptx *  InstancePtr,
XDptx_HpdPulseHandler  CallbackFunc,
void *  CallbackRef 
)
+
+
+ +

+This function installs a callback function for when a hot-plug-detect pulse interrupt occurs.

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
CallbackFunc is the address to the callback function.
CallbackRef is the user data item that will be passed to the callback function when it is invoked.
+
+ +
+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__selftest_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__selftest_8c.html new file mode 100644 index 00000000..fd79fe0a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__selftest_8c.html @@ -0,0 +1,71 @@ + + + + + xdptx_selftest.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

xdptx_selftest.c File Reference

Detailed Description

+This file contains a diagnostic self-test function for the XDptx driver.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
+

+#include "xdptx.h"
+#include "xstatus.h"
+ + + + + +

Functions

u32 XDptx_SelfTest (XDptx *InstancePtr)
+

Function Documentation

+ +
+
+ + + + + + + + + +
u32 XDptx_SelfTest (XDptx *  InstancePtr  ) 
+
+
+ +

+This function runs a self-test on the XDptx driver/device. The test attempts to intialize the DisplayPort TX core, train the main link at the highest common capabilities between the core and the sink, and checks the status of the link after training.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Returns:
    +
  • XST_SUCCESS if the self-test passed. The main link has been trained and established successfully.
  • XST_FAILURE otherwise.
+
+ +
+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__sinit_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__sinit_8c.html new file mode 100644 index 00000000..18a0ffc1 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__sinit_8c.html @@ -0,0 +1,88 @@ + + + + + xdptx_sinit.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

xdptx_sinit.c File Reference

Detailed Description

+This file contains static initialization methods for the XDptx driver.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
+

+#include "xdptx.h"
+#include "xparameters.h"
+ + + + + + + + +

Functions

XDptx_Config * XDptx_LookupConfig (u16 DeviceId)

Variables

XDptx_Config XDptx_ConfigTable [XPAR_XDPTX_NUM_INSTANCES]
+

Function Documentation

+ +
+
+ + + + + + + + + +
XDptx_Config* XDptx_LookupConfig (u16  DeviceId  ) 
+
+
+ +

+This function looks for the device configuration based on the unique device ID. The table XDptx_ConfigTable[] contains the configuration information for each device in the system.

+

Parameters:
+ + +
DeviceId is the unique device ID of the device being looked up.
+
+
Returns:
A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.
+ +
+

+

Variable Documentation

+ +
+
+ + + + +
XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES]
+
+
+ +

+A table of configuration structures containing the configuration information for each DisplayPort TX core in the system. +

+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__spm_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__spm_8c.html new file mode 100644 index 00000000..90e392a4 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__spm_8c.html @@ -0,0 +1,261 @@ + + + + + xdptx_spm.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

xdptx_spm.c File Reference

Detailed Description

+This file contains the stream policy maker functions for the XDptx driver. These functions set up the DisplayPort TX core's main stream attributes that determine how a video stream will be displayed.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
+

+#include "xdptx.h"
+#include "xdptx_hw.h"
+#include "xstatus.h"
+ + + + + + + + + + + + + + + +

Functions

void XDptx_CfgMsaRecalculate (XDptx *InstancePtr)
u32 XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, XDptx_VideoMode VideoMode)
void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr)
void XDptx_CfgMsaUseCustom (XDptx *InstancePtr, XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
u32 XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 BitsPerColor)
void XDptx_SetVideoMode (XDptx *InstancePtr)
+

Function Documentation

+ +
+
+ + + + + + + + + +
void XDptx_CfgMsaRecalculate (XDptx *  InstancePtr  ) 
+
+
+ +

+This function calculates the following main stream attributes:

+

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance.
+
+
Note:
The MsaConfig structure is modified with the new, calculated values. The main stream attributes that were used to derive the calculated values are untouched in the MsaConfig structure.
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_CfgMsaSetBpc (XDptx *  InstancePtr,
u8  BitsPerColor 
)
+
+
+ +

+This function sets the bits per color value of the video stream.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance
BitsPerColor is the new number of bits per color to use.
+
+
Note:
The InstancePtr->MsaConfig structure is modified to reflect the new main stream attributes associated with a new bits per color value.
+
Returns:
    +
  • XST_INVALID_PARAM if the supplied bits per color value is not either 6, 8, 10, 12, or 16.
  • XST_SUCCESS otherwise.
+
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XDptx_CfgMsaUseCustom (XDptx *  InstancePtr,
XDptx_MainStreamAttributes *  MsaConfigCustom,
u8  Recalculate 
)
+
+
+ +

+This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes that must be contained in the MsaConfigCustom structure are:

+

+

Parameters:
+ + + + +
InstancePtr is a pointer to the XDptx instance.
MsaConfigCustom is the structure that will be used to copy the main stream attributes from (into InstancePtr->MsaConfig).
Recalculate is a boolean enable that determines whether or not the main stream attributes should be recalculated.
+
+
Note:
The InstancePtr-> MsaConfig structure is modified with the new values.
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *  InstancePtr  ) 
+
+
+ +

+This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. This preferred timing information is stored in the sink's extended display identification data (EDID).

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance
+
+
Note:
The InstancePtr->MsaConfig structure is modified to reflect the main stream attribute values associated to the preferred timing of the sink monitor.
+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
u32 XDptx_CfgMsaUseStandardVideoMode (XDptx *  InstancePtr,
XDptx_VideoMode  VideoMode 
)
+
+
+ +

+This function sets the main stream attribute values in the configuration structure to match one of the standard display mode timings from the XDptx_DmtModes[] table. THe XDptx_VideoMode enumeration in xdptx.h lists the available video modes.

+

Parameters:
+ + + +
InstancePtr is a pointer to the XDptx instance.
VideoMode is one of the enumerated standard video modes that is used to determine the main stream attributes to be used.
+
+
Returns:
    +
  • XST_INVALID_PARAM if the supplied video mode isn't in the DMT table.
  • XST_SUCCESS otherwise.
+
+
Note:
The InstancePtr->MsaConfig structure is modified to reflect the main stream attribute values associated to the specified video mode.
+ +
+

+ +

+
+ + + + + + + + + +
void XDptx_SetVideoMode (XDptx *  InstancePtr  ) 
+
+
+ +

+This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure.

+

Parameters:
+ + +
InstancePtr is a pointer to the XDptx instance
+
+ +
+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__vidmodetable_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__vidmodetable_8c.html new file mode 100644 index 00000000..11ac61c7 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__vidmodetable_8c.html @@ -0,0 +1,57 @@ + + + + + xdptx_vidmodetable.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ +
+
+
+
+

xdptx_vidmodetable.c File Reference

Detailed Description

+Contains display monitor timing (DMT) modes for various standard resolutions.

+

+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
+

+#include "xil_types.h"
+#include "xdptx.h"
+ + + + + +

Variables

XDptx_DmtMode XDptx_DmtModes []
+

Variable Documentation

+ +
+
+ + + + +
XDptx_DmtMode XDptx_DmtModes[]
+
+
+ +

+This table contains the main stream attributes for various standard resolutions. +

+

+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c new file mode 100644 index 00000000..ac6ec0d6 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c @@ -0,0 +1,236 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_example_common.c + * + * Contains a design example using the XDptx driver. It performs a self test on + * the DisplayPort TX core by training the main link at the maximum common + * capabilities between the TX and RX and checking the lane status. + * + * @note The DisplayPort TX core does not work alone. Some platform + * initialization will need to happen prior to calling XDptx driver + * functions. See XAPP1178 as a reference. + * + * 

+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  06/17/14 Initial creation.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx_example_common.h" +#include "xstatus.h" + +/**************************** Function Prototypes *****************************/ + +static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate); +static void Dptx_StartVideoStream(XDptx *InstancePtr); + +/**************************** Function Definitions ****************************/ + +u32 Dptx_Run(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate) +{ + u32 Status; + + Status = Dptx_StartLink(InstancePtr, LaneCount, LinkRate); + if (Status == XST_SUCCESS) { + Dptx_StartVideoStream(InstancePtr); + } else { + xil_printf("<-- Failed to train.\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId) +{ + XDptx_Config *ConfigPtr; + u32 Status; + + /* Obtain the device configuration for the DisplayPort TX core. */ + ConfigPtr = XDptx_LookupConfig(DeviceId); + if (!ConfigPtr) { + return XST_FAILURE; + } + XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr); + + /* Initialize the DisplayPort TX core. */ + Status = XDptx_InitializeTx(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate) +{ + u32 VsLevelTx; + u32 PeLevelTx; + u32 Status; + + /* Obtain the capabilities of the sink by reading the monitor's DPCD. */ + Status = XDptx_GetSinkCapabilities(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + +#if defined(USE_MAX_LINK) + Status = XDptx_CheckLinkStatus(InstancePtr, + InstancePtr->LinkConfig.MaxLaneCount); +#else + Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount); +#endif + if (Status == XST_SUCCESS) { + xil_printf("-> Does not need training.\n"); + if (XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_LINK_BW_SET) == LinkRate) { + return XST_SUCCESS; + } + } + else if (Status == XST_FAILURE) { + xil_printf("-> Needs training.\n"); + } + else { + xil_printf("-> Error checking link status.\n"); + return XST_FAILURE; + } + +#if defined(USE_MAX_LINK) + /* Configure the main link based on the common capabilities of the + * transmitter core and the sink monitor. */ + Status = XDptx_CfgMainLinkMax(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#else + XDptx_SetLinkRate(InstancePtr, LinkRate); + XDptx_SetLaneCount(InstancePtr, LaneCount); + XDptx_SetEnhancedFrameMode(InstancePtr, 1); + XDptx_SetDownspread(InstancePtr, 0); +#endif + + xil_printf("******************************************\n"); + Status = XDptx_EstablishLink(InstancePtr); + if (Status != XST_SUCCESS) { + xil_printf("!!! Training failed !!!\n"); + xil_printf("******************************************\n"); + return XST_FAILURE; + } + VsLevelTx = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_PHY_VOLTAGE_DIFF_LANE_0); + PeLevelTx = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_PHY_POSTCURSOR_LANE_0); + + xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n", + InstancePtr->LinkConfig.LinkRate, + InstancePtr->LinkConfig.LaneCount); + xil_printf("VS:%d (TX:%d) PE:%d (TX:%d)\n", + InstancePtr->LinkConfig.VsLevel, VsLevelTx, + InstancePtr->LinkConfig.PeLevel, PeLevelTx); + xil_printf("******************************************\n"); + + return XST_SUCCESS; +} + +static void Dptx_StartVideoStream(XDptx *InstancePtr) +{ + u32 Status; + u8 AuxData[1]; + + /* Set the bits per color. If not set, the default is 6. */ + XDptx_CfgMsaSetBpc(InstancePtr, 8); + +/* Choose a method for selecting the video mode. There are 3 ways to do this: + * 1) Use the preferred timing from the monitor's EDID: + * XDptx_GetEdid(InstancePtr); + * XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr); + * + * 2) Use a standard video timing mode (see mode_table.h): + * XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_VM_640x480_60_P); + * + * 3) Use a custom configuration for the main stream attributes: + * XDptx_MainStreamAttributes MsaConfigCustom; + * MsaConfigCustom.MVid = 108000; + * MsaConfigCustom.HSyncPolarity = 0; + * MsaConfigCustom.VSyncPolarity = 0; + * MsaConfigCustom.HSyncPulseWidth = 112; + * MsaConfigCustom.VSyncPulseWidth = 3; + * MsaConfigCustom.HResolution = 1280; + * MsaConfigCustom.VResolution = 1024; + * MsaConfigCustom.VBackPorch = 38; + * MsaConfigCustom.VFrontPorch = 1; + * MsaConfigCustom.HBackPorch = 248; + * MsaConfigCustom.HFrontPorch = 48; + * XDptx_CfgMsaUseCustom(InstancePtr, &MsaConfigCustom, 1); + */ + Status = XDptx_GetEdid(InstancePtr); + if (Status == XST_SUCCESS) { + XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr); + XDptx_CfgMsaUseStandardVideoMode(InstancePtr, + XDPTX_VM_640x480_60_P); + } + else { + XDptx_CfgMsaUseStandardVideoMode(InstancePtr, + XDPTX_VM_640x480_60_P); + } + + /* Disable MST for this example. */ + AuxData[0] = 0; + XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 1, AuxData); + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_TX_MST_CONFIG, + 0x0); + + /* Disable main stream to force sending of IDLE patterns. */ + XDptx_DisableMainLink(InstancePtr); + + /* Reset the transmitter. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SOFT_RESET, + XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK); + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SOFT_RESET, 0x0); + + /* Configure video stream source or generator here. This function needs + * to be implemented in order for video to be displayed and is hardware + * system specific. It is up to the user to implement this function. */ + Dptx_ConfigureVidgen(InstancePtr); + /*********************************/ + + XDptx_EnableMainLink(InstancePtr); +} diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h new file mode 100644 index 00000000..dbea1824 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h @@ -0,0 +1,83 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_example_common.h + * + * Contains a design example using the XDptx driver. It performs a self test on + * the DisplayPort TX core by training the main link at the maximum common + * capabilities between the TX and RX and checking the lane status. + * + * @note The DisplayPort TX core does not work alone. Some platform + * initialization will need to happen prior to calling XDptx driver + * functions. See XAPP1178 as a reference. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  06/17/14 Initial creation.
+ *
+ * +*******************************************************************************/ + +#ifndef XDPTX_EXAMPLE_COMMON_H_ +#define XDPTX_EXAMPLE_COMMON_H_ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xil_types.h" + +/**************************** Constant Definitions ****************************/ + +#define TRAIN_ADAPTIVE 1 +#define TRAIN_HAS_REDRIVER 1 +#define USE_MAX_LINK 1 +#define USE_LINK_RATE XDPTX_LINK_BW_SET_540GBPS +#define USE_LANE_COUNT 4 + +/**************************** Function Prototypes *****************************/ + +extern u32 Dptx_PlatformInit(void); +extern u32 Dptx_ConfigureVidgen(XDptx *InstancePtr); + +u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId); +u32 Dptx_Run(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate); + +/*************************** Variable Declarations ****************************/ + +XDptx DptxInstance; + +#endif /* XDPTX_EXAMPLE_COMMON_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c new file mode 100644 index 00000000..06089904 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c @@ -0,0 +1,245 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_intr_example.c + * + * Contains a design example using the XDptx driver with interrupts. Upon hot- + * plug-detect (DisplayPort cable is plugged/unplugged or the monitor is turned + * on/off), the main link will be trained. + * + * @note For this example to display output, the user will need to + * implement initialization of the system (Dptx_PlatformInit) and, + * after training is complete, implement configuration of the video + * stream source in order to provide the DisplayPort core with + * input (Dptx_ConfigureVidgen - called in xdptx_example_common.c). + * See XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are + * declared extern in xdptx_example_common.h and are left up to the + * user to implement. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  06/17/14 Initial creation.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xdptx_example_common.h" +#include "xil_printf.h" +#include "xparameters.h" +#include "xstatus.h" +#if defined(__MICROBLAZE__) +#include "xintc.h" +#elif defined(__arm__) +#include "xscugic.h" +#else +#error "Unknown processor type." +#endif + +/**************************** Constant Definitions ****************************/ + +#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID +#if defined(__MICROBLAZE__) +#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR +#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID +#elif defined(__arm__) +#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID +#endif + +/**************************** Function Prototypes *****************************/ + +static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, + void *IntrHandler, u32 IntrId); +static void Dptx_InterruptHandler(XDptx *InstancePtr); +static void Dptx_HpdEventHandler(void *InstancePtr); +static void Dptx_HpdPulseHandler(void *InstancePtr); + +/**************************** Variable Definitions ****************************/ + +#if defined(__MICROBLAZE__) +static XIntc IntcInstance; +#elif defined(__arm__) +static XScuGic IntcInstance; +#endif + +/**************************** Function Definitions ****************************/ + +int main(void) +{ + u32 Status; + + /* Do platform initialization here. This is hardware system specific - + * it is up to the user to implement this function. */ + Dptx_PlatformInit(); + /******************/ + + Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + +#if defined(TRAIN_ADAPTIVE) + XDptx_EnableTrainAdaptive(&DptxInstance, 1); +#else + XDptx_EnableTrainAdaptive(&DptxInstance, 0); +#endif +#if defined(TRAIN_HAS_REDRIVER) + XDptx_SetHasRedriverInPath(&DptxInstance, 1); +#else + XDptx_SetHasRedriverInPath(&DptxInstance, 0); +#endif + + /* Setup interrupt handling in the system. */ + Status = Dptx_SetupInterruptHandler(&DptxInstance, + &Dptx_InterruptHandler, DP_INTERRUPT_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Do not return in order to allow interrupt handling to run. */ + while (1); + return XST_SUCCESS; +} + +static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, + void *IntrHandler, u32 IntrId) +{ + u32 Status; +#if defined(__arm__) + XScuGic_Config *IntcConfig; +#endif + + /* Set the HPD interrupt handlers. */ + XDptx_SetHpdEventHandler(InstancePtr, &Dptx_HpdEventHandler, + InstancePtr); + XDptx_SetHpdPulseHandler(InstancePtr, &Dptx_HpdPulseHandler, + InstancePtr); + + /* Initialize interrupt controller driver. */ +#if defined(__MICROBLAZE__) + Status = XIntc_Initialize(&IntcInstance, INTC_DEVICE_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#elif defined(__arm__) + IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); + Status = XScuGic_CfgInitialize(&IntcInstance, IntcConfig, + IntcConfig->CpuBaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + XScuGic_SetPriorityTriggerType(&IntcInstance, IntrId, 0xA0, 0x1); +#endif + + /* Connect the device driver handler that will be called when an + * interrupt for the device occurs, the handler defined above performs + * the specific interrupt processing for the device. */ +#if defined(__MICROBLAZE__) + Status = XIntc_Connect(&IntcInstance, IntrId, + (XInterruptHandler)IntrHandler, InstancePtr); +#elif defined(__arm__) + Status = XScuGic_Connect(&IntcInstance, IntrId, + (Xil_InterruptHandler)IntrHandler, InstancePtr); +#endif + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Start the interrupt controller. */ +#if defined(__MICROBLAZE__) + Status = XIntc_Start(&IntcInstance, XIN_REAL_MODE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + XIntc_Enable(&IntcInstance, IntrId); +#elif defined(__arm__) + XScuGic_Enable(&IntcInstance, IntrId); +#endif + + /* Initialize the exception table. */ + Xil_ExceptionInit(); + + /* Register the interrupt controller handler with the exception table. */ +#if defined(__MICROBLAZE__) + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XIntc_InterruptHandler, &IntcInstance); +#elif defined(__arm__) + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, + (Xil_ExceptionHandler)XScuGic_InterruptHandler, &IntcInstance); +#endif + + /* Enable exceptions. */ + Xil_ExceptionEnable(); + +#if defined(__MICROBLAZE__) + /* Enable interrupts in the MicroBlaze processor. */ + microblaze_enable_interrupts(); +#endif + + return XST_SUCCESS; +} + +static void Dptx_InterruptHandler(XDptx *InstancePtr) +{ + XDptx_HpdInterruptHandler(InstancePtr); +} + +static void Dptx_HpdEventHandler(void *InstancePtr) +{ + XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + + if (XDptx_IsConnected(XDptx_InstancePtr)) { + xil_printf("+===> HPD connection event detected.\n"); + Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); + } + else { + xil_printf("+===> HPD disconnection event detected.\n\n"); + } +} + +static void Dptx_HpdPulseHandler(void *InstancePtr) +{ + XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + + xil_printf("===> HPD pulse detected.\n"); + + Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); +} diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_timer_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_timer_example.c new file mode 100644 index 00000000..769fb936 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_timer_example.c @@ -0,0 +1,271 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_intr_timer_example.c + * + * Contains a design example using the XDptx driver with interrupts. Upon hot- + * plug-detect (DisplayPort cable is plugged/unplugged or the monitor is turned + * on/off), the main link will be trained. + * + * @note For this example to display output, the user will need to + * implement initialization of the system (Dptx_PlatformInit) and, + * after training is complete, implement configuration of the video + * stream source in order to provide the DisplayPort core with + * input (Dptx_ConfigureVidgen - called in xdptx_example_common.c). + * See XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are + * declared extern in xdptx_example_common.h and are left up to the + * user to implement. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  06/17/14 Initial creation.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xdptx_example_common.h" +#include "xil_printf.h" +#include "xparameters.h" +#include "xstatus.h" +#include "xtmrctr.h" +#if defined(__MICROBLAZE__) +#include "xintc.h" +#elif defined(__arm__) +#include "xscugic.h" +#else +#error "Unknown processor type." +#endif + +/**************************** Constant Definitions ****************************/ + +#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID +#if defined(__MICROBLAZE__) +#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR +#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID +#elif defined(__arm__) +#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID +#endif + +/**************************** Function Prototypes *****************************/ + +static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, + void *IntrHandler, u32 IntrId); +static void Dptx_InterruptHandler(XDptx *InstancePtr); +static void Dptx_HpdEventHandler(void *InstancePtr); +static void Dptx_HpdPulseHandler(void *InstancePtr); + +static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds); + +/**************************** Variable Definitions ****************************/ + +#if defined(__MICROBLAZE__) +XIntc IntcInstance; +#elif defined(__arm__) +XScuGic IntcInstance; +#endif +XTmrCtr TimerCounterInst; + +/**************************** Function Definitions ****************************/ + +int main(void) +{ + u32 Status; + + /* Do platform initialization here. This is hardware system specific - + * it is up to the user to implement this function. */ + Dptx_PlatformInit(); + /******************/ + + /* Set a custom timer handler for improved delay accuracy. + * Note: This only has an affect for MicroBlaze systems. */ + XDptx_SetUserTimerHandler(&DptxInstance, &Dptx_CustomWaitUs, + &TimerCounterInst); + + Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + +#if defined(TRAIN_ADAPTIVE) + XDptx_EnableTrainAdaptive(&DptxInstance, 1); +#else + XDptx_EnableTrainAdaptive(&DptxInstance, 0); +#endif +#if defined(TRAIN_HAS_REDRIVER) + XDptx_SetHasRedriverInPath(&DptxInstance, 1); +#else + XDptx_SetHasRedriverInPath(&DptxInstance, 0); +#endif + + /* Setup interrupt handling in the system. */ + Status = Dptx_SetupInterruptHandler(&DptxInstance, + &Dptx_InterruptHandler, DP_INTERRUPT_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Do not return in order to allow interrupt handling to run. */ + while (1); + return XST_SUCCESS; +} + +static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, + void *IntrHandler, u32 IntrId) +{ + u32 Status; +#if defined(__arm__) + XScuGic_Config *IntcConfig; +#endif + + /* Set the HPD interrupt handlers. */ + XDptx_SetHpdEventHandler(InstancePtr, &Dptx_HpdEventHandler, + InstancePtr); + XDptx_SetHpdPulseHandler(InstancePtr, &Dptx_HpdPulseHandler, + InstancePtr); + + /* Initialize interrupt controller driver. */ +#if defined(__MICROBLAZE__) + Status = XIntc_Initialize(&IntcInstance, INTC_DEVICE_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#elif defined(__arm__) + IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); + Status = XScuGic_CfgInitialize(&IntcInstance, IntcConfig, + IntcConfig->CpuBaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + XScuGic_SetPriorityTriggerType(&IntcInstance, IntrId, 0xA0, 0x1); +#endif + + /* Connect the device driver handler that will be called when an + * interrupt for the device occurs, the handler defined above performs + * the specific interrupt processing for the device. */ +#if defined(__MICROBLAZE__) + Status = XIntc_Connect(&IntcInstance, IntrId, + (XInterruptHandler)IntrHandler, InstancePtr); +#elif defined(__arm__) + Status = XScuGic_Connect(&IntcInstance, IntrId, + (Xil_InterruptHandler)IntrHandler, InstancePtr); +#endif + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Start the interrupt controller. */ +#if defined(__MICROBLAZE__) + Status = XIntc_Start(&IntcInstance, XIN_REAL_MODE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + XIntc_Enable(&IntcInstance, IntrId); +#elif defined(__arm__) + XScuGic_Enable(&IntcInstance, IntrId); +#endif + + /* Initialize the exception table. */ + Xil_ExceptionInit(); + + /* Register the interrupt controller handler with the exception table. */ +#if defined(__MICROBLAZE__) + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XIntc_InterruptHandler, &IntcInstance); +#elif defined(__arm__) + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, + (Xil_ExceptionHandler)XScuGic_InterruptHandler, &IntcInstance); +#endif + + /* Enable exceptions. */ + Xil_ExceptionEnable(); + +#if defined(__MICROBLAZE__) + /* Enable interrupts in the MicroBlaze processor. */ + microblaze_enable_interrupts(); +#endif + + return XST_SUCCESS; +} + +static void Dptx_InterruptHandler(XDptx *InstancePtr) +{ + XDptx_HpdInterruptHandler(InstancePtr); +} + +static void Dptx_HpdEventHandler(void *InstancePtr) +{ + XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + + if (XDptx_IsConnected(XDptx_InstancePtr)) { + xil_printf("+===> HPD connection event detected.\n"); + Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); + } + else { + xil_printf("+===> HPD disconnection event detected.\n\n"); + } +} + +static void Dptx_HpdPulseHandler(void *InstancePtr) +{ + XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + + xil_printf("===> HPD pulse detected.\n"); + + Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); +} + +static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) +{ + XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + u32 TimerVal; + + XTmrCtr_Start(XDptx_InstancePtr->UserTimerPtr, 0); + + /* Wait specified number of useconds. */ + do { + TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0); + } + while (TimerVal < (MicroSeconds * + (XDptx_InstancePtr->TxConfig.SAxiClkHz / 1000000))); + + XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0); +} diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c new file mode 100644 index 00000000..a6b35eb2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c @@ -0,0 +1,156 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_poll_example.c + * + * Contains a design example using the XDptx driver with polling. Once the + * polling detects a hot-plug-detect event (DisplayPort cable is plugged/ + * unplugged or the monitor is turned on/off), the main link will be trained. + * + * @note For this example to display output, the user will need to + * implement initialization of the system (Dptx_PlatformInit) and, + * after training is complete, implement configuration of the video + * stream source in order to provide the DisplayPort core with + * input (Dptx_ConfigureVidgen - called in xdptx_example_common.c). + * See XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are + * declared extern in xdptx_example_common.h and are left up to the + * user to implement. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  06/17/14 Initial creation.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xdptx_example_common.h" +#include "xparameters.h" +#include "xstatus.h" + +/**************************** Constant Definitions ****************************/ + +#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID + +/**************************** Function Prototypes *****************************/ + +static void Dptx_HpdPoll(XDptx *InstancePtr); + +/**************************** Function Definitions ****************************/ + +int main(void) +{ + u32 Status; + + /* Do platform initialization here. This is hardware system specific - + * it is up to the user to implement this function. */ + Dptx_PlatformInit(); + /******************/ + + Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + +#if defined(TRAIN_ADAPTIVE) + XDptx_EnableTrainAdaptive(&DptxInstance, 1); +#else + XDptx_EnableTrainAdaptive(&DptxInstance, 0); +#endif +#if defined(TRAIN_HAS_REDRIVER) + XDptx_SetHasRedriverInPath(&DptxInstance, 1); +#else + XDptx_SetHasRedriverInPath(&DptxInstance, 0); +#endif + + /* A receiver must be connected at this point. */ + while (1) { + /* Continuously poll for HPD events. */ + Dptx_HpdPoll(&DptxInstance); + } + + return XST_SUCCESS; +} + +static void Dptx_HpdPoll(XDptx *InstancePtr) +{ + u32 InterruptSignalState; + u32 InterruptStatus; + u32 HpdState; + u32 HpdEvent; + u32 HpdPulseDetected; + u32 HpdDuration; + + /* Read interrupt registers. */ + InterruptSignalState = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_INTERRUPT_SIG_STATE); + InterruptStatus = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_INTERRUPT_STATUS); + + /* Check for HPD events. */ + HpdState = InterruptSignalState & + XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK; + HpdEvent = InterruptStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK; + HpdPulseDetected = InterruptStatus & + XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK; + if (HpdPulseDetected) { + HpdDuration = XDptx_ReadReg(InstancePtr, XDPTX_HPD_DURATION); + } + + /* HPD event handling. */ + if (HpdState && HpdEvent) { + xil_printf("+===> HPD connection event detected.\n"); + + /* Initiate link training. */ + Dptx_Run(&DptxInstance, USE_LANE_COUNT, USE_LINK_RATE); + } + else if (HpdState && HpdPulseDetected && (HpdDuration >= 250)) { + xil_printf("===> HPD pulse detected.\n"); + + /* Re-train if needed. */ + Dptx_Run(InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); + } + else if (!HpdState && HpdEvent) { + xil_printf("+===> HPD disconnection event detected.\n\n"); + + /* Disable main link. */ + XDptx_DisableMainLink(InstancePtr); + } +} diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c new file mode 100644 index 00000000..b0b01fdb --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c @@ -0,0 +1,105 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_selftest_example.c + * + * Contains a design example using the XDptx driver. It performs a self test on + * the DisplayPort TX core by training the main link at the maximum common + * capabilities between the TX and RX and checking the lane status. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  06/17/14 Initial creation.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xdptx_example_common.h" +#include "xil_printf.h" +#include "xparameters.h" +#include "xstatus.h" + +/**************************** Constant Definitions ****************************/ + +#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID + +/**************************** Function Prototypes *****************************/ + +static u32 Dptx_SelfTestExample(u16 DeviceId); + +/**************************** Function Definitions ****************************/ + +int main(void) +{ + u32 Status; + + Status = Dptx_SelfTestExample(DPTX_DEVICE_ID); + if (Status != XST_SUCCESS) { + xil_printf("XDptx_SelfTest failed.\n"); + return XST_FAILURE; + } + xil_printf("XDptx_SelfTest passed.\n"); + return Status; +} + +static u32 Dptx_SelfTestExample(u16 DeviceId) +{ + u32 Status; + + Status = Dptx_SetupExample(&DptxInstance, DeviceId); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + +#if defined(TRAIN_ADAPTIVE) + XDptx_EnableTrainAdaptive(&DptxInstance, 1); +#else + XDptx_EnableTrainAdaptive(&DptxInstance, 0); +#endif +#if defined(TRAIN_HAS_REDRIVER) + XDptx_SetHasRedriverInPath(&DptxInstance, 1); +#else + XDptx_SetHasRedriverInPath(&DptxInstance, 0); +#endif + + /* Run the self test. */ + Status = XDptx_SelfTest(&DptxInstance); + return Status; +} diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c new file mode 100644 index 00000000..12f0d8e8 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c @@ -0,0 +1,138 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_timer_example.c + * + * Contains a design example using the XDptx driver with a user-defined hook + * for delay. The reasoning behind this is that MicroBlaze sleep is not very + * accurate without a hardware timer. For systems that have a hardware timer, + * the user may override the default MicroBlaze sleep with a function that will + * use the hardware timer. + * + * @note For this example to display output, the user will need to + * implement initialization of the system (Dptx_PlatformInit) and, + * after training is complete, implement configuration of the video + * stream source in order to provide the DisplayPort core with + * input (Dptx_ConfigureVidgen - called in xdptx_example_common.c). + * See XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are + * declared extern in xdptx_example_common.h and are left up to the + * user to implement. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  06/17/14 Initial creation.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xdptx_example_common.h" +#include "xparameters.h" +#include "xstatus.h" +#include "xtmrctr.h" + +/**************************** Constant Definitions ****************************/ + +#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID + +/**************************** Function Prototypes *****************************/ + +static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds); + +/*************************** Variable Declarations ****************************/ + +XTmrCtr TimerCounterInst; + +/**************************** Function Definitions ****************************/ + +int main(void) +{ + u32 Status; + + /* Do platform initialization here. This is hardware system specific - + * it is up to the user to implement this function. */ + Dptx_PlatformInit(); + /*******************/ + + /* Set a custom timer handler for improved delay accuracy. + * Note: This only has an affect for MicroBlaze systems. */ + XDptx_SetUserTimerHandler(&DptxInstance, &Dptx_CustomWaitUs, + &TimerCounterInst); + + Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + +#if defined(TRAIN_ADAPTIVE) + XDptx_EnableTrainAdaptive(&DptxInstance, 1); +#else + XDptx_EnableTrainAdaptive(&DptxInstance, 0); +#endif +#if defined(TRAIN_HAS_REDRIVER) + XDptx_SetHasRedriverInPath(&DptxInstance, 1); +#else + XDptx_SetHasRedriverInPath(&DptxInstance, 0); +#endif + + /* A receiver must be connected at this point. */ + Dptx_Run(&DptxInstance, USE_LANE_COUNT, USE_LINK_RATE); + + /* Do not return in order to keep the program running. */ + while (1); + return XST_SUCCESS; +} + +static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) +{ + XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + u32 TimerVal; + + XTmrCtr_Start(XDptx_InstancePtr->UserTimerPtr, 0); + + /* Wait specified number of useconds. */ + do { + TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0); + } + while (TimerVal < (MicroSeconds * + (XDptx_InstancePtr->TxConfig.SAxiClkHz / 1000000))); + + XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0); +} diff --git a/XilinxProcessorIPLib/drivers/dptx/src/Makefile b/XilinxProcessorIPLib/drivers/dptx/src/Makefile new file mode 100755 index 00000000..a0e0c61a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xdptx_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling dptx" + +xdptx_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xdptx_includes + +xdptx_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c new file mode 100644 index 00000000..3c04f124 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c @@ -0,0 +1,2424 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx.c + * + * Contains a minimal wset of functions for the XDptx driver that allow access + * to all the DisplayPort transmitter's functionality. See xdptx.h for a + * detailed description of the driver. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  05/17/14 Initial release.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xstatus.h" +#if defined(__MICROBLAZE__) +#include "microblaze_sleep.h" +#elif defined(__arm__) +#include "sleep.h" +#endif +#include "xenv.h" + +/**************************** Constant Definitions ****************************/ + +#define XDPTX_MAXIMUM_VS_LEVEL 3 +#define XDPTX_MAXIMUM_PE_LEVEL 3 + +#define XDPTX_AUX_MAX_DEFER_COUNT 50 +#define XDPTX_AUX_MAX_TIMEOUT_COUNT 50 + +/****************************** Type Definitions ******************************/ + +/** + * This typedef enumerates the list of training states used in the state machine + * during the link training process. + */ +typedef enum { + XDPTX_TS_CLOCK_RECOVERY, + XDPTX_TS_CHANNEL_EQUALIZATION, + XDPTX_TS_ADJUST_LINK_RATE, + XDPTX_TS_ADJUST_LANE_COUNT, + XDPTX_TS_FAILURE, + XDPTX_TS_SUCCESS +} XDptx_TrainingState; + +/** + * This typedef describes an AUX transaction. + */ +typedef struct { + u16 CmdCode; + u8 NumBytes; + u32 Address; + u8 *ReadData; + u8 *WriteData; +} XDptx_AuxTransaction; + +/**************************** Function Prototypes *****************************/ + +/* Training functions. */ +static u32 XDptx_RunTraining(XDptx *InstancePtr); +static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr); +static XDptx_TrainingState XDptx_TrainingStateChannelEqualization( + XDptx *InstancePtr, u32 MaxIterations); +static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate( + XDptx *InstancePtr); +static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount( + XDptx *InstancePtr); +static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr); +static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount); +static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount); +static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr); +static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr); +static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern); +static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr, + XDptx_TrainingState TrainingState); +/* AUX transaction functions. */ +static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request); +static u32 XDptx_AuxRequestSend(XDptx *InstancePtr, + XDptx_AuxTransaction *Request); +static u32 XDptx_AuxWaitReply(XDptx *InstancePtr); +/* Miscellaneous functions. */ +static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed); +static u32 XDptx_WaitPhyReady(XDptx *InstancePtr); + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * This function prepares the DisplayPort TX core for use. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS if the DisplayPort TX core was successfully + * initialized. + * - XST_INVALID_PARAM if the supplied link rate does not + * correspond to either 1.62, 2.70, or 5.40 Gbps. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_InitializeTx(XDptx *InstancePtr) +{ + u32 Status; + u32 RegVal; + XDptx_Config *TxConfig = &InstancePtr->TxConfig; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + /* Place the PHY (and GTTXRESET) into reset. */ + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CONFIG, + XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK); + + /* Disable the transmitter. */ + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_ENABLE, 0); + + /* Set the clock divider. */ + RegVal = (XDptx_ReadReg(TxConfig->BaseAddr, XDPTX_AUX_CLK_DIVIDER) & + ~XDPTX_AUX_CLK_DIVIDER_VAL_MASK) | + (TxConfig->SAxiClkHz / 1000000); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_AUX_CLK_DIVIDER, RegVal); + + /* Set the transmitter's clock speed. */ + switch (TxConfig->MaxLinkRate) { + case XDPTX_LINK_BW_SET_540GBPS: + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CLOCK_SELECT, + XDPTX_PHY_CLOCK_SELECT_540GBPS); + break; + case XDPTX_LINK_BW_SET_270GBPS: + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CLOCK_SELECT, + XDPTX_PHY_CLOCK_SELECT_270GBPS); + break; + case XDPTX_LINK_BW_SET_162GBPS: + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CLOCK_SELECT, + XDPTX_PHY_CLOCK_SELECT_162GBPS); + break; + default: + return XST_INVALID_PARAM; + } + + /* Bring the PHY (and GTTXRESET) out of reset. */ + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CONFIG, + XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); + + /* Wait for the PHY to be ready. */ + Status = XDptx_WaitPhyReady(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Enable the transmitter. */ + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_ENABLE, 1); + + /* Unmask hot-plug-detect (HPD) interrupts. */ + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_INTERRUPT_MASK, + ~XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK & + ~XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK & + ~XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function retrieves the configuration for this DisplayPort TX instance + * and fills in the InstancePtr->TxConfig structure. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param ConfigPtr is a pointer to the configuration structure that will + * be used to copy the settings from. + * @param EffectiveAddr is the device base address in the virtual memory + * space. If the address translation is not used, then the physical + * address is passed. + * + * @note Unexpected errors may occur if the address mapping is changed + * after this function is invoked. + * +*******************************************************************************/ +void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr, + u32 EffectiveAddr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(ConfigPtr != NULL); + Xil_AssertVoid(EffectiveAddr != 0x0); + + InstancePtr->IsReady = 0; + + InstancePtr->TxConfig.DeviceId = ConfigPtr->DeviceId; + InstancePtr->TxConfig.BaseAddr = EffectiveAddr; + InstancePtr->TxConfig.SAxiClkHz = ConfigPtr->SAxiClkHz; + + InstancePtr->TxConfig.MaxLinkRate = ConfigPtr->MaxLinkRate; + InstancePtr->TxConfig.MaxLaneCount = ConfigPtr->MaxLaneCount; + + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; +} + +/******************************************************************************/ +/** + * This function retrieves sink device capabilities from the receiver's DPCD. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS if the DPCD was read successfully. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_GetSinkCapabilities(XDptx *InstancePtr) +{ + u32 Status; + u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField; + XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + XDptx_Config *TxConfig = &InstancePtr->TxConfig; + u8 RxMaxLinkRate; + u8 RxMaxLaneCount; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_RECEIVER_CAP_FIELD_START, + XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE, Dpcd); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + RxMaxLinkRate = Dpcd[XDPTX_DPCD_MAX_LINK_RATE]; + RxMaxLaneCount = Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] & + XDPTX_DPCD_MAX_LANE_COUNT_MASK; + LinkConfig->MaxLinkRate = (RxMaxLinkRate > TxConfig->MaxLinkRate) ? + TxConfig->MaxLinkRate : RxMaxLinkRate; + LinkConfig->MaxLaneCount = (RxMaxLaneCount > TxConfig->MaxLaneCount) ? + TxConfig->MaxLaneCount : RxMaxLaneCount; + + LinkConfig->SupportEnhancedFramingMode = + Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] & + XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK; + LinkConfig->SupportDownspreadControl = + Dpcd[XDPTX_DPCD_MAX_DOWNSPREAD] & + XDPTX_DPCD_MAX_DOWNSPREAD_MASK; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function retrieves the receiver's EDID. + * + * @param InstancePtr is a pointer to the XDptx instance. + * +*******************************************************************************/ +u32 XDptx_GetEdid(XDptx *InstancePtr) +{ + u32 Status; + + Status = XDptx_IicRead(InstancePtr, XDPTX_EDID_ADDR, 0, XDPTX_EDID_SIZE, + InstancePtr->RxConfig.Edid); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function determines the common capabilities between the DisplayPort TX + * core and the receiver. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS if main link settings were successfully set. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_INVALID_PARAM if the specified link configuration + * specifies a link rate or lane count that isn't valid. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr) +{ + u32 Status; + XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + /* Configure the main link to the maximum common link rate between the + * transmitter and the sink device. */ + Status = XDptx_SetLinkRate(InstancePtr, LinkConfig->MaxLinkRate); + if (Status != XST_SUCCESS) { + return Status; + } + + /* Configure the main link to the maximum common lane count between the + * transmitter and the sink device. */ + Status = XDptx_SetLaneCount(InstancePtr, LinkConfig->MaxLaneCount); + if (Status != XST_SUCCESS) { + return Status; + } + + /* Configure enhanced frame mode for the main link if both the + * transmitter and sink device. */ + Status = XDptx_SetEnhancedFrameMode(InstancePtr, + LinkConfig->SupportEnhancedFramingMode); + if (Status != XST_SUCCESS) { + return Status; + } + + /* Configure downspreading for the main link if both the transmitter + * and sink device. */ + Status = XDptx_SetDownspread(InstancePtr, + LinkConfig->SupportDownspreadControl); + if (Status != XST_SUCCESS) { + return Status; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function determines the common capabilities between the DisplayPort TX + * core and the receiver. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS was either already trained, or has been + * trained successfully. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_INVALID_PARAM if the current link rate or lane count + * isn't valid. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_EstablishLink(XDptx *InstancePtr) +{ + u32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + switch (InstancePtr->LinkConfig.LinkRate) { + case XDPTX_LINK_BW_SET_540GBPS: + case XDPTX_LINK_BW_SET_270GBPS: + case XDPTX_LINK_BW_SET_162GBPS: + /* Link rate is valid. */ + break; + default: + return XST_INVALID_PARAM; + } + /* Lane count gets verified while checking the link status. */ + + Status = XDptx_CheckLinkStatus(InstancePtr, + InstancePtr->LinkConfig.LaneCount); + if (Status != XST_FAILURE) { + return Status; + } + + XDptx_ResetPhy(InstancePtr, XDPTX_PHY_CONFIG_PHY_RESET_MASK); + + XDptx_DisableMainLink(InstancePtr); + + /* Train main link. */ + Status = XDptx_RunTraining(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + XDptx_EnableMainLink(InstancePtr); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function checks if the reciever's DPCD indicates the reciever has + * achieved and maintained clock recovery, channel equalization, symbol lock, + * and interlane alignment for all lanes currently in use. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param LaneCount is the number of lanes to check. + * + * @return + * - XST_SUCCESS if the receiver has maintained clock recovery, + * channel equalization, symbol lock, and interlane alignment. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_INVALID_PARAM if the number of lanes to check does not + match 1, 2, or 4 lanes. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount) +{ + u8 RetryCount = 0; + XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + u32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if ((LaneCount != 1) && (LaneCount != 2) && (LaneCount != 4)) { + return XST_INVALID_PARAM; + } + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + /* Retrieve AUX info. */ + do { + /* Get lane and adjustment requests. */ + Status = XDptx_GetLaneStatusAdjReqs(InstancePtr); + if (Status != XST_SUCCESS) { + /* The AUX read failed. */ + return XST_FAILURE; + } + + /* Check if the link needs training. */ + if ((XDptx_CheckClockRecovery( + InstancePtr, LaneCount) == XST_SUCCESS) && + (XDptx_CheckChannelEqualization( + InstancePtr, LaneCount) == XST_SUCCESS)) { + return XST_SUCCESS; + } + + RetryCount++; + } + while (RetryCount < 5); /* Retry up to 5 times. */ + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * This function enables or disables downshifting during the training process. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Enable controls the downshift feature in the training process. + * +*******************************************************************************/ +void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + InstancePtr->TrainAdaptive = Enable; +} + +/******************************************************************************/ +/** + * This function sets a software switch that signifies whether or not a redriver + * exists on the DisplayPort output path. XDptx_SetVswingPreemp uses this switch + * to determine which set of voltage swing and pre-emphasis values to use in the + * TX core. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Set establishes that a redriver exists in the DisplayPort output + * path. + * +*******************************************************************************/ +void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + InstancePtr->HasRedriverInPath = Set; +} + +/******************************************************************************/ +/** + * This function issues a read request over the AUX channel. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Address is the starting address to read from the receiver. + * @param NumBytes is the number of bytes to read from the receiver. + * @param Data is a pointer to the data buffer that will be filled with + * read data. + * + * @return + * - XST_SUCCESS if the AUX read request was successfully + * acknowledged. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_NO_DATA if no data was provided. + * - XST_ERROR_COUNT_MAX if the AUX request timed out. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data) +{ + XDptx_AuxTransaction Request; + u32 Status; + u32 Index; + u8 *DataToRead = (u8 *)Data; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Address <= 0xFFFFF); + Xil_AssertNonvoid(NumBytes <= 0xFFFFF); + Xil_AssertNonvoid(Data != NULL); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + if (Data == NULL) { + return XST_NO_DATA; + } + + /* Setup command. */ + Request.CmdCode = XDPTX_AUX_CMD_READ; + Request.Address = Address; + Request.NumBytes = NumBytes; + + Status = XDptx_AuxRequest(InstancePtr, &Request); + if (Status != XST_SUCCESS) { + return Status; + } + + for (Index = 0; Index < NumBytes; Index++) { + DataToRead[Index] = XDptx_ReadReg( + InstancePtr->TxConfig.BaseAddr, XDPTX_AUX_REPLY_DATA); + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function issues a write request over the AUX channel. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Address is the starting address to write to the receiver. + * @param NumBytes is the number of bytes to write to the receiver. + * @param Data is a pointer to the data buffer that contains the data + * to be written to the receiver. + * + * @return + * - XST_SUCCESS if AUX write request was successfully + * acknowledged. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_NO_DATA if no data was provided. + * - XST_ERROR_COUNT_MAX if the AUX request timed out. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data) +{ + u32 Status; + XDptx_AuxTransaction Request; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Address <= 0xFFFFF); + Xil_AssertNonvoid(NumBytes <= 0xFFFFF); + Xil_AssertNonvoid(Data != NULL); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + if (Data == NULL) { + return XST_NO_DATA; + } + + /* Setup command. */ + Request.CmdCode = XDPTX_AUX_CMD_WRITE; + Request.Address = Address; + Request.NumBytes = NumBytes; + Request.WriteData = (u8 *)Data; + + Status = XDptx_AuxRequest(InstancePtr, &Request); + if (Status != XST_SUCCESS) { + return Status; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function performs an I2C write over the AUX channel. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param IicAddress is the address on the I2C bus of the target device. + * @param RegStartAddress is the sub-address of the targeted I2C device + * that the write will start at. + * @param NumBytes is the number of bytes to write. + * @param DataBuffer is a pointer to a buffer which will be used as the + * data source for the write. + * + * @return + * - XST_SUCCESS if the I2C write has successfully completed with + * no errors. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_ERROR_COUNT_MAX if the AUX request timed out. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, + u8 NumBytes, u8 *DataBuffer) +{ + u32 Status; + XDptx_AuxTransaction Request; + u32 BytesLeftToWrite; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(IicAddress <= 0xFFFFF); + Xil_AssertNonvoid(RegStartAddress <= 256); + Xil_AssertNonvoid(NumBytes <= 256); + Xil_AssertNonvoid(DataBuffer != NULL); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + BytesLeftToWrite = NumBytes; + Request.Address = IicAddress; + + /* Setup the I2C-over-AUX write transaction with the address. */ + Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT; + Request.NumBytes = 1; + Request.WriteData = &RegStartAddress; + + Status = XDptx_AuxRequest(InstancePtr, &Request); + if (Status != XST_SUCCESS) { + return Status; + } + + while (BytesLeftToWrite > 0) { + if (BytesLeftToWrite > 16) { + Request.NumBytes = 16; + } + else { + Request.NumBytes = BytesLeftToWrite; + } + Request.WriteData = &DataBuffer[NumBytes - BytesLeftToWrite]; + BytesLeftToWrite -= Request.NumBytes; + + if (BytesLeftToWrite == 0) { + /* This is the last write request. */ + Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE; + } + else { + /* Middle of a transaction write request. */ + Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT; + } + + Status = XDptx_AuxRequest(InstancePtr, &Request); + if (Status != XST_SUCCESS) { + return Status; + } + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function performs an I2C read over the AUX channel. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param IicAddress is the address on the I2C bus of the target device. + * @param RegStartAddress is the subaddress of the targeted I2C device + * that the read will start from. + * @param NumBytes is the number of bytes to read. + * @param DataBuffer is a pointer to a buffer that will be filled with + * the I2C read data. + * + * @return + * - XST_SUCCESS if the I2C read has successfully completed with no + * errors. + * - XST_ERROR_COUNT_MAX if the AUX request timed out. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, + u8 NumBytes, u8 *DataBuffer) +{ + u32 Status; + XDptx_AuxTransaction Request; + u32 BytesLeftToRead; + u32 BytesToRead; + u32 Index = 0; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(IicAddress <= 0xFFFFF); + Xil_AssertNonvoid(RegStartAddress <= 128); + Xil_AssertNonvoid(NumBytes <= 128); + Xil_AssertNonvoid(DataBuffer != NULL); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + BytesLeftToRead = NumBytes; + Request.Address = IicAddress; + + /* Setup the I2C-over-AUX read transaction with the address. */ + Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT; + Request.NumBytes = 1; + Request.WriteData = &RegStartAddress; + + Status = XDptx_AuxRequest(InstancePtr, &Request); + if (Status != XST_SUCCESS) { + return Status; + } + + while (BytesLeftToRead > 0) { + if (BytesLeftToRead > 16) { + Request.NumBytes = 16; + } + else { + Request.NumBytes = BytesLeftToRead; + } + BytesLeftToRead -= Request.NumBytes; + + if (BytesLeftToRead == 0) { + /* This is the last read request. */ + Request.CmdCode = XDPTX_AUX_CMD_I2C_READ; + } + else { + /* Middle of a transaction read request. */ + Request.CmdCode = XDPTX_AUX_CMD_I2C_READ_MOT; + } + + Status = XDptx_AuxRequest(InstancePtr, &Request); + if (Status != XST_SUCCESS) { + return Status; + } + + BytesToRead = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_REPLY_DATA_COUNT); + while (BytesToRead > 0) { + DataBuffer[Index] = XDptx_ReadReg( + InstancePtr->TxConfig.BaseAddr, + XDPTX_AUX_REPLY_DATA); + Index++; + + BytesToRead--; + } + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function enables or disables 0.5% spreading of the clock for both the + * DisplayPort and the sink device. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Enable will enable or disable down-spread control. + * + * @return + * - XST_SUCCESS if setting the downspread control enable was + * successful. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable) +{ + u32 Status; + u8 RegVal; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + InstancePtr->LinkConfig.DownspreadControl = (Enable) ? 1 : 0; + + /* Write downspread enable to the transmitter. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_DOWNSPREAD_CTRL, + InstancePtr->LinkConfig.DownspreadControl); + + /* Preserve the current receiver settings. */ + Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 1, + &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + if (InstancePtr->LinkConfig.DownspreadControl) { + RegVal |= XDPTX_DPCD_SPREAD_AMP_MASK; + } + else { + RegVal &= ~XDPTX_DPCD_SPREAD_AMP_MASK; + } + + /* Write downspread enable to the sink device. */ + Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 1, + &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function enables or disables the enhanced framing symbol sequence for + * both the DisplayPort TX core and the sink device. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Enable will enable or disable enhanced frame mode. + * + * @return + * - XST_SUCCESS if setting the enhanced frame mode enable was + * successful. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable) +{ + u32 Status; + u8 RegVal; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + InstancePtr->LinkConfig.EnhancedFramingMode = (Enable) ? 1 : 0; + + /* Write enhanced frame mode enable to the transmitter. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENHANCED_FRAME_EN, + InstancePtr->LinkConfig.EnhancedFramingMode); + + /* Preserve the current receiver settings. */ + Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1, + &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + if (InstancePtr->LinkConfig.EnhancedFramingMode) { + RegVal |= XDPTX_DPCD_ENHANCED_FRAME_EN_MASK; + } + else { + RegVal &= ~XDPTX_DPCD_ENHANCED_FRAME_EN_MASK; + } + + /* Write enhanced frame mode enable to the sink device. */ + Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1, + &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the number of lanes to be used by the main link for both + * the DisplayPort TX core and the sink device. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param LaneCount is the number of lanes to be used over the main link. + * + * @return + * - XST_SUCCESS if setting the new lane count was successful. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_INVALID_PARAM if the supplied lane count is not either 1, + * 2, or 4 lanes. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount) +{ + u32 Status; + u8 RegVal; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if ((LaneCount != 1) && (LaneCount != 2) && (LaneCount != 4)) { + return XST_INVALID_PARAM; + } + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + InstancePtr->LinkConfig.LaneCount = LaneCount; + + /* Write the new lane count to the transmitter. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_LANE_COUNT_SET, + InstancePtr->LinkConfig.LaneCount); + + /* Preserve the current receiver settings. */ + Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1, + &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + RegVal &= ~XDPTX_DPCD_LANE_COUNT_SET_MASK; + RegVal |= InstancePtr->LinkConfig.LaneCount; + + /* Write the new lane count to the sink device. */ + Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1, + &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the data rate to be used by the main link for both the + * DisplayPort TX core and the sink device. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param LinkRate is the link rate to be used over the main link based on + * one of the following selects: + * - XDPTX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate) + * - XDPTX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate) + * - XDPTX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate) + * + * @return + * - XST_SUCCESS if setting the new link rate was successful. + * - XST_DEVICE_NOT_FOUND if no receiver is connected. + * - XST_INVALID_PARAM if the supplied link rate does not + * correspond to either 1.62, 2.70, or 5.40 Gbps. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate) +{ + u32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (!XDptx_IsConnected(InstancePtr)) { + return XST_DEVICE_NOT_FOUND; + } + + /* Write a corresponding clock frequency to the transmitter. */ + switch (LinkRate) { + case XDPTX_LINK_BW_SET_162GBPS: + Status = XDptx_SetClkSpeed(InstancePtr, + XDPTX_PHY_CLOCK_SELECT_162GBPS); + break; + case XDPTX_LINK_BW_SET_270GBPS: + Status = XDptx_SetClkSpeed(InstancePtr, + XDPTX_PHY_CLOCK_SELECT_270GBPS); + break; + case XDPTX_LINK_BW_SET_540GBPS: + Status = XDptx_SetClkSpeed(InstancePtr, + XDPTX_PHY_CLOCK_SELECT_540GBPS); + break; + default: + return XST_INVALID_PARAM; + } + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + InstancePtr->LinkConfig.LinkRate = LinkRate; + + /* Write new link rate to transmitter. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_LINK_BW_SET, + InstancePtr->LinkConfig.LinkRate); + + /* Write new link rate to sink device. */ + Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LINK_BW_SET, 1, + &InstancePtr->LinkConfig.LinkRate); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function enables or disables scrambling of symbols for both the + * DisplayPort and the sink device. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Enable will enable or disable scrambling. + * + * @return + * - XST_SUCCESS if setting the scrambling enable was successful. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable) +{ + u32 Status; + u8 RegVal; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + InstancePtr->LinkConfig.ScramblerEn = (Enable) ? 1 : 0; + + /* Write scrambler disable to the transmitter. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SCRAMBLING_DISABLE, + Enable ? 0 : 1); + + /* Preserve the current receiver settings. */ + Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + if (Enable) { + RegVal &= ~XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK; + } + else { + RegVal |= XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK; + } + + /* Write scrambler disable to the sink device. */ + Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function enables the main link. + * + * @param InstancePtr is a pointer to the XDptx instance. + * +*******************************************************************************/ +void XDptx_EnableMainLink(XDptx *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Reset the scrambler. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_FORCE_SCRAMBLER_RESET, 1); + + /* Enable the main stream. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_ENABLE_MAIN_STREAM, 1); +} + +/******************************************************************************/ +/** + * This function disables the main link. + * + * @param InstancePtr is a pointer to the XDptx instance. + * +*******************************************************************************/ +void XDptx_DisableMainLink(XDptx *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Reset the scrambler. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_FORCE_SCRAMBLER_RESET, 1); + + /* Disable the main stream. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_ENABLE_MAIN_STREAM, 0); +} + +/******************************************************************************/ +/** + * This function does a PHY reset. + * + * @param InstancePtr is a pointer to the XDptx instance. + & @param Reset is the type of reset to assert. + * +*******************************************************************************/ +void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE, 0); + + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_PHY_CONFIG, Reset); + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_PHY_CONFIG, + XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); + XDptx_WaitPhyReady(InstancePtr); + + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE, 1); +} + +/******************************************************************************/ +/** + * This function installs a custom delay/sleep function to be used by the XDdptx + * driver. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param CallbackFunc is the address to the callback function. + * @param CallbackRef is the user data item (microseconds to delay) that + * will be passed to the custom sleep/delay function when it is + * invoked. + * +*******************************************************************************/ +void XDptx_SetUserTimerHandler(XDptx *InstancePtr, + XDptx_TimerHandler CallbackFunc, void *CallbackRef) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallbackFunc != NULL); + Xil_AssertVoid(CallbackRef != NULL); + + InstancePtr->UserTimerWaitUs = CallbackFunc; + InstancePtr->UserTimerPtr = CallbackRef; +} + +/******************************************************************************/ +/** + * This function is the delay/sleep function for the XDptx driver. For the Zynq + * family, there exists native sleep functionality. For MicroBlaze however, + * there does not exist such functionality. In the MicroBlaze case, the default + * method for delaying is to use a predetermined amount of loop iterations. This + * method is prone to inaccuracy and dependent on system configuration; for + * greater accuracy, the user may supply their own delay/sleep handler, pointed + * to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a + * hardware timer is used. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param MicroSeconds is the number of microseconds to delay/sleep for. + * +*******************************************************************************/ +void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + +#if defined(__MICROBLAZE__) + if (InstancePtr->UserTimerWaitUs != NULL) { + /* Use the timer handler specified by the user for better + * accuracy. */ + InstancePtr->UserTimerWaitUs(InstancePtr, MicroSeconds); + } + else { + /* MicroBlaze sleep only has millisecond accuracy. Round up. */ + u32 MilliSeconds = (MicroSeconds + 999) / 1000; + MB_Sleep(MilliSeconds); + } +#elif defined(__arm__) + /* Wait the requested amount of time. */ + usleep(MicroSeconds); +#endif +} + +/******************************************************************************/ +/** + * This function runs the link training process. It is implemented as a state + * machine, with each state returning the next state. First, the clock recovery + * sequence will be run; if successful, the channel equalization sequence will + * run. If either the clock recovery or channel equalization sequence failed, + * the data rate or the number of lanes used will be reduced and training will + * be re-attempted. If training fails at the minimal data rate, 1.62 Gbps with + * a single lane, training will no longer re-attempt and fail. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return The next training state: + * - XST_SUCCESS if the training process succeeded. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +static u32 XDptx_RunTraining(XDptx *InstancePtr) +{ + u32 Status; + XDptx_TrainingState TrainingState = XDPTX_TS_CLOCK_RECOVERY; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Disable scrambler. */ + Status = XDptx_SetScrambler(InstancePtr, 0); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + while (1) { + switch (TrainingState) { + case XDPTX_TS_CLOCK_RECOVERY: + TrainingState = XDptx_TrainingStateClockRecovery( + InstancePtr); + break; + case XDPTX_TS_CHANNEL_EQUALIZATION: + TrainingState = XDptx_TrainingStateChannelEqualization( + InstancePtr, 5); + break; + case XDPTX_TS_ADJUST_LINK_RATE: + TrainingState = XDptx_TrainingStateAdjustLinkRate( + InstancePtr); + break; + case XDPTX_TS_ADJUST_LANE_COUNT: + TrainingState = XDptx_TrainingStateAdjustLaneCount( + InstancePtr); + break; + case XDPTX_TS_FAILURE: + return XST_FAILURE; + default: + break; + } + + if (TrainingState == XDPTX_TS_SUCCESS) { + break; + } + + if ((InstancePtr->TrainAdaptive == 0) && + ((TrainingState == XDPTX_TS_ADJUST_LANE_COUNT) || + (TrainingState == XDPTX_TS_ADJUST_LINK_RATE))) { + return XST_FAILURE; + } + } + + /* Turn off the training pattern. */ + Status = XDptx_SetTrainingPattern(InstancePtr, + XDPTX_TRAINING_PATTERN_SET_OFF); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Enable scrambler. */ + Status = XDptx_SetScrambler(InstancePtr, 1); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Final status check. */ + Status = XDptx_CheckLinkStatus(InstancePtr, + InstancePtr->LinkConfig.LaneCount); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function runs the clock recovery sequence as part of link training. The + * sequence is as follows: + * 0) Start signaling at the minimum voltage swing, pre-emphasis, and post- + * cursor levels. + * 1) Transmit training pattern 1 over the main link with symbol scrambling + * disabled. + * 2) The clock recovery loop. If clock recovery is unsuccessful after + * MaxIterations loop iterations, return. + * 2a) Wait for at least the period of time specified in the receiver's + * DPCD register, TRAINING_AUX_RD_INTERVAL. + * 2b) Check if all lanes have achieved clock recovery lock. If so, return. + * 2c) Check if the same voltage swing level has been used 5 consecutive + * times or if the maximum level has been reached. If so, return. + * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as + * requested by the receiver. + * 2e) Loop back to 2a. + * For a more detailed description of the clock recovery sequence, see section + * 3.5.1.2.1 of the DisplayPort 1.2a specification document. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XDPTX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence + * completed successfully. + * - XDPTX_TS_FAILURE if writing the drive settings to the receiver + * was unsuccesful. + * - XDPTX_TS_ADJUST_LINK_RATE if CR is unsuccessful. + * +*******************************************************************************/ +static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr) +{ + u32 Status; + u32 DelayUs; + u8 PrevVsLevel = 0; + u8 SameVsLevelCount = 0; + XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Obtain the required delay for CR as specified in the sink's DPCD. */ + DelayUs = XDptx_GetTrainingDelay(InstancePtr, XDPTX_TS_CLOCK_RECOVERY); + + /* Start CRLock. */ + + /* Transmit training pattern 1. */ + Status = XDptx_SetTrainingPattern(InstancePtr, + XDPTX_TRAINING_PATTERN_SET_TP1); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + /* Start from minimal voltage swing and pre-emphasis levels. */ + LinkConfig->VsLevel = 0; + LinkConfig->PeLevel = 0; + Status = XDptx_SetVswingPreemp(InstancePtr); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + while (1) { + /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */ + XDptx_WaitUs(InstancePtr, DelayUs); + + /* Get lane and adjustment requests. */ + Status = XDptx_GetLaneStatusAdjReqs(InstancePtr); + if (Status != XST_SUCCESS) { + /* The AUX read failed. */ + return XDPTX_TS_FAILURE; + } + + /* Check if all lanes have realized and maintained the frequency + * loc and get adjustment requests. */ + Status = XDptx_CheckClockRecovery(InstancePtr, + InstancePtr->LinkConfig.LaneCount); + if (Status == XST_SUCCESS) { + return XDPTX_TS_CHANNEL_EQUALIZATION; + } + + /* Check if training has tried, and failed, with the maximum + * voltage swing. */ + if (LinkConfig->VsLevel == XDPTX_MAXIMUM_VS_LEVEL) { + break; + } + + /* Check if the same voltage swing for each lane has been used 5 + * consecutive times. */ + if (PrevVsLevel == LinkConfig->VsLevel) { + SameVsLevelCount++; + } + else { + SameVsLevelCount = 0; + PrevVsLevel = LinkConfig->VsLevel; + } + if (SameVsLevelCount >= 5) { + break; + } + + /* Adjust the drive settings as requested by the sink device. */ + Status = XDptx_AdjVswingPreemp(InstancePtr); + if (Status != XST_SUCCESS) { + /* The AUX write failed. */ + return XDPTX_TS_FAILURE; + } + } + + return XDPTX_TS_ADJUST_LINK_RATE; +} + +/******************************************************************************/ +/** + * This function runs the channel equalization sequence as part of link + * training. The sequence is as follows: + * 0) Start signaling with the same drive settings used at the end of the + * clock recovery sequence. + * 1) Transmit training pattern 2 (or 3) over the main link with symbol + * scrambling disabled. + * 2) The channel equalization loop. If channel equalization is + * unsuccessful after MaxIterations loop iterations, return. + * 2a) Wait for at least the period of time specified in the receiver's + * DPCD register, TRAINING_AUX_RD_INTERVAL. + * 2b) Check if all lanes have achieved channel equalization, symbol lock, + * and interlane alignment. If so, return. + * 2c) Check if the same voltage swing level has been used 5 consecutive + * times or if the maximum level has been reached. If so, return. + * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as + * requested by the receiver. + * 2e) Loop back to 2a. + * For a more detailed description of the channel equalization sequence, see + * section 3.5.1.2.2 of the DisplayPort 1.2a specification document. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param MaxIterations is the maximum number of times to loop through the + * clock recovery sequence before down-shifting to a reduced data + * rate or a reduced number of lanes. + * + * @return + * - XDPTX_TS_SUCCESS if training succeeded. + * - XDPTX_TS_FAILURE if writing the drive settings to the receiver + * was unsuccesful. + * - XDPTX_TS_ADJUST_LINK_RATE if, after MaxIterations loop + * iterations, clock recovery is unsuccessful. + * +*******************************************************************************/ +static XDptx_TrainingState XDptx_TrainingStateChannelEqualization( + XDptx *InstancePtr, u32 MaxIterations) +{ + u32 Status; + u32 DelayUs; + u32 IterationCount = 0; + u8 PrevVsLevel = 0; + u8 SameVsLevelCount = 0; + XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Obtain the required delay for CE as specified in the sink's DPCD. */ + DelayUs = XDptx_GetTrainingDelay(InstancePtr, + XDPTX_TS_CHANNEL_EQUALIZATION); + + /* Start channel equalization. */ + + /* Write the current drive settings to the sink device. */ + Status = XDptx_SetVswingPreemp(InstancePtr); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + /* Transmit training pattern 2/3. */ + if (InstancePtr->RxConfig.DpcdRxCapsField[XDPTX_DPCD_MAX_LANE_COUNT] & + XDPTX_DPCD_TPS3_SUPPORT_MASK) { + Status = XDptx_SetTrainingPattern(InstancePtr, + XDPTX_TRAINING_PATTERN_SET_TP3); + } + else { + Status = XDptx_SetTrainingPattern(InstancePtr, + XDPTX_TRAINING_PATTERN_SET_TP2); + } + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + while (IterationCount < MaxIterations) { + /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */ + XDptx_WaitUs(InstancePtr, DelayUs); + + /* Get lane and adjustment requests. */ + Status = XDptx_GetLaneStatusAdjReqs(InstancePtr); + if (Status != XST_SUCCESS) { + /* The AUX read failed. */ + return XDPTX_TS_FAILURE; + } + + /* Check that all lanes still have their clocks locked. */ + Status = XDptx_CheckClockRecovery(InstancePtr, + InstancePtr->LinkConfig.LaneCount); + if (Status != XST_SUCCESS) { + break; + } + + /* Check that all lanes stihave accomplished channel equalization, + * symbol lock, and interlane alignment. */ + Status = XDptx_CheckChannelEqualization(InstancePtr, + InstancePtr->LinkConfig.LaneCount); + if (Status == XST_SUCCESS) { + return XDPTX_TS_SUCCESS; + } + + /* Check if training has tried, and failed, with the maximum + * voltage swing. */ + if (LinkConfig->VsLevel == XDPTX_MAXIMUM_VS_LEVEL) { + break; + } + + /* Check if the same voltage swing for each lane has been used 5 + * consecutive times. */ + if (PrevVsLevel == LinkConfig->VsLevel) { + SameVsLevelCount++; + } + else { + SameVsLevelCount = 0; + PrevVsLevel = LinkConfig->VsLevel; + } + if (SameVsLevelCount >= 5) { + break; + } + + /* Adjust the drive settings as requested by the sink device. */ + Status = XDptx_AdjVswingPreemp(InstancePtr); + if (Status != XST_SUCCESS) { + /* The AUX write failed. */ + return XDPTX_TS_FAILURE; + } + + IterationCount++; + } + + /* Tried MaxIteration times with no success. Try a reduced bitrate + * first, then reduce the number of lanes. */ + return XDPTX_TS_ADJUST_LINK_RATE; +} + +/******************************************************************************/ +/** + * This function is reached if either the clock recovery or the channel + * equalization process failed during training. As a result, the data rate will + * be downshifted, and training will be re-attempted (starting with clock + * recovery) at the reduced data rate. If the data rate is already at 1.62 Gbps, + * a downshift in lane count will be attempted. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return The next training state: + * - XDPTX_TS_ADJUST_LANE_COUNT if the minimal data rate is already + * in use. Re-attempt training at a reduced lane count. + * - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training. + * +*******************************************************************************/ +static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate(XDptx *InstancePtr) +{ + u32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + switch (InstancePtr->LinkConfig.LinkRate) { + case XDPTX_LINK_BW_SET_540GBPS: + Status = XDptx_SetLinkRate(InstancePtr, + XDPTX_LINK_BW_SET_270GBPS); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + return XDPTX_TS_CLOCK_RECOVERY; + case XDPTX_LINK_BW_SET_270GBPS: + Status = XDptx_SetLinkRate(InstancePtr, + XDPTX_LINK_BW_SET_162GBPS); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + return XDPTX_TS_CLOCK_RECOVERY; + default: + /* Already at the lowest link rate. Try reducing the lane + * count next. */ + break; + } + + return XDPTX_TS_ADJUST_LANE_COUNT; +} + +/******************************************************************************/ +/** + * This function is reached if either the clock recovery or the channel + * equalization process failed during training, and a minimal data rate of 1.62 + * Gbps was being used. As a result, the number of lanes in use will be reduced, + * and training will be re-attempted (starting with clock recovery) at this + * lower lane count. + * + * @note Training will be re-attempted with the maximum data rate being + * used with the reduced lane count to train at the main link at + * the maximum bandwidth possible. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return The next training state: + * - XDPTX_TS_FAILURE if only one lane is already in use. + * - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training. + * +*******************************************************************************/ +static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount( + XDptx *InstancePtr) +{ + u32 Status; + XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + switch (LinkConfig->LaneCount) { + case 4: + Status = XDptx_SetLaneCount(InstancePtr, 2); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + Status = XDptx_SetLinkRate(InstancePtr, + LinkConfig->MaxLinkRate); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + return XDPTX_TS_CLOCK_RECOVERY; + case 2: + Status = XDptx_SetLaneCount(InstancePtr, 1); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + Status = XDptx_SetLinkRate(InstancePtr, + LinkConfig->MaxLinkRate); + if (Status != XST_SUCCESS) { + return XDPTX_TS_FAILURE; + } + + return XDPTX_TS_CLOCK_RECOVERY; + default: + /* Already at the lowest lane count. Training has failed at the + * lowest lane count and link rate. */ + break; + } + + return XDPTX_TS_FAILURE; +} + +/******************************************************************************/ +/** + * This function will do a burst AUX read from the receiver over the AUX + * channel. The contents of the status registers will be stored for later use by + * XDptx_CheckClockRecovery, XDptx_CheckChannelEqualization, and + * XDptx_AdjVswingPreemp. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS if the AUX read was successful. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr) +{ + u32 Status; + u8 AuxData[6]; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Read and store 4 bytes of lane status and 2 bytes of adjustment + * requests. */ + Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_STATUS_LANE_0_1, + 6, InstancePtr->RxConfig.LaneStatusAdjReqs); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function checks if the receiver's DPCD indicates that the clock recovery + * sequence during link training was successful - the receiver's link clock and + * data recovery unit has realized and maintained the frequency lock for all + * lanes currently in use. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param LaneCount is the number of lanes to check. + * + * @return + * - XST_SUCCESS if the receiver's clock recovery PLL has achieved + * frequency lock for all lanes in use. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount) +{ + u32 Status; + u8 AuxData[6]; + + u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(LaneStatus != NULL); + + /* Check that all LANEx_CR_DONE bits are set. */ + switch (LaneCount) { + case 4: + if (!(LaneStatus[1] & + XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK)) { + return XST_FAILURE; + } + if (!(LaneStatus[1] & + XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK)) { + return XST_FAILURE; + } + /* Drop through and check lane 1. */ + case 2: + if (!(LaneStatus[0] & + XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK)) { + return XST_FAILURE; + } + /* Drop through and check lane 0. */ + case 1: + if (!(LaneStatus[0] & + XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK)) { + return XST_FAILURE; + } + default: + /* All (LaneCount) lanes have achieved clock recovery. */ + break; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function checks if the receiver's DPCD indicates that the channel + * equalization sequence during link training was successful - the receiver has + * achieved channel equalization, symbol lock, and interlane alignment for all + * lanes currently in use. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param LaneCount is the number of lanes to check. + * + * @return + * - XST_SUCCESS if the receiver has achieved channel equalization + * symbol lock, and interlane alignment for all lanes in use. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount) +{ + u32 Status; + u8 AuxData[6]; + u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(LaneStatus != NULL); + + /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */ + switch (LaneCount) { + case 4: + if (!(LaneStatus[1] & + XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK)) { + return XST_FAILURE; + } + if (!(LaneStatus[1] & + XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK)) { + return XST_FAILURE; + } + /* Drop through and check lane 1. */ + case 2: + if (!(LaneStatus[0] & + XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK)) { + return XST_FAILURE; + } + /* Drop through and check lane 0. */ + case 1: + if (!(LaneStatus[0] & + XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK)) { + return XST_FAILURE; + } + default: + /* All (LaneCount) lanes have achieved channel equalization. */ + break; + } + + /* Check that all LANEx_SYMBOL_LOCKED bits are set. */ + switch (LaneCount) { + case 4: + if (!(LaneStatus[1] & + XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK)) { + return XST_FAILURE; + } + if (!(LaneStatus[1] & + XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK)) { + return XST_FAILURE; + } + /* Drop through and check lane 1. */ + case 2: + if (!(LaneStatus[0] & + XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK)) { + return XST_FAILURE; + } + /* Drop through and check lane 0. */ + case 1: + if (!(LaneStatus[0] & + XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK)) { + return XST_FAILURE; + } + default: + /* All (LaneCount) lanes have achieved symbol lock. */ + break; + } + + /* Check that interlane alignment is done. */ + if (!(LaneStatus[2] & + XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK)) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets current voltage swing and pre-emphasis level settings from + * the LinkConfig structure to hardware. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS if writing the settings was successful. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr) +{ + u32 Status; + u8 Data; + u8 AuxData[4]; + u8 Index; + u8 VsLevelRx = InstancePtr->LinkConfig.VsLevel; + u8 PeLevelRx = InstancePtr->LinkConfig.PeLevel; + u32 VsLevel; + u32 PeLevel; + u32 VsLevels[4] = {XDPTX_VS_LEVEL_0, XDPTX_VS_LEVEL_1, + XDPTX_VS_LEVEL_2, XDPTX_VS_LEVEL_3}; + u32 PeLevels[4] = {XDPTX_PE_LEVEL_0, XDPTX_PE_LEVEL_1, + XDPTX_PE_LEVEL_2, XDPTX_PE_LEVEL_3}; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->HasRedriverInPath == 0) { + PeLevel = PeLevels[PeLevelRx]; + VsLevel = VsLevels[VsLevelRx]; + + /* Need to compensate due to lack of redriver. */ + if (PeLevelRx != 0) { + VsLevel += XDPTX_VS_LEVEL_OFFSET; + } + } + else { + /* No need to compensate since redriver does that. Can evenly + * disperse the voltage swing and pre-emphasis levels. */ + + /* Map 16 possible voltage swing levels in TX to 4 in RX. */ + VsLevel = VsLevelRx * 4 + 2; + /* Map 32 possible pre-emphasis levels in TX to 4 in RX. */ + PeLevel = PeLevelRx * 8 + 4; + } + + /* Set up the data buffer for writing to the sink device. */ + Data = (PeLevelRx << XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT) | + VsLevelRx; + /* The maximum voltage swing has been reached. */ + if (VsLevelRx == XDPTX_MAXIMUM_VS_LEVEL) { + Data |= XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK; + } + /* The maximum pre-emphasis level has been reached. */ + if (PeLevelRx == XDPTX_MAXIMUM_PE_LEVEL) { + Data |= XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK; + } + memset(AuxData, Data, InstancePtr->LinkConfig.LaneCount); + + for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) { + /* Disable pre-cursor levels. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_PHY_PRECURSOR_LANE_0 + 4 * Index, 0); + + /* Write new voltage swing levels to the TX registers. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_PHY_VOLTAGE_DIFF_LANE_0 + 4 * Index, VsLevel); + + /* Write new pre-emphasis levels to the TX registers. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_PHY_POSTCURSOR_LANE_0 + 4 * Index, PeLevel); + } + + /* Write the voltage swing and pre-emphasis levels for each lane to the + * sink device. */ + Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TRAINING_LANE0_SET, + InstancePtr->LinkConfig.LaneCount, AuxData); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function obtains adjustment requests for voltage swing and pre-emphasis + * levels from the receiver and sets these new settings. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS if the adjustment request from the receiver and + * the new settings were written successfully. + * - XST_FAILURE otherwise (an AUX transaction failed). + * +*******************************************************************************/ +static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr) +{ + u32 Status; + u8 Index; + u8 VsLevelAdjReq[4]; + u8 PeLevelAdjReq[4]; + u8 *AdjReqs = &InstancePtr->RxConfig.LaneStatusAdjReqs[4]; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(AdjReqs != NULL); + + /* Analyze the adjustment requests for changes in voltage swing and + * pre-emphasis levels. */ + VsLevelAdjReq[0] = AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK; + VsLevelAdjReq[1] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> + XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; + VsLevelAdjReq[2] = AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK; + VsLevelAdjReq[3] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> + XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; + PeLevelAdjReq[0] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> + XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; + PeLevelAdjReq[1] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> + XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; + PeLevelAdjReq[2] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> + XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; + PeLevelAdjReq[3] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> + XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; + + /* Change the drive settings to match the adjustment requests. Use the + * greatest level requested. */ + InstancePtr->LinkConfig.VsLevel = 0; + InstancePtr->LinkConfig.PeLevel = 0; + for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) { + if (VsLevelAdjReq[Index] >InstancePtr->LinkConfig.VsLevel) { + InstancePtr->LinkConfig.VsLevel = VsLevelAdjReq[Index]; + } + if (PeLevelAdjReq[Index] >InstancePtr->LinkConfig.PeLevel) { + InstancePtr->LinkConfig.PeLevel = PeLevelAdjReq[Index]; + } + } + + /* Verify that the voltage swing and pre-emphasis combination is + * allowed. Some combinations will result in a differential peak-to-peak + * voltage that is outside the permissable range. See the VESA + * DisplayPort v1.2 Specification, section 3.1.5.2. + * The valid combinations are: + * PE=0 PE=1 PE=2 PE=3 + * VS=0 Valid Valid Valid Valid + * VS=1 Valid Valid Valid + * VS=2 Valid Valid + * VS=3 Valid + */ + if (InstancePtr->LinkConfig.PeLevel > + (4 - InstancePtr->LinkConfig.VsLevel)) { + InstancePtr->LinkConfig.PeLevel = + 4 - InstancePtr->LinkConfig.VsLevel; + } + + /* Make the adjustments to both the transmitter and the sink device. */ + Status = XDptx_SetVswingPreemp(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the training pattern to be used during link training for + * both the DisplayPort TX core and the sink device. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Pattern selects the pattern to be used. One of the following: + * - XDPTX_TRAINING_PATTERN_SET_OFF + * - XDPTX_TRAINING_PATTERN_SET_TP1 + * - XDPTX_TRAINING_PATTERN_SET_TP2 + * - XDPTX_TRAINING_PATTERN_SET_TP3 + * + * @return + * - XST_SUCCESS if setting the pattern was successful. + * - XST_INVALID_PARAM if the supplied pattern select isn't valid. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern) +{ + u32 Status; + u8 RegVal; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + switch (Pattern) { + case XDPTX_TRAINING_PATTERN_SET_OFF: + case XDPTX_TRAINING_PATTERN_SET_TP1: + case XDPTX_TRAINING_PATTERN_SET_TP2: + case XDPTX_TRAINING_PATTERN_SET_TP3: + break; + default: + return XST_INVALID_PARAM; + } + + /* Write to the transmitter. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_TRAINING_PATTERN_SET, Pattern); + + /* Preserve the current receiver settings. */ + Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal); + RegVal &= ~XDPTX_DPCD_TP_SEL_MASK; + RegVal |= (Pattern & XDPTX_DPCD_TP_SEL_MASK); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Write to the sink device. */ + Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 1, + &RegVal); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function determines what the receiver's required training delay is for + * link training. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param TrainingState is the current training state; either clock + * recovery or channel equalization. + * + * @return The training delay specified in the receiver's DPCD register, + * XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL. + * +*******************************************************************************/ +static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr, + XDptx_TrainingState TrainingState) +{ + u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(Dpcd != NULL); + + switch (Dpcd[XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL]) { + case XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US: + if (TrainingState == XDPTX_TS_CLOCK_RECOVERY) { + /* Delay for the clock recovery phase. */ + return 100; + } + else { + /* Delay for the channel equalization phase. */ + return 400; + } + case XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS: + return 4000; + case XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS: + return 8000; + case XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS: + return 12000; + case XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS: + return 16000; + default: + break; + } + + /* A DPCD register value corresponding with an unknown delay should + * default to 20 ms. */ + return 20000; +} + +/******************************************************************************/ +/** + * This function submits the supplied AUX request to the sink device over the + * AUX channel. If waiting for a reply times out, or if the DisplayPort TX core + * indicates that the request was deferred, the request is sent again(up to a + * maximum specified by XDPTX_AUX_MAX_DEFER_COUNT|XDPTX_AUX_MAX_TIMEOUT_COUNT). + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Request is a pointer to an initialized XDptx_AuxTransaction + * structure containing the required information for issuing an + * AUX command, as well as a write buffer used for write commands, + * and a read buffer for read commands. + * + * @return + * - XST_SUCCESS if the request was acknowledged. + * - XST_ERROR_COUNT_MAX if resending the request exceeded the + * maximum for deferral and timeout. + * - XST_FAILURE otherwise (if the transmitter sees a NACK + * reply code or if the AUX transaction failed). + * +*******************************************************************************/ +static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request) +{ + u32 Status; + u32 DeferCount = 0; + u32 TimeoutCount = 0; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Request != NULL); + + while ((DeferCount < XDPTX_AUX_MAX_DEFER_COUNT) && + (TimeoutCount < XDPTX_AUX_MAX_TIMEOUT_COUNT)) { + /* Submit the request. */ + Status = XDptx_AuxRequestSend(InstancePtr, Request); + if (Status != XST_SUCCESS) { + /* A timeout occurred while waiting for the transmitter + * to be ready. */ + return XST_ERROR_COUNT_MAX; + } + + /* Check for a reply for the submitted request. */ + Status = XDptx_AuxWaitReply(InstancePtr); + if (Status != XST_SUCCESS) { + /* Waiting for a reply timed out. Try resending the + * request (at the top of the while loop). */ + XDptx_WaitUs(InstancePtr, 100); + TimeoutCount++; + } + else { + Status = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_AUX_REPLY_CODE); + switch (Status) { + case XDPTX_AUX_REPLY_CODE_DEFER: + case XDPTX_AUX_REPLY_CODE_I2C_DEFER: + /* The request was deferred, try resending the + * request (at the top of the while loop). */ + XDptx_WaitUs(InstancePtr, 100); + DeferCount++; + break; + case XDPTX_AUX_REPLY_CODE_NACK: + case XDPTX_AUX_REPLY_CODE_I2C_NACK: + /* The request was not acknowledged. */ + return XST_FAILURE; + default: + /* The request was acknowledged. */ + return XST_SUCCESS; + } + } + } + + /* The request was not successfully received by the sink device. */ + return XST_ERROR_COUNT_MAX; +} + +/******************************************************************************/ +/** + * This function submits the supplied AUX request to the sink device over the + * AUX channel by writing the command, the destination sink address, (the write + * buffer for write commands), and the data size to the DisplayPort TX core. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Request is a pointer to an initialized XDptx_AuxTransaction + * structure containing the required information for issuing an AUX + * command. + * + * @return + * - XST_SUCCESS if the request was acknowledged. + * - XST_ERROR_COUNT_MAX otherwise. + * +*******************************************************************************/ +static u32 XDptx_AuxRequestSend(XDptx *InstancePtr, + XDptx_AuxTransaction *Request) +{ + u32 Status; + u32 Index; + u32 Timeout = 100; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Request != NULL); + + /* Wait until the transmitter is ready. */ + do { + Status = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_INTERRUPT_SIG_STATE); + + /* Protect against an infinite loop. */ + if (!Timeout--) { + return XST_ERROR_COUNT_MAX; + } + XDptx_WaitUs(InstancePtr, 20); + } + while (Status & XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK); + + /* Set the address for the request. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_AUX_ADDRESS, + Request->Address); + + switch (Request->CmdCode) { + case XDPTX_AUX_CMD_WRITE: + case XDPTX_AUX_CMD_I2C_WRITE: + case XDPTX_AUX_CMD_I2C_WRITE_MOT: + /* Feed write data into the transmitter FIFO. */ + for (Index = 0; Index < Request->NumBytes; Index++) { + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_AUX_WRITE_FIFO, + Request->WriteData[Index]); + } + default: + break; + } + + /* Submit the command and the data size. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_AUX_CMD, + ((Request->CmdCode << XDPTX_AUX_CMD_SHIFT) | + ((Request->NumBytes - 1) & + XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK))); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function waits for a reply indicating that the most recent AUX request + * has been received by the sink device. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS if a reply from the sink device was received. + * - XST_ERROR_COUNT_MAX if a timeout has occurred. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +static u32 XDptx_AuxWaitReply(XDptx *InstancePtr) +{ + u32 Timeout = 100; + u32 StateVal; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + while (0 < Timeout) { + StateVal = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_INTERRUPT_SIG_STATE); + + /* Check for a reply. */ + if (StateVal & XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) { + return XST_SUCCESS; + } + + /* Check for a timeout. */ + if (StateVal & XDPTX_REPLY_STATUS_REPLY_ERROR_MASK) { + return XST_ERROR_COUNT_MAX; + } + + Timeout--; + XDptx_WaitUs(InstancePtr, 20); + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * This function sets the clock frequency for the DisplayPort PHY corresponding + * to a desired data rate. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param Speed determines what clock frequency will be used based on one + * of the following selects: + * - XDPTX_PHY_CLOCK_SELECT_162GBPS = 0x01 + * - XDPTX_PHY_CLOCK_SELECT_270GBPS = 0x03 + * - XDPTX_PHY_CLOCK_SELECT_540GBPS = 0x05 + * + * @return + * - XST_SUCCESS if the reset for each lane is done after the clock + * frequency has been set. + * - XST_INVALID_PARAM if the clock frequency doesn't correspond to + * an associated 1.62, 2.70, or 5.40 Gbps link rate. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed) +{ + u32 Status; + u32 RegVal; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (Speed != XDPTX_PHY_CLOCK_SELECT_162GBPS && + Speed != XDPTX_PHY_CLOCK_SELECT_270GBPS && + Speed != XDPTX_PHY_CLOCK_SELECT_540GBPS) { + return XST_INVALID_PARAM; + } + + /* Disable the transmitter first. */ + RegVal = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE); + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE, 0); + + /* Change speed of the feedback clock. */ + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_PHY_CLOCK_SELECT, Speed); + + /* Re-enable the transmitter if it was previously. */ + if (RegVal != 0) { + XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE, 1); + } + + /* Wait until the PHY is ready. */ + Status = XDptx_WaitPhyReady(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function waits for the DisplayPort PHY to come out of reset. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_ERROR_COUNT_MAX if the PHY failed to be ready. + * - XST_SUCCESS otherwise. + * +*******************************************************************************/ +static u32 XDptx_WaitPhyReady(XDptx *InstancePtr) +{ + u32 Timeout = 100; + u32 PhyStatus; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Wait until the PHY is ready. */ + do { + PhyStatus = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_PHY_STATUS) & + XDPTX_PHY_STATUS_ALL_LANES_READY_MASK; + + /* Protect against an infinite loop. */ + if (!Timeout--) { + return XST_ERROR_COUNT_MAX; + } + XDptx_WaitUs(InstancePtr, 20); + } + while (PhyStatus != XDPTX_PHY_STATUS_ALL_LANES_READY_MASK); + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h new file mode 100644 index 00000000..e8c4c476 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h @@ -0,0 +1,458 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx.h + * + * The Xilinx DisplayPort transmitter (TX) driver. + * + * The driver currently supports single-stream transport (SST) functionality. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  05/17/14 Initial release.
+ *
+ * +*******************************************************************************/ + +#ifndef XDPTX_H_ /* Prevent circular inclusions */ +#define XDPTX_H_ /* by using protection macros. */ + +/******************************* Include Files ********************************/ + +#include "xdptx_hw.h" +#include "xil_assert.h" +#include "xil_types.h" + +/******************* Macros (Inline Functions) Definitions ********************/ + +/******************************************************************************/ +/** + * This macro checks if there is a connected sink. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - TRUE if there is a connection. + * - FALSE if there is no connection. + * + * @note C-style signature: + * void XDptx_IsConnected(XDptx *InstancePtr) + * +*******************************************************************************/ +#define XDptx_IsConnected(InstancePtr) \ + (XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, \ + XDPTX_INTERRUPT_SIG_STATE) & XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK) + +/****************************** Type Definitions ******************************/ + +/** + * This typedef enumerates the list of available standard display monitor + * timings as specified in the mode_table.c file. The naming format is: + * + * XDPTX_VM___ + * + * Where RB stands for reduced blanking. + */ +typedef enum { + XDPTX_VM_640x480_60_P, + XDPTX_VM_800x600_60_P, + XDPTX_VM_848x480_60_P, + XDPTX_VM_1024x768_60_P, + XDPTX_VM_1280x768_60_P_RB, + XDPTX_VM_1280x768_60_P, + XDPTX_VM_1280x800_60_P_RB, + XDPTX_VM_1280x800_60_P, + XDPTX_VM_1280x960_60_P, + XDPTX_VM_1280x1024_60_P, + XDPTX_VM_1360x768_60_P, + XDPTX_VM_1400x1050_60_P_RB, + XDPTX_VM_1400x1050_60_P, + XDPTX_VM_1440x900_60_P_RB, + XDPTX_VM_1440x900_60_P, + XDPTX_VM_1600x1200_60_P, + XDPTX_VM_1680x1050_60_P_RB, + XDPTX_VM_1680x1050_60_P, + XDPTX_VM_1792x1344_60_P, + XDPTX_VM_1856x1392_60_P, + XDPTX_VM_1920x1200_60_P_RB, + XDPTX_VM_1920x1200_60_P, + XDPTX_VM_1920x1440_60_P, + XDPTX_VM_2560x1600_60_P_RB, + XDPTX_VM_2560x1600_60_P, + XDPTX_VM_800x600_56_P, + XDPTX_VM_1600x1200_65_P, + XDPTX_VM_1600x1200_70_P, + XDPTX_VM_1024x768_70_P, + XDPTX_VM_640x480_72_P, + XDPTX_VM_800x600_72_P, + XDPTX_VM_640x480_75_P, + XDPTX_VM_800x600_75_P, + XDPTX_VM_1024x768_75_P, + XDPTX_VM_1152x864_75_P, + XDPTX_VM_1280x768_75_P, + XDPTX_VM_1280x800_75_P, + XDPTX_VM_1280x1024_75_P, + XDPTX_VM_1400x1050_75_P, + XDPTX_VM_1440x900_75_P, + XDPTX_VM_1600x1200_75_P, + XDPTX_VM_1680x1050_75_P, + XDPTX_VM_1792x1344_75_P, + XDPTX_VM_1856x1392_75_P, + XDPTX_VM_1920x1200_75_P, + XDPTX_VM_1920x1440_75_P, + XDPTX_VM_2560x1600_75_P, + XDPTX_VM_640x350_85_P, + XDPTX_VM_640x400_85_P, + XDPTX_VM_720x400_85_P, + XDPTX_VM_640x480_85_P, + XDPTX_VM_800x600_85_P, + XDPTX_VM_1024x768_85_P, + XDPTX_VM_1280x768_85_P, + XDPTX_VM_1280x800_85_P, + XDPTX_VM_1280x960_85_P, + XDPTX_VM_1280x1024_85_P, + XDPTX_VM_1400x1050_85_P, + XDPTX_VM_1440x900_85_P, + XDPTX_VM_1600x1200_85_P, + XDPTX_VM_1680x1050_85_P, + XDPTX_VM_1920x1200_85_P, + XDPTX_VM_2560x1600_85_P, + XDPTX_VM_800x600_120_P_RB, + XDPTX_VM_1024x768_120_P_RB, + XDPTX_VM_1280x768_120_P_RB, + XDPTX_VM_1280x800_120_P_RB, + XDPTX_VM_1280x960_120_P_RB, + XDPTX_VM_1280x1024_120_P_RB, + XDPTX_VM_1360x768_120_P_RB, + XDPTX_VM_1400x1050_120_P_RB, + XDPTX_VM_1440x900_120_P_RB, + XDPTX_VM_1600x1200_120_P_RB, + XDPTX_VM_1680x1050_120_P_RB, + XDPTX_VM_1792x1344_120_P_RB, + XDPTX_VM_1856x1392_120_P_RB, + XDPTX_VM_1920x1200_120_P_RB, + XDPTX_VM_1920x1440_120_P_RB, + XDPTX_VM_2560x1600_120_P_RB, + XDPTX_VM_1366x768_60_P, + XDPTX_VM_1920x1080_60_P, + XDPTX_VM_UHD_30_P, + XDPTX_VM_720_60_P, + XDPTX_VM_480_60_P, + XDPTX_VM_UHD2_60_P, + XDPTX_VM_UHD_60, + XDPTX_VM_USE_EDID_PREFERRED, + XDPTX_VM_LAST = XDPTX_VM_USE_EDID_PREFERRED +} XDptx_VideoMode; + +/** + * This typedef contains the display monitor timing attributes for a video mode. + */ +typedef struct { + XDptx_VideoMode VideoMode; /**< Enumerated key. */ + u8 DmtId; /**< Standard DMT ID number. */ + u16 HResolution; /**< Horizontal resolution. */ + u16 VResolution; /**< Vertical resolution. */ + u32 PixelClkKhz; /**< Pixel frequency (in KHz). */ + u8 Scan; /**< Interlaced/non-interlaced. */ + u8 HSyncPolarity; /**< Horizontal polarity. */ + u8 VSyncPolarity; /**< Vertical polarity. */ + u32 HFrontPorch; /**< Horizontal front porch. */ + u32 HSyncPulseWidth; /**< Horizontal synchronization pulse + width. */ + u32 HBackPorch; /**< Horizontal back porch. */ + u32 VFrontPorch; /**< Vertical front porch. */ + u32 VSyncPulseWidth; /**< Vertical synchronization pulse + width.*/ + u32 VBackPorch; /**< Vertical back porch. */ +} XDptx_DmtMode; + +extern XDptx_DmtMode XDptx_DmtModes[]; + +/** + * This typedef contains configuration information for the DisplayPort TX core. + */ +typedef struct { + u16 DeviceId; /**< Device instance ID. */ + u32 BaseAddr; /**< The base address of the core. */ + u32 SAxiClkHz; /**< The clock frequency of the core's + S_AXI_ACLK port. */ + u8 MaxLaneCount; /**< The maximum lane count supported by this + core's instance. */ + u8 MaxLinkRate; /**< The maximum link rate supported by this + core's instance. */ + u8 MaxBitsPerColor; /**< The maximum bits/color supported by this + core's instance*/ + u8 QuadPixelEn; /**< Quad pixel support by this core's + instance. */ + u8 DualPixelEn; /**< Dual pixel support by this core's + instance. */ + u8 YOnlyEn; /**< YOnly format support by this core's + instance. */ + u8 YCrCbEn; /**< YCrCb format support by this core's + instance. */ +} XDptx_Config; + +/** + * This typedef contains configuration information about the sink. + */ +typedef struct { + u8 DpcdRxCapsField[256]; /**< The raw capabilities field + of the sink's DPCD. */ + u8 Edid[128]; /**< The sink's raw EDID. */ + u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the receiver + DPCD's status registers. The + first 4 bytes correspond to the + lane status from the receiver's + DPCD associated with clock + recovery, channel equalization, + symbol lock, and interlane + alignment. The 2 remaining bytes + represent the adjustments + requested by the DPCD. */ +} XDptx_SinkConfig; + +/** + * This typedef contains configuration information about the main link settings. + */ +typedef struct { + u8 LaneCount; /**< The current lane count of the main + link. */ + u8 LinkRate; /**< The current link rate of the main + link. */ + u8 ScramblerEn; /**< Symbol scrambling is currently in + use over the main link. */ + u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in + use over the main link. */ + u8 DownspreadControl; /**< Downspread control is currently in + use over the main link. */ + u8 MaxLaneCount; /**< The maximum lane count of the + source-sink main link. */ + u8 MaxLinkRate; /**< The maximum link rate of the + source-sink main link. */ + u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by + the receiver. */ + u8 SupportDownspreadControl; /**< Downspread control is supported by + the receiver. */ + u8 VsLevel; /**< The current voltage swing level for + each lane. */ + u8 PeLevel; /**< The current pre-emphasis/cursor + level for each lane. */ + u8 ComponentFormat; /**< The component format currently in + use over the main link. */ + u8 DynamicRange; /**< The dynamic range currently in use + over the main link. */ + u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in + use over the main link. */ + u8 SynchronousClockMode; /**< Synchronous clock mode is currently + in use over the main link. */ + u8 Pattern; /**< The current pattern currently in + use over the main link. */ +} XDptx_LinkConfig; + +/** + * This typedef contains the main stream attributes which determine how the + * video will be displayed. + */ +typedef struct { + u32 HClkTotal; + u32 VClkTotal; + u32 HSyncPulseWidth; + u32 VSyncPulseWidth; + u32 HResolution; + u32 VResolution; + u32 HSyncPolarity; + u32 VSyncPolarity; + u32 HStart; + u32 VStart; + u32 VBackPorch; + u32 VFrontPorch; + u32 HBackPorch; + u32 HFrontPorch; + u32 Misc0; + u32 Misc1; + u32 MVid; + u32 NVid; + u32 TransferUnitSize; + u32 UserPixelWidth; + u32 DataPerLane; + u32 AvgBytesPerTU; + u32 InitWait; + u32 Interlaced; + u32 BitsPerColor; +} XDptx_MainStreamAttributes; + +/******************************************************************************/ +/** + * Callback type which represents a custom timer wait handler. This is only + * used for Microblaze since it doesn't have a native sleep function. To avoid + * dependency on a hardware timer, the default wait functionality is implemented + * using loop iterations; this isn't too accurate. If a custom timer handler is + * used, the user may implement their own wait implementation using a hardware + * timer (see example/) for better accuracy. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param MicroSeconds is the number of microseconds to be passed to the + * timer function. + * +*******************************************************************************/ +typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds); + +/******************************************************************************/ +/** + * Callback type which represents the handler for a hot-plug-detect event + * interrupt. + * + * @param InstancePtr is a pointer to the XDptx instance. + * +*******************************************************************************/ +typedef void (*XDptx_HpdEventHandler)(void *InstancePtr); + +/******************************************************************************/ +/** + * Callback type which represents the handler for a hot-plug-detect pulse + * interrupt. + * + * @param InstancePtr is a pointer to the XDptx instance. + * +*******************************************************************************/ +typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr); + +/** + * The XDptx driver instance data. The user is required to allocate a variable + * of this type for every XDptx device in the system. A pointer to a variable of + * this type is then passed to the driver API functions. + */ +typedef struct { + u32 IsReady; /**< Device is initialized and + ready. */ + u8 TrainAdaptive; /**< Downshift lane count and + link rate if necessary + during training. */ + u8 HasRedriverInPath; /**< Redriver in path requires + different voltage swing + and pre-emphasis. */ + XDptx_Config TxConfig; /**< Configuration structure for + the core. */ + XDptx_SinkConfig RxConfig; /**< Configuration structure for + the sink. */ + XDptx_LinkConfig LinkConfig; /**< Configuration structure for + the main link. */ + XDptx_MainStreamAttributes MsaConfig; /**< Configuration structure for + the main stream + attributes. */ + XDptx_TimerHandler UserTimerWaitUs; /**< Custom user function for + delay/sleep. */ + void *UserTimerPtr; /**< Pointer to a timer instance + used by the custom user + delay/sleep function. */ + XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for hot- + plug-detect event + interrupts. */ + void *HpdEventCallbackRef; /**< A pointer to the user data + passed to the HPD event + callback function.*/ + XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for hot- + plug-detect pulse + interrupts. */ + void *HpdPulseCallbackRef; /**< A pointer to the user data + passed to the HPD pulse + callback function.*/ +} XDptx; + +/**************************** Function Prototypes *****************************/ + +/* xdptx.c: Setup and initialization functions. */ +u32 XDptx_InitializeTx(XDptx *InstancePtr); +void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr, + u32 EffectiveAddr); +u32 XDptx_GetSinkCapabilities(XDptx *InstancePtr); +u32 XDptx_GetEdid(XDptx *InstancePtr); + +/* xdptx.c: Link policy maker functions. */ +u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr); +u32 XDptx_EstablishLink(XDptx *InstancePtr); +u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount); +void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable); +void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set); + +/* xdptx.c: AUX transaction functions. */ +u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data); +u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data); +u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, + u8 NumBytes, u8 *DataBuffer); +u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, + u8 NumBytes, u8 *DataBuffer); + +/* xdptx.c: Functions for controlling the link configuration. */ +u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable); +u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable); +u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount); +u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate); +u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable); + +/* xdptx.c: General usage functions. */ +void XDptx_EnableMainLink(XDptx *InstancePtr); +void XDptx_DisableMainLink(XDptx *InstancePtr); +void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset); +void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds); +void XDptx_SetUserTimerHandler(XDptx *InstancePtr, + XDptx_TimerHandler CallbackFunc, void *CallbackRef); + +/* xdptx_spm.c: Stream policy maker functions. */ +void XDptx_CfgMsaRecalculate(XDptx *InstancePtr); +u32 XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, + XDptx_VideoMode VideoMode); +void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr); +void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, + XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate); +u32 XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor); +void XDptx_SetVideoMode(XDptx *InstancePtr); + +/* xdptx_intr.c: Interrupt handling functions. */ +void XDptx_SetHpdEventHandler(XDptx *InstancePtr, + XDptx_HpdEventHandler CallbackFunc, void *CallbackRef); +void XDptx_SetHpdPulseHandler(XDptx *InstancePtr, + XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef); +void XDptx_HpdInterruptHandler(XDptx *InstancePtr); + +/* xdptx_selftest.c: Self test function. */ +u32 XDptx_SelfTest(XDptx *InstancePtr); + +/* xdptx_sinit.c: Configuration extraction function.*/ +XDptx_Config *XDptx_LookupConfig(u16 DeviceId); + +#endif /* XDPTX_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h new file mode 100644 index 00000000..52c8a26b --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h @@ -0,0 +1,1336 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_hw.h + * + * This header file contains the identifiers and low-level driver functions (or + * macros) that can be used to access the device. High-level driver functions + * are defined in xdptx.h. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  05/17/14 Initial release.
+ *
+ * +*******************************************************************************/ + +#ifndef XDPTX_HW_H_ +#define XDPTX_HW_H_ + +/***************************** Include Files **********************************/ + +#include "xil_io.h" +#include "xil_types.h" + +/************************** Constant Definitions ******************************/ + +/******************************************************************************/ +/** + * Address mapping for the DPTX core. + * +*******************************************************************************/ +/** @name DPTX core registers: Link configuration field. + * @{ + */ +#define XDPTX_LINK_BW_SET 0x0000 /**< Set main link bandwidth + setting. */ +#define XDPTX_LANE_COUNT_SET 0x0004 /**< Set lane count setting. */ +#define XDPTX_ENHANCED_FRAME_EN 0x0008 /**< Enable enhanced framing + symbol sequence. */ +#define XDPTX_TRAINING_PATTERN_SET 0x000C /**< Set the link training + pattern. */ +#define XDPTX_LINK_QUAL_PATTERN_SET 0x0010 /**< Transmit the link quality + pattern. */ +#define XDPTX_SCRAMBLING_DISABLE 0x0014 /**< Disable scrambler and + transmit all symbols. */ +#define XDPTX_DOWNSPREAD_CTRL 0x0018 /**< Enable a 0.5% spreading of + the clock. */ +#define XDPTX_SOFT_RESET 0x001C /**< Software reset. */ +/* @} */ + +/** @name DPTX core registers: Core enables. + * @{ + */ +#define XDPTX_ENABLE 0x0080 /**< Enable the basic operations + of the transmitter or + output stuffing symbols + if disabled. */ +#define XDPTX_ENABLE_MAIN_STREAM 0x0084 /**< Enable transmission of main + link video info. */ +#define XDPTX_ENABLE_SEC_STREAM 0x0088 /**< Enable the transmission of + secondary link info. */ +#define XDPTX_FORCE_SCRAMBLER_RESET 0x00C0 /**< Force a scrambler reset. */ +#define XDPTX_TX_MST_CONFIG 0x00D0 /**< Enable MST. */ +/* @} */ + +/** @name DPTX core registers: Core ID. + * @{ + */ +#define XDPTX_VERSION 0x00F8 /**< Core version. */ +#define XDPTX_CORE_ID 0x00FC /**< DisplayPort revision. */ +/* @} */ + +/** @name DPTX core registers: AUX channel interface. + * @{ + */ +#define XDPTX_AUX_CMD 0x0100 /**< Initiates AUX commands. */ +#define XDPTX_AUX_WRITE_FIFO 0x0104 /**< Write data for the current + AUX command. */ +#define XDPTX_AUX_ADDRESS 0x0108 /**< Specifies the address of + current AUX command. */ +#define XDPTX_AUX_CLK_DIVIDER 0x010C /**< Clock divider value for + generating the internal + 1MHz clock. */ +#define XDPTX_TX_USER_FIFO_OVERFLOW 0x0110 /**< Indicates an overflow in + user FIFO. */ +#define XDPTX_INTERRUPT_SIG_STATE 0x0130 /**< The raw signal values for + interupt events. */ +#define XDPTX_AUX_REPLY_DATA 0x0134 /**< Reply data received during + the AUX reply. */ +#define XDPTX_AUX_REPLY_CODE 0x0138 /**< Reply code received from + the most recent AUX + command. */ +#define XDPTX_AUX_REPLY_COUNT 0x013C /**< Number of reply + transactions receieved + over AUX. */ +#define XDPTX_INTERRUPT_STATUS 0x0140 /**< Status for interrupt + events. */ +#define XDPTX_INTERRUPT_MASK 0x0144 /**< Masks the specified + interrupt sources. */ +#define XDPTX_REPLY_DATA_COUNT 0x0148 /**< Total number of data bytes + actually received during + a transaction. */ +#define XDPTX_REPLY_STATUS 0x014C /**< Reply status of most recent + AUX transaction. */ +#define XDPTX_HPD_DURATION 0x0150 /**< Duration of the HPD pulse + in microseconds. */ +/* @} */ + +/** @name DPTX core registers: Main stream attributes for SST / MST STREAM1. + * @{ + */ +#define XDPTX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in + the horizontal framing + period. */ +#define XDPTX_MAIN_STREAM_VTOTAL 0x0184 /**< Total number of lines in + the video frame. */ +#define XDPTX_MAIN_STREAM_POLARITY 0x0188 /**< Polarity for the video + sync signals. */ +#define XDPTX_MAIN_STREAM_HSWIDTH 0x018C /**< Width of the horizontal + sync pulse. */ +#define XDPTX_MAIN_STREAM_VSWIDTH 0x0190 /**< Width of the vertical sync + pulse. */ +#define XDPTX_MAIN_STREAM_HRES 0x0194 /**< Number of active pixels per + line (the horizontal + resolution). */ +#define XDPTX_MAIN_STREAM_VRES 0x0198 /**< Number of active lines (the + vertical resolution). */ +#define XDPTX_MAIN_STREAM_HSTART 0x019C /**< Number of clocks between + the leading edge of the + horizontal sync and the + start of active data. */ +#define XDPTX_MAIN_STREAM_VSTART 0x01A0 /**< Number of lines between the + leading edge of the + vertical sync and the + first line of active + data. */ +#define XDPTX_MAIN_STREAM_MISC0 0x01A4 /**< Miscellaneous stream + attributes. */ +#define XDPTX_MAIN_STREAM_MISC1 0x01A8 /**< Miscellaneous stream + attributes. */ +#define XDPTX_M_VID 0x01AC /**< M value for the video + stream as computed by + the source core in + asynchronous clock + mode. Must be written + in synchronous mode. */ +#define XDPTX_TU_SIZE 0x01B0 /**< Size of a transfer unit in + the framing logic. */ +#define XDPTX_N_VID 0x01B4 /**< N value for the video + stream as computed by + the source core in + asynchronous clock mode. + Must be written in + synchronous mode. */ +#define XDPTX_USER_PIXEL_WIDTH 0x01B8 /**< Selects the width of the + user data input port. */ +#define XDPTX_USER_DATA_COUNT_PER_LANE 0x01BC /**< Used to translate the + number of pixels per + line to the native + internal 16-bit + datapath. */ +#define XDPTX_MAIN_STREAM_INTERLACED 0x01C0 /**< Video is interlaced. */ +#define XDPTX_MIN_BYTES_PER_TU 0x01C4 /**< The minimum number of bytes + per transfer unit. */ +#define XDPTX_FRAC_BYTES_PER_TU 0x01C8 /**< The fractional component + when calculated the + XDPTX_MIN_BYTES_PER_TU + register value. */ +#define XDPTX_INIT_WAIT 0x01CC /**< Number of initial wait + cycles at the start of a + new line by the framing + logic, allowing enough + data to be buffered in + the input FIFO. */ +#define XDPTX_STREAM0 0x01D0 /**< Average stream symbol + timeslots per MTP + config. */ +#define XDPTX_STREAM1 0x01D4 /**< Average stream symbol + timeslots per MTP + config. */ +#define XDPTX_STREAM2 0x01D8 /**< Average stream symbol + timeslots per MTP + config. */ +#define XDPTX_STREAM3 0x01DC /**< Average stream symbol + timeslots per MTP + config. */ +/* @} */ + +/** @name DPTX core registers: PHY configuration status. + * @{ + */ +#define XDPTX_PHY_CONFIG 0x0200 /**< Transceiver PHY reset and + configuration. */ +#define XDPTX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 /**< Controls the differential + voltage swing. */ +#define XDPTX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 /**< Controls the differential + voltage swing. */ +#define XDPTX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 /**< Controls the differential + voltage swing. */ +#define XDPTX_PHY_VOLTAGE_DIFF_LANE_3 0x022C /**< Controls the differential + voltage swing. */ +#define XDPTX_PHY_TRANSMIT_PRBS7 0x0230 /**< Enable pseudo random bit + sequence 7 pattern + transmission for link + quality assessment. */ +#define XDPTX_PHY_CLOCK_SELECT 0x0234 /**< Instructs the PHY PLL to + generate the proper + clock frequency for the + required link rate. */ +#define XDPTX_TX_PHY_POWER_DOWN 0x0238 /**< Controls PHY power down. */ +#define XDPTX_PHY_PRECURSOR_LANE_0 0x023C /**< Controls the pre-cursor + level. */ +#define XDPTX_PHY_PRECURSOR_LANE_1 0x0240 /**< Controls the pre-cursor + level. */ +#define XDPTX_PHY_PRECURSOR_LANE_2 0x0244 /**< Controls the pre-cursor + level. */ +#define XDPTX_PHY_PRECURSOR_LANE_3 0x0248 /**< Controls the pre-cursor + level. */ +#define XDPTX_PHY_POSTCURSOR_LANE_0 0x024C /**< Controls the post-cursor + level. */ +#define XDPTX_PHY_POSTCURSOR_LANE_1 0x0250 /**< Controls the post-cursor + level. */ +#define XDPTX_PHY_POSTCURSOR_LANE_2 0x0254 /**< Controls the post-cursor + level. */ +#define XDPTX_PHY_POSTCURSOR_LANE_3 0x0258 /**< Controls the post-cursor + level. */ +#define XDPTX_PHY_STATUS 0x0280 /**< Current PHY status. */ +#define XDPTX_GT_DRP_COMMAND 0x02A0 /**< Provides acces to the GT + DRP ports. */ +#define XDPTX_GT_DRP_READ_DATA 0x02A4 /**< Provides access to GT DRP + read data. */ +#define XDPTX_GT_DRP_CHANNEL_STATUS 0x02A8 /**< Provides access to GT DRP + channel status. */ +/* @} */ + +/** @name DPTX core registers: DisplayPort audio. + * @{ + */ +#define XDPTX_TX_AUDIO_CONTROL 0x0300 /**< Enables audio stream + packets in main link and + buffer control. */ +#define XDPTX_TX_AUDIO_CHANNELS 0x0304 /**< Used to input active + channel count. */ +#define XDPTX_TX_AUDIO_INFO_DATA 0x0308 /**< Word formatted as per + CEA 861-C info frame. */ +#define XDPTX_TX_AUDIO_MAUD 0x0328 /**< M value of audio stream + as computed by the + transmitter when audio + clock and link clock are + synchronous. */ +#define XDPTX_TX_AUDIO_NAUD 0x032C /**< N value of audio stream + as computed by the + transmitter when audio + clock and link clock are + synchronous. */ +#define XDPTX_TX_AUDIO_EXT_DATA 0x0330 /**< Word formatted as per + extension packet. */ +/* @} */ + +/** @name DPTX core registers: Main stream attributes for MST STREAM2. + * @{ + */ +#define XDPTX_MAIN_STREAM2_HTOTAL 0x0500 /**< Total number of clocks in + the horizontal framing + period. */ +#define XDPTX_MAIN_STREAM2_VTOTAL 0x0504 /**< Total number of lines in + the video frame. */ +#define XDPTX_MAIN_STREAM2_POLARITY 0x0508 /**< Polarity for the video sync + signals. */ +#define XDPTX_MAIN_STREAM2_HSWIDTH 0x050C /**< Width of the horizontal + sync pulse. */ +#define XDPTX_MAIN_STREAM2_VSWIDTH 0x0510 /**< Width of the vertical sync + pulse. */ +#define XDPTX_MAIN_STREAM2_HRES 0x0514 /**< Number of active pixels per + line (the horizontal + resolution). */ +#define XDPTX_MAIN_STREAM2_VRES 0x0518 /**< Number of active lines (the + vertical resolution). */ +#define XDPTX_MAIN_STREAM2_HSTART 0x051C /**< Number of clocks between + the leading edge of the + horizontal sync and the + start of active data. */ +#define XDPTX_MAIN_STREAM2_VSTART 0x0520 /**< Number of lines between the + leading edge of the + vertical sync and the + first line of active + data. */ +#define XDPTX_MAIN_STREAM2_MISC0 0x0524 /**< Miscellaneous stream + attributes. */ +#define XDPTX_MAIN_STREAM2_MISC1 0x0528 /**< Miscellaneous stream + attributes. */ +#define XDPTX_M_VID_STREAM2 0x052C /**< M value for the video + stream as computed by + the source core in + asynchronous clock mode. + Must be written in + synchronous mode. */ +#define XDPTX_TU_SIZE_STREAM2 0x0530 /**< Size of a transfer unit in + the framing logic. */ +#define XDPTX_N_VID_STREAM2 0x0534 /**< N value for the video + stream as computed by + the source core in + asynchronous clock mode. + Must be written in + synchronous mode. */ +#define XDPTX_USER_PIXEL_WIDTH_STREAM2 0x0538 /**< Selects the width of the + user data input port. */ +#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2 \ + 0x053C /**< Used to translate the + number of pixels per + line to the native + internal 16-bit + datapath. */ +#define XDPTX_MAIN_STREAM2_INTERLACED 0x0540 /**< Video is interlaced. */ +#define XDPTX_MIN_BYTES_PER_TU_STREAM2 0x0544 /**< The minimum number of bytes + per transfer unit. */ +#define XDPTX_FRAC_BYTES_PER_TU_STREAM2 0x0548 /**< The fractional component + when calculated the + XDPTX_MIN_BYTES_PER_TU + register value. */ +#define XDPTX_INIT_WAIT_STREAM2 0x054C /**< Number of initial wait + cycles at the start of a + new line by the framing + logic, allowing enough + data to be buffered in + the input FIFO. */ +/* @} */ + +/** @name DPTX core registers: Main stream attributes for MST STREAM3. + * @{ + */ +#define XDPTX_MAIN_STREAM3_HTOTAL 0x0550 /**< Total number of clocks in + the horizontal framing + period. */ +#define XDPTX_MAIN_STREAM3_VTOTAL 0x0554 /**< Total number of lines in + the video frame. */ +#define XDPTX_MAIN_STREAM3_POLARITY 0x0558 /**< Polarity for the video sync + signals. */ +#define XDPTX_MAIN_STREAM3_HSWIDTH 0x055C /**< Width of the horizontal + sync pulse. */ +#define XDPTX_MAIN_STREAM3_VSWIDTH 0x0560 /**< Width of the vertical sync + pulse. */ +#define XDPTX_MAIN_STREAM3_HRES 0x0564 /**< Number of active pixels per + line (the horizontal + resolution). */ +#define XDPTX_MAIN_STREAM3_VRES 0x0568 /**< Number of active lines (the + vertical resolution). */ +#define XDPTX_MAIN_STREAM3_HSTART 0x056C /**< Number of clocks between + the leading edge of the + horizontal sync and the + start of active data. */ +#define XDPTX_MAIN_STREAM3_VSTART 0x0570 /**< Number of lines between the + leading edge of the + vertical sync and the + first line of active + data. */ +#define XDPTX_MAIN_STREAM3_MISC0 0x0574 /**< Miscellaneous stream + attributes. */ +#define XDPTX_MAIN_STREAM3_MISC1 0x0578 /**< Miscellaneous stream + attributes. */ +#define XDPTX_M_VID_STREAM3 0x057C /**< M value for the video + stream as computed by + the source core in + asynchronous clock mode. + Must be written in + synchronous mode. */ +#define XDPTX_TU_SIZE_STREAM3 0x0580 /**< Size of a transfer unit in + the framing logic. */ +#define XDPTX_N_VID_STREAM3 0x0584 /**< N value for the video + stream as computed by + the source core in + asynchronous clock mode. + Must be written in + synchronous mode. */ +#define XDPTX_USER_PIXEL_WIDTH_STREAM3 0x0588 /**< Selects the width of the + user data input port. */ +#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3 \ + 0x058C /**< Used to translate the + number of pixels per + line to the native + internal 16-bit + datapath. */ +#define XDPTX_MAIN_STREAM3_INTERLACED 0x0590 /**< Video is interlaced. */ +#define XDPTX_MIN_BYTES_PER_TU_STREAM3 0x0594 /**< The minimum number of bytes + per transfer unit. */ +#define XDPTX_FRAC_BYTES_PER_TU_STREAM3 0x0598 /**< The fractional component + when calculated the + XDPTX_MIN_BYTES_PER_TU + register value. */ +#define XDPTX_INIT_WAIT_STREAM3 0x059C /**< Number of initial wait + cycles at the start of a + new line by the framing + logic, allowing enough + data to be buffered in + the input FIFO. */ +/* @} */ + +/** @name DPTX core registers: Main stream attributes for MST STREAM4. + * @{ + */ +#define XDPTX_MAIN_STREAM4_HTOTAL 0x05A0 /**< Total number of clocks in + the horizontal framing + period. */ +#define XDPTX_MAIN_STREAM4_VTOTAL 0x05A4 /**< Total number of lines in + the video frame. */ +#define XDPTX_MAIN_STREAM4_POLARITY 0x05A8 /**< Polarity for the video sync + signals. */ +#define XDPTX_MAIN_STREAM4_HSWIDTH 0x05AC /**< Width of the horizontal + sync pulse. */ +#define XDPTX_MAIN_STREAM4_VSWIDTH 0x05B0 /**< Width of the vertical sync + pulse. */ +#define XDPTX_MAIN_STREAM4_HRES 0x05B4 /**< Number of active pixels per + line (the horizontal + resolution). */ +#define XDPTX_MAIN_STREAM4_VRES 0x05B8 /**< Number of active lines (the + vertical resolution). */ +#define XDPTX_MAIN_STREAM4_HSTART 0x05BC /**< Number of clocks between + the leading edge of the + horizontal sync and the + start of active data. */ +#define XDPTX_MAIN_STREAM4_VSTART 0x05C0 /**< Number of lines between the + leading edge of the + vertical sync and the + first line of active + data. */ +#define XDPTX_MAIN_STREAM4_MISC0 0x05C4 /**< Miscellaneous stream + attributes. */ +#define XDPTX_MAIN_STREAM4_MISC1 0x05C8 /**< Miscellaneous stream + attributes. */ +#define XDPTX_M_VID_STREAM4 0x05CC /**< M value for the video + stream as computed by + the source core in + asynchronous clock mode. + Must be written in + synchronous mode. */ +#define XDPTX_TU_SIZE_STREAM4 0x05D0 /**< Size of a transfer unit in + the framing logic. */ +#define XDPTX_N_VID_STREAM4 0x05D4 /**< N value for the video + stream as computed by + the source core in + asynchronous clock mode. + Must be written in + synchronous mode. */ +#define XDPTX_USER_PIXEL_WIDTH_STREAM4 0x05D8 /**< Selects the width of the + user data input port. */ +#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4 \ + 0x05DC /**< Used to translate the + number of pixels per + line to the native + internal 16-bit + datapath. */ +#define XDPTX_MAIN_STREAM4_INTERLACED 0x05E0 /**< Video is interlaced. */ +#define XDPTX_MIN_BYTES_PER_TU_STREAM4 0x05E4 /**< The minimum number of bytes + per transfer unit. */ +#define XDPTX_FRAC_BYTES_PER_TU_STREAM4 0x05E8 /**< The fractional component + when calculated the + XDPTX_MIN_BYTES_PER_TU + register value. */ +#define XDPTX_INIT_WAIT_STREAM4 0x05EC /**< Number of initial wait + cycles at the start of a + new line by the framing + logic, allowing enough + data to be buffered in + the input FIFO. */ +/* @} */ + +#define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload + table (0xFF bytes). */ + +/******************************************************************************/ + +/** @name DPTX core masks, shifts, and register values. + * @{ + */ +/* 0x000: LINK_BW_SET */ +#define XDPTX_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */ +#define XDPTX_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */ +#define XDPTX_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */ +/* 0x00C: TRAINING_PATTERN_SET */ +#define XDPTX_TRAINING_PATTERN_SET_OFF 0x0 /**< Training off. */ +#define XDPTX_TRAINING_PATTERN_SET_TP1 0x1 /**< Training pattern 1 used for + clock recovery. */ +#define XDPTX_TRAINING_PATTERN_SET_TP2 0x2 /**< Training pattern 2 used for + channel equalization. */ +#define XDPTX_TRAINING_PATTERN_SET_TP3 0x3 /**< Training pattern 3 used for + channel equalization for + cores with DP v1.2. */ +/* 0x010: LINK_QUAL_PATTERN_SET */ +#define XDPTX_LINK_QUAL_PATTERN_SET_OFF 0x0 /**< Link quality test pattern + not transmitted. */ +#define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST \ + 0x1 /**< D10.2 unscrambled test + pattern transmitted. */ +#define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES \ + 0x2 /**< Symbol error rate + measurement pattern + transmitted. */ +#define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7 \ + 0x3 /**< Pseudo random bit sequence + 7 transmitted. */ +/* 0x01C: SOFTWARE_RESET */ +#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK \ + 0x00000001 /**< Reset video logic. */ +#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK \ + 0x00000002 /**< Reset video logic. */ +#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK \ + 0x00000004 /**< Reset video logic. */ +#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK \ + 0x00000008 /**< Reset video logic. */ +#define XDPTX_SOFT_RESET_AUX_MASK \ + 0x00000080 /**< Reset AUX logic. */ +#define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK \ + 0x0000000F /**< Reset video logic for all + streams. */ +/* 0x0D0: TX_MST_CONFIG */ +#define XDPTX_TX_MST_CONFIG_MST_EN_MASK \ + 0x00000001 /**< Enable MST. */ +#define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK \ + 0x00000002 /**< The VC payload has been + updated in the sink. */ +/* 0x0F8 : VERSION_REGISTER */ +#define XDPTX_VERSION_INTER_REV_MASK \ + 0x0000000F /**< Internal revision. */ +#define XDPTX_VERSION_CORE_PATCH_MASK \ + 0x00000030 /**< Core patch details. */ +#define XDPTX_VERSION_CORE_PATCH_SHIFT \ + 8 /**< Shift bits for core patch + details. */ +#define XDPTX_VERSION_CORE_VER_REV_MASK \ + 0x000000C0 /**< Core version revision. */ +#define XDPTX_VERSION_CORE_VER_REV_SHIFT \ + 12 /**< Shift bits for core version + revision. */ +#define XDPTX_VERSION_CORE_VER_MNR_MASK \ + 0x00000F00 /**< Core minor version. */ +#define XDPTX_VERSION_CORE_VER_MNR_SHIFT \ + 16 /**< Shift bits for core minor + version. */ +#define XDPTX_VERSION_CORE_VER_MJR_MASK \ + 0x0000F000 /**< Core major version. */ +#define XDPTX_VERSION_CORE_VER_MJR_SHIFT \ + 24 /**< Shift bits for core major + version. */ +/* 0x0FC : CORE_ID */ +#define XDPTX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */ +#define XDPTX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */ +#define XDPTX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */ +#define XDPTX_CORE_ID_DP_REV_MASK \ + 0x000000F0 /**< DisplayPort protocol + revision. */ +#define XDPTX_CORE_ID_DP_REV_SHIFT \ + 8 /**< Shift bits for DisplayPort + protocol revision. */ +#define XDPTX_CORE_ID_DP_MNR_VER_MASK \ + 0x00000F00 /**< DisplayPort protocol minor + version. */ +#define XDPTX_CORE_ID_DP_MNR_VER_SHIFT \ + 16 /**< Shift bits for DisplayPort + protocol major + version. */ +#define XDPTX_CORE_ID_DP_MJR_VER_MASK \ + 0x0000F000 /**< DisplayPort protocol major + version. */ +#define XDPTX_CORE_ID_DP_MJR_VER_SHIFT \ + 24 /**< Shift bits for DisplayPort + protocol major + version. */ +/* 0x100 AUX_CMD */ +#define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK \ + 0x0000000F /**< Number of bytes to transfer + with the current AUX + command. */ +#define XDPTX_AUX_CMD_MASK 0x00000F00 /**< AUX command. */ +#define XDPTX_AUX_CMD_SHIFT 8 /**< Shift bits for command. */ +#define XDPTX_AUX_CMD_I2C_WRITE 0x0 /**< I2C-over-AUX write + command. */ +#define XDPTX_AUX_CMD_I2C_READ 0x1 /**< I2C-over-AUX read + command. */ +#define XDPTX_AUX_CMD_I2C_WRITE_STATUS 0x2 /**< I2C-over-AUX write status + command. */ +#define XDPTX_AUX_CMD_I2C_WRITE_MOT 0x4 /**< I2C-over-AUX write MOT + (middle-of-transaction) + command. */ +#define XDPTX_AUX_CMD_I2C_READ_MOT 0x5 /**< I2C-over-AUX read MOT + (middle-of-transaction) + command. */ +#define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT \ + 0x6 /**< I2C-over-AUX write status + MOT (middle-of- + transaction) command. */ +#define XDPTX_AUX_CMD_WRITE 0x8 /**< AUX write command. */ +#define XDPTX_AUX_CMD_READ 0x9 /**< AUX read command. */ +#define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN \ + 0x00001000 /**< Address only transfer + enable (STOP will be + sent after command). */ +/* 0x10C: AUX_CLK_DIVIDER */ +#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK \ + 0x0000000F /**< Clock divider value. */ +#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK \ + 0x00000F00 /**< AUX (noise) signal width + filter. */ +#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \ + 8 /**< Shift bits for AUX signal + width filter. */ +/* 0x130: INTERRUPT_SIG_STATE */ +#define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK \ + 0x00000001 /**< Raw state of the HPD pin on + the DP connector. */ +#define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK \ + 0x00000002 /**< A request is currently + being sent. */ +#define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK \ + 0x00000004 /**< A reply is currently being + received. */ +#define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK \ + 0x00000008 /**< A reply timeout has + occurred. */ +/* 0x138: AUX_REPLY_CODE */ +#define XDPTX_AUX_REPLY_CODE_ACK 0x0 /**< AUX command ACKed. */ +#define XDPTX_AUX_REPLY_CODE_I2C_ACK 0x0 /**< I2C-over-AUX command + not ACKed. */ +#define XDPTX_AUX_REPLY_CODE_NACK 0x1 /**< AUX command not ACKed. */ +#define XDPTX_AUX_REPLY_CODE_DEFER 0x2 /**< AUX command deferred. */ +#define XDPTX_AUX_REPLY_CODE_I2C_NACK 0x4 /**< I2C-over-AUX command not + ACKed. */ +#define XDPTX_AUX_REPLY_CODE_I2C_DEFER 0x8 /**< I2C-over-AUX command + deferred. */ +/* 0x140: INTERRUPT_STATUS */ +#define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK \ + 0x00000001 /**< Detected an IRQ framed with + the proper timing on the + HPD signal. */ +#define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK \ + 0x00000002 /**< Detected the presence of + the HPD signal. */ +#define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK \ + 0x00000004 /**< An AUX reply transaction + has been detected. */ +#define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK \ + 0x00000008 /**< A reply timeout has + occurred. */ +#define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK \ + 0x00000010 /**< A pulse on the HPD line was + detected. */ +#define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK \ + 0x00000020 /**< Extended packet has been + transmitted and the core + is ready to accept a new + packet. */ +/* 0x144: INTERRUPT_MASK */ +#define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK \ + 0x00000001 /**< Mask HPD IRQ interrupt. */ +#define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK \ + 0x00000002 /**< Mask HPD event + interrupt. */ +#define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK \ + 0x00000004 /**< Mask reply received + interrupt. */ +#define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK \ + 0x00000008 /**< Mask reply received + interrupt. */ +#define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK \ + 0x00000010 /**< Mask HPD pulse detected + interrupt. */ +#define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK \ + 0x00000020 /**< Mask extended packet + transmit interrupt. */ +/* 0x14C: REPLY_STATUS */ +#define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK \ + 0x00000001 /**< AUX transaction is complete + and a valid reply + transaction received. */ +#define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK \ + 0x00000002 /**< AUX reply is currently + being received. */ +#define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK \ + 0x00000004 /**< AUX request is currently + being transmitted. */ +#define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK \ + 0x00000008 /**< Detected an error in the + AUX reply of the most + recent transaction. */ +#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK \ + 0x00000FF0 /**< Internal AUX reply state + machine status bits. */ +#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT \ + 4 /**< Shift bits for the internal + AUX reply state machine + status. */ +/* 0x188, 0x508, 0x558, 0x5A8: MAIN_STREAM[0-4]_POLARITY */ +#define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK \ + 0x00000001 /**< Polarity of the horizontal + sync pulse. */ +#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK \ + 0x00000002 /**< Polarity of the vertical + sync pulse. */ +#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT \ + 1 /**< Shift bits for polarity of + the vertical sync + pulse. */ +/* 0x1A4, 0x524, 0x578, 0x5C8: MAIN_STREAM[0-4]_MISC0 */ +#define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK \ + 0x00000001 /**< Synchronous clock. */ +#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK \ + 0x00000006 /**< Component format. */ +#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT \ + 1 /**< Shift bits for component + format. */ +#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK \ + 0x00000008 /**< Dynamic range. */ +#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT \ + 3 /**< Shift bits for dynamic + range. */ +#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK \ + 0x00000010 /**< YCbCr colorimetry. */ +#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT \ + 4 /**< Shift bits for YCbCr + colorimetry. */ +#define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK \ + 0x000000E0 /**< Bit depth per color + component (BDC). */ +#define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT \ + 5 /**< Shift bits for BDC.*/ +/* 0x1A8, 0x528, 0x5C8: MAIN_STREAM[0-4]_MISC1 */ +#define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK \ + 0x00000001 /**< Interlaced vertical total + even. */ +#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK \ + 0x00000006 /**< Stereo video attribute. */ +#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT \ + 1 /**< Shift bits for stereo video + attribute. */ +/* 0x200: PHY_CONFIG */ +#define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK \ + 0x0010000 /**< Release reset. */ +#define XDPTX_PHY_CONFIG_PHY_RESET_MASK \ + 0x0010001 /**< Hold the PHY in reset. */ +#define XDPTX_PHY_CONFIG_GTTX_RESET_MASK \ + 0x0010002 /**< Hold GTTXRESET in reset. */ +#define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK \ + 0x0010100 /**< Hold TX_PHY_PMA reset. */ +#define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \ + 0x0010200 /**< HOLD TX_PHY_PCS reset. */ +#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK \ + 0x0010400 /**< Set TX_PHY_POLARITY. */ +#define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \ + 0x0011000 /**< Set TX_PHY_PRBSFORCEERR. */ +#define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK \ + 0x001E000 /**< Set TX_PHY_LOOPBACK. */ +#define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK \ + 0x0010003 /**< Rest GT and PHY. */ +/* 0x234: PHY_CLOCK_SELECT */ +#define XDPTX_PHY_CLOCK_SELECT_162GBPS 0x1 /**< 1.62 Gbps link. */ +#define XDPTX_PHY_CLOCK_SELECT_270GBPS 0x3 /**< 2.70 Gbps link. */ +#define XDPTX_PHY_CLOCK_SELECT_540GBPS 0x5 /**< 5.40 Gbps link. */ +/* 0x0220, 0x0224, 0x0228, 0x022C: XDPTX_PHY_VOLTAGE_DIFF_LANE_[0-3] */ +#define XDPTX_VS_LEVEL_0 0x2 /**< Voltage swing level 0. */ +#define XDPTX_VS_LEVEL_1 0x5 /**< Voltage swing level 1. */ +#define XDPTX_VS_LEVEL_2 0x8 /**< Voltage swing level 2. */ +#define XDPTX_VS_LEVEL_3 0xF /**< Voltage swing level 3. */ +#define XDPTX_VS_LEVEL_OFFSET 0x4 /**< Voltage swing compensation + offset used when there's + no redriver in display + path. */ +/* 0x024C, 0x0250, 0x0254, 0x0258: XDPTX_PHY_POSTCURSOR_LANE_[0-3] */ +#define XDPTX_PE_LEVEL_0 0x00 /**< Pre-emphasis level 0. */ +#define XDPTX_PE_LEVEL_1 0x0E /**< Pre-emphasis level 1. */ +#define XDPTX_PE_LEVEL_2 0x14 /**< Pre-emphasis level 2. */ +#define XDPTX_PE_LEVEL_3 0x1B /**< Pre-emphasis level 3. */ +/* 0x280: PHY_STATUS */ +#define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \ + 0x00000003 /**< Reset done for lanes + 0 and 1. */ +#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \ + 0x0000000C /**< Reset done for lanes + 2 and 3. */ +#define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK \ + 0x00000010 /**< PLL locked for lanes + 0 and 1. */ +#define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK \ + 0x00000020 /**< PLL locked for lanes + 2 and 3. */ +#define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK \ + 0x00000020 /**< FPGA fabric clock PLL + locked. */ +#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK \ + 0x00030000 /**< TX buffer status lane 0. */ +#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT \ + 16 /**< Shift bits for TX buffer + status lane 0. */ +#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK \ + 0x000C0000 /**< TX error on lane 0. */ +#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT \ + 18 /**< Shift bits for TX error on + lane 0. */ +#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK \ + 0x00300000 /**< TX buffer status lane 1. */ +#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT \ + 20 /**< Shift bits for TX buffer + status lane 1. */ +#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK \ + 0x00C00000 /**< TX error on lane 1. */ +#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT \ + 22 /**< Shift bits for TX error on + lane 1. */ +#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK \ + 0x03000000 /**< TX buffer status lane 2. */ +#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT \ + 24 /**< Shift bits for TX buffer + status lane 2. */ +#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK \ + 0x0C000000 /**< TX error on lane 2. */ +#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT \ + 26 /**< Shift bits for TX error on + lane 2. */ +#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK \ + 0x30000000 /**< TX buffer status lane 3. */ +#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT \ + 28 /**< Shift bits for TX buffer + status lane 3. */ +#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK \ + 0xC0000000 /**< TX error on lane 3. */ +#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT \ + 30 /**< Shift bits for TX error on + lane 3. */ +#define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK \ + 0x0000003F /**< All lanes are ready. */ +/* 0x2A0: XDPTX_GT_DRP_COMMAND */ +#define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK \ + 0x000F /**< DRP address. */ +#define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK \ + 0x0080 /**< DRP read/write command + (Read=0, Write=1). */ +#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK \ + 0xFF00 /**< DRP write data. */ +#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT \ + 16 /**< Shift bits for DRP write + data. */ +/* @} */ + +/******************************************************************************/ + +/******************************************************************************/ +/** + * Address mapping for the DPCD of the downstream device. + * +*******************************************************************************/ +/** @name DPCD: Receiver capability field. + * + */ +#define XDPTX_DPCD_REV 0x00000 +#define XDPTX_DPCD_MAX_LINK_RATE 0x00001 +#define XDPTX_DPCD_MAX_LANE_COUNT 0x00002 +#define XDPTX_DPCD_MAX_DOWNSPREAD 0x00003 +#define XDPTX_DPCD_NORP_PWR_V_CAP 0x00004 +#define XDPTX_DPCD_DOWNSP_PRESENT 0x00005 +#define XDPTX_DPCD_ML_CH_CODING_CAP 0x00006 +#define XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI 0x00007 +#define XDPTX_DPCD_RX_PORT0_CAP_0 0x00008 +#define XDPTX_DPCD_RX_PORT0_CAP_1 0x00009 +#define XDPTX_DPCD_RX_PORT1_CAP_0 0x0000A +#define XDPTX_DPCD_RX_PORT1_CAP_1 0x0000B +#define XDPTX_DPCD_I2C_SPEED_CTL_CAP 0x0000C +#define XDPTX_DPCD_EDP_CFG_CAP 0x0000D +#define XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E +#define XDPTX_DPCD_ADAPTER_CAP 0x0000F +#define XDPTX_DPCD_FAUX_CAP 0x00020 +#define XDPTX_DPCD_MSTM_CAP 0x00021 +#define XDPTX_DPCD_NUM_AUDIO_EPS 0x00022 +#define XDPTX_DPCD_AV_GRANULARITY 0x00023 +#define XDPTX_DPCD_AUD_DEC_LAT_7_0 0x00024 +#define XDPTX_DPCD_AUD_DEC_LAT_15_8 0x00025 +#define XDPTX_DPCD_AUD_PP_LAT_7_0 0x00026 +#define XDPTX_DPCD_AUD_PP_LAT_15_8 0x00027 +#define XDPTX_DPCD_VID_INTER_LAT 0x00028 +#define XDPTX_DPCD_VID_PROG_LAT 0x00029 +#define XDPTX_DPCD_REP_LAT 0x0002A +#define XDPTX_DPCD_AUD_DEL_INS_7_0 0x0002B +#define XDPTX_DPCD_AUD_DEL_INS_15_8 0x0002C +#define XDPTX_DPCD_AUD_DEL_INS_23_16 0x0002D +#define XDPTX_DPCD_GUID 0x00030 +#define XDPTX_DPCD_RX_GTC_VALUE_7_0 0x00054 +#define XDPTX_DPCD_RX_GTC_VALUE_15_8 0x00055 +#define XDPTX_DPCD_RX_GTC_VALUE_23_16 0x00056 +#define XDPTX_DPCD_RX_GTC_VALUE_31_24 0x00057 +#define XDPTX_DPCD_RX_GTC_MSTR_REQ 0x00058 +#define XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059 +#define XDPTX_DPCD_DOWNSP_0_CAP 0x00080 +#define XDPTX_DPCD_DOWNSP_1_CAP 0x00081 +#define XDPTX_DPCD_DOWNSP_2_CAP 0x00082 +#define XDPTX_DPCD_DOWNSP_3_CAP 0x00083 +#define XDPTX_DPCD_DOWNSP_0_DET_CAP 0x00080 +#define XDPTX_DPCD_DOWNSP_1_DET_CAP 0x00084 +#define XDPTX_DPCD_DOWNSP_2_DET_CAP 0x00088 +#define XDPTX_DPCD_DOWNSP_3_DET_CAP 0x0008C +/* @} */ + +/** @name DPCD: Link configuration field. + * + */ +#define XDPTX_DPCD_LINK_BW_SET 0x00100 +#define XDPTX_DPCD_LANE_COUNT_SET 0x00101 +#define XDPTX_DPCD_TP_SET 0x00102 +#define XDPTX_DPCD_TRAINING_LANE0_SET 0x00103 +#define XDPTX_DPCD_TRAINING_LANE1_SET 0x00104 +#define XDPTX_DPCD_TRAINING_LANE2_SET 0x00105 +#define XDPTX_DPCD_TRAINING_LANE3_SET 0x00106 +#define XDPTX_DPCD_DOWNSPREAD_CTRL 0x00107 +#define XDPTX_DPCD_ML_CH_CODING_SET 0x00108 +#define XDPTX_DPCD_I2C_SPEED_CTL_SET 0x00109 +#define XDPTX_DPCD_EDP_CFG_SET 0x0010A +#define XDPTX_DPCD_LINK_QUAL_LANE0_SET 0x0010B +#define XDPTX_DPCD_LINK_QUAL_LANE1_SET 0x0010C +#define XDPTX_DPCD_LINK_QUAL_LANE2_SET 0x0010D +#define XDPTX_DPCD_LINK_QUAL_LANE3_SET 0x0010E +#define XDPTX_DPCD_TRAINING_LANE0_1_SET2 0x0010F +#define XDPTX_DPCD_TRAINING_LANE2_3_SET2 0x00110 +#define XDPTX_DPCD_MSTM_CTRL 0x00111 +#define XDPTX_DPCD_AUDIO_DELAY_7_0 0x00112 +#define XDPTX_DPCD_AUDIO_DELAY_15_8 0x00113 +#define XDPTX_DPCD_AUDIO_DELAY_23_6 0x00114 +#define XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118 +#define XDPTX_DPCD_FAUX_MODE_CTRL 0x00120 +#define XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121 +#define XDPTX_DPCD_BACK_CH_STATUS 0x00122 +#define XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123 +#define XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125 +#define XDPTX_DPCD_TX_GTC_VALUE_7_0 0x00154 +#define XDPTX_DPCD_TX_GTC_VALUE_15_8 0x00155 +#define XDPTX_DPCD_TX_GTC_VALUE_23_16 0x00156 +#define XDPTX_DPCD_TX_GTC_VALUE_31_24 0x00157 +#define XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158 +#define XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159 +#define XDPTX_DPCD_ADAPTER_CTRL 0x001A0 +#define XDPTX_DPCD_BRANCH_DEVICE_CTRL 0x001A1 +#define XDPTX_DPCD_PAYLOAD_ALLOCATE_SET 0x001C0 +#define XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1 +#define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2 +/* @} */ + +/** @name DPCD: Link/sink status field. + * + */ +#define XDPTX_DPCD_SINK_COUNT 0x00200 +#define XDPTX_DPCD_DEVICE_SERVICE_IRQ 0x00201 +#define XDPTX_DPCD_STATUS_LANE_0_1 0x00202 +#define XDPTX_DPCD_STATUS_LANE_2_3 0x00203 +#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204 +#define XDPTX_DPCD_SINK_STATUS 0x00205 +#define XDPTX_DPCD_ADJ_REQ_LANE_0_1 0x00206 +#define XDPTX_DPCD_ADJ_REQ_LANE_2_3 0x00207 +#define XDPTX_DPCD_TRAINING_SCORE_LANE_0 0x00208 +#define XDPTX_DPCD_TRAINING_SCORE_LANE_1 0x00209 +#define XDPTX_DPCD_TRAINING_SCORE_LANE_2 0x0020A +#define XDPTX_DPCD_TRAINING_SCORE_LANE_3 0x0020B +#define XDPTX_DPCD_ADJ_REQ_PC2 0x0020C +#define XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D +#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210 +#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212 +#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214 +#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216 +/* @} */ + +/** @name DPCD: Automated testing sub-field. + * @{ + */ +#define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS 0x00280 +#define XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281 +#define XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282 +#define XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0 +#define XDPTX_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum) \ + (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum) +/* @} */ + +/** @name DPCD: Sink control field. + * @{ + */ +#define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 +/* @} */ + +/** @name DPCD: Sideband MSG buffers. + * @{ + */ +#define XDPTX_DPCD_DOWN_REQ 0x01000 +#define XDPTX_DPCD_UP_REP 0x01200 +#define XDPTX_DPCD_DOWN_REP 0x01400 +#define XDPTX_DPCD_UP_REQ 0x01600 +/* @} */ + +/** @name DPCD: Event status indicator field. + * @{ + */ +#define XDPTX_DPCD_SINK_COUNT_ESI 0x02002 +#define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003 +#define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004 +#define XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005 +#define XDPTX_DPCD_SINK_LANE0_1_STATUS 0x0200C +#define XDPTX_DPCD_SINK_LANE2_3_STATUS 0x0200D +#define XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E +#define XDPTX_DPCD_SINK_STATUS_ESI 0x0200F +/* @} */ + +/** @name DPCD: Field addresses and sizes. + * @{ + */ +#define XDPTX_DPCD_RECEIVER_CAP_FIELD_START XDPTX_DPCD_REV +#define XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE 0xFF +#define XDPTX_DPCD_LINK_CFG_FIELD_START XDPTX_DPCD_LINK_BW_SET +#define XDPTX_DPCD_LINK_CFG_FIELD_SIZE 0xFF +#define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START XDPTX_DPCD_SINK_COUNT +#define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17 +/* @} */ + +/******************************************************************************/ + +/** @name DPCD: Receiver capability field masks, shifts, and register values. + * + */ +/* 0x00000: DPCD_REV */ +#define XDPTX_DPCD_REV_MNR_MASK 0x0F +#define XDPTX_DPCD_REV_MJR_MASK 0xF0 +#define XDPTX_DPCD_REV_MJR_SHIFT 4 +/* 0x00001: MAX_LINK_RATE */ +#define XDPTX_DPCD_MAX_LINK_RATE_162GBPS 0x06 +#define XDPTX_DPCD_MAX_LINK_RATE_270GBPS 0x0A +#define XDPTX_DPCD_MAX_LINK_RATE_540GBPS 0x14 +/* 0x00002: MAX_LANE_COUNT */ +#define XDPTX_DPCD_MAX_LANE_COUNT_MASK 0x1F +#define XDPTX_DPCD_TPS3_SUPPORT_MASK 0x40 +#define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 +/* 0x00003: MAX_DOWNSPREAD */ +#define XDPTX_DPCD_MAX_DOWNSPREAD_MASK 0x01 +#define XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40 +/* 0x00005: DOWNSP_PRESENT */ +#define XDPTX_DPCD_DOWNSP_PRESENT_MASK 0x01 +#define XDPTX_DPCD_DOWNSP_TYPE_MASK 0x06 +#define XDPTX_DPCD_DOWNSP_TYPE_SHIFT 1 +#define XDPTX_DPCD_DOWNSP_TYPE_DP 0x0 +#define XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1 +#define XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2 +#define XDPTX_DPCD_DOWNSP_TYPE_OTHERS 0x3 +#define XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK 0x08 +#define XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10 +/* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */ +#define XDPTX_DPCD_ML_CH_CODING_MASK 0x01 +/* 0x00007: DOWNSP_COUNT_MSA_OUI */ +#define XDPTX_DPCD_DOWNSP_COUNT_MASK 0x0F +#define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40 +#define XDPTX_DPCD_OUI_SUPPORT_MASK 0x80 +/* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */ +#define XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02 +#define XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04 +/* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */ +#define XDPTX_DPCD_I2C_SPEED_CTL_NONE 0x00 +#define XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS 0x01 +#define XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS 0x02 +#define XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS 0x04 +#define XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS 0x08 +#define XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS 0x10 +#define XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS 0x20 +/* 0x0000E: TRAIN_AUX_RD_INTERVAL */ +#define XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US 0x00 +#define XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS 0x01 +#define XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS 0x02 +#define XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS 0x03 +#define XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS 0x04 +/* 0x00020: DPCD_FAUX_CAP */ +#define XDPTX_DPCD_FAUX_CAP_MASK 0x01 +/* 0x00021: MSTM_CAP */ +#define XDPTX_DPCD_MST_CAP_MASK 0x01 +/* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */ +#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07 +#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP 0x0 +#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1 +#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2 +#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3 +#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4 +#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5 +#define XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK 0x80 +#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0 +#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4 +#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1 +#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2 +#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3 +#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4 +#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5 +#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7 +/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ +#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03 +#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0 +#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1 +#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2 +#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3 +/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ +#define XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01 +#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02 +#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04 +/* @} */ + +/** @name DPCD: Link configuration field masks, shifts, and register values. + * + */ +/* 0x00100: XDPTX_DPCD_LINK_BW_SET */ +#define XDPTX_DPCD_LINK_BW_SET_162GBPS 0x06 +#define XDPTX_DPCD_LINK_BW_SET_270GBPS 0x0A +#define XDPTX_DPCD_LINK_BW_SET_540GBPS 0x14 +/* 0x00101: LANE_COUNT_SET */ +#define XDPTX_DPCD_LANE_COUNT_SET_MASK 0x1F +#define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK 0x80 +/* 0x00102: TP_SET */ +#define XDPTX_DPCD_TP_SEL_MASK 0x03 +#define XDPTX_DPCD_TP_SEL_OFF 0x0 +#define XDPTX_DPCD_TP_SEL_TP1 0x1 +#define XDPTX_DPCD_TP_SEL_TP2 0x2 +#define XDPTX_DPCD_TP_SEL_TP3 0x3 +#define XDPTX_DPCD_TP_SET_LQP_MASK 0x06 +#define XDPTX_DPCD_TP_SET_LQP_SHIFT 2 +#define XDPTX_DPCD_TP_SET_LQP_OFF 0x0 +#define XDPTX_DPCD_TP_SET_LQP_D102_TEST 0x1 +#define XDPTX_DPCD_TP_SET_LQP_SER_MES 0x2 +#define XDPTX_DPCD_TP_SET_LQP_PRBS7 0x3 +#define XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10 +#define XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 +#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0 +#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6 +#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0 +#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE 0x1 +#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2 +/* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */ +#define XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK 0x03 +#define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 +#define XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK 0x18 +#define XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 +#define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 +/* 0x00107: DOWNSPREAD_CTRL */ +#define XDPTX_DPCD_SPREAD_AMP_MASK 0x10 +#define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80 +/* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */ +/* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */ +/* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */ +#define XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03 +#define XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04 +#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30 +#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4 +#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40 +/* 0x00111: MSTM_CTRL */ +#define XDPTX_DPCD_MST_EN_MASK 0x01 +#define XDPTX_DPCD_UP_REQ_EN_MASK 0x02 +#define XDPTX_DPCD_UP_IS_SRC_MASK 0x03 +/* @} */ + +/** @name DPCD: Link/sink status field masks, shifts, and register values. + * + */ +/* 0x00202: STATUS_LANE_0_1 */ +#define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 +#define XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 +#define XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 +#define XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 +#define XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 +#define XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 +/* 0x00202: STATUS_LANE_2_3 */ +#define XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01 +#define XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02 +#define XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04 +#define XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10 +#define XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20 +#define XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40 +/* 0x00204: LANE_ALIGN_STATUS_UPDATED */ +#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \ + 0x01 +#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \ + 0x40 +#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \ + 0x80 +/* 0x00205: SINK_STATUS */ +#define XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01 +#define XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02 + +/* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */ +#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 +#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C +#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 +#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 +#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 +#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 +#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 +/* 0x0020C: ADJ_REQ_PC2 */ +#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03 +#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C +#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2 +#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30 +#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4 +#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0 +#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6 +/* @} */ + +/******************************************************************************/ + +/******************************************************************************/ +/** + * Address mapping for the EDID of the downstream device. + * +*******************************************************************************/ +/** @name EDID: Field addresses and sizes. + * @{ + */ +#define XDPTX_EDID_ADDR 0x50 +#define XDPTX_EDID_SIZE 128 +#define XDPTX_EDID_DTD_DD(Num) (0x36 + (18 * Num)) +#define XDPTX_EDID_PTM XDPTX_EDID_DTD_DD(0) +/* @} */ + +/** @name EDID: Register offsets for the DTD (detailed timing descriptor). + * @{ + */ +#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB 0x00 +#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB 0x01 +#define XDPTX_EDID_DTD_HRES_LSB 0x02 +#define XDPTX_EDID_DTD_HBLANK_LSB 0x03 +#define XDPTX_EDID_DTD_HRES_HBLANK_U4 0x04 +#define XDPTX_EDID_DTD_VRES_LSB 0x05 +#define XDPTX_EDID_DTD_VBLANK_LSB 0x06 +#define XDPTX_EDID_DTD_VRES_VBLANK_U4 0x07 +#define XDPTX_EDID_DTD_HFPORCH_LSB 0x08 +#define XDPTX_EDID_DTD_HSPW_LSB 0x09 +#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4 0x0A +#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2 0x0B +#define XDPTX_EDID_DTD_HIMGSIZE_MM_LSB 0x0C +#define XDPTX_EDID_DTD_VIMGSIZE_MM_LSB 0x0D +#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4 0x0E +#define XDPTX_EDID_DTD_HBORDER 0x0F +#define XDPTX_EDID_DTD_VBORDER 0x10 +#define XDPTX_EDID_DTD_SIGNAL 0x11 + +/** @name EDID: Masks, shifts, and register values. + * @{ + */ +#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK 0x0F +#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK 0xF0 +#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT 4 +#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK 0x0F +#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0 +#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4 +#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0 +#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK 0x30 +#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C +#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK 0x03 +#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6 +#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT 4 +#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2 +#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F +#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0 +#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4 +#define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK 0x02 +#define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK 0x04 +#define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT 1 +#define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT 2 +/* @} */ + +/******************* Macros (Inline Functions) Definitions ********************/ + +/** @name Register access macro definitions. + * @{ + */ +#define XDptx_In32 Xil_In32 +#define XDptx_Out32 Xil_Out32 +/* @} */ + +/******************************************************************************/ +/** + * This is a low-level function that reads from the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to be read from. + * + * @return The 32-bit value of the specified register. + * + * @note C-style signature: + * u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset) + * +*******************************************************************************/ +#define XDptx_ReadReg(BaseAddress, RegOffset) \ + XDptx_In32((BaseAddress) + (RegOffset)) + +/******************************************************************************/ +/** + * This is a low-level function that writes to the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to write to. + * @param Data is the 32-bit data to write to the specified register. + * + * @note C-style signature: + * void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) + * +*******************************************************************************/ +#define XDptx_WriteReg(BaseAddress, RegOffset, Data) \ + XDptx_Out32((BaseAddress) + (RegOffset), (Data)) + +#endif /* XDPTX_HW_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c new file mode 100644 index 00000000..431ea0f4 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c @@ -0,0 +1,146 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_intr.c + * + * This file contains functions related to XDptx interrupt handling. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  05/17/14 Initial release.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * This function installs a callback function for when a hot-plug-detect event + * interrupt occurs. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param CallbackFunc is the address to the callback function. + * @param CallbackRef is the user data item that will be passed to the + * callback function when it is invoked. + * +*******************************************************************************/ +void XDptx_SetHpdEventHandler(XDptx *InstancePtr, + XDptx_HpdEventHandler CallbackFunc, void *CallbackRef) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallbackFunc != NULL); + Xil_AssertVoid(CallbackRef != NULL); + + InstancePtr->HpdEventHandler = CallbackFunc; + InstancePtr->HpdEventCallbackRef = CallbackRef; +} + +/******************************************************************************/ +/** + * This function installs a callback function for when a hot-plug-detect pulse + * interrupt occurs. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param CallbackFunc is the address to the callback function. + * @param CallbackRef is the user data item that will be passed to the + * callback function when it is invoked. + * +*******************************************************************************/ +void XDptx_SetHpdPulseHandler(XDptx *InstancePtr, + XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallbackFunc != NULL); + Xil_AssertVoid(CallbackRef != NULL); + + InstancePtr->HpdPulseHandler = CallbackFunc; + InstancePtr->HpdPulseCallbackRef = CallbackRef; +} + +/******************************************************************************/ +/** + * This function is the interrupt handler for the XDptx driver. + * + * When an interrupt happens, it first detects what kind of interrupt happened, + * then decides which callback function to invoke. + * + * @param InstancePtr is a pointer to the XDptx instance. + * +*******************************************************************************/ +void XDptx_HpdInterruptHandler(XDptx *InstancePtr) +{ + u32 IntrStatus; + u8 HpdEventDetected; + u8 HpdPulseDetected; + u32 HpdDuration; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + /* Determine what kind of interrupt occurred. + * Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */ + IntrStatus = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_INTERRUPT_STATUS); + IntrStatus &= ~XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_INTERRUPT_MASK); + + HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK; + HpdPulseDetected = IntrStatus & + XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK; + + if (HpdEventDetected) { + InstancePtr->HpdEventHandler(InstancePtr->HpdEventCallbackRef); + } + + if (HpdPulseDetected) { + /* The source device must debounce the incoming HPD signal by + * sampling the value at an interval greater than 250 ms. */ + HpdDuration = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + XDPTX_HPD_DURATION); + if (HpdDuration >= 250) { + InstancePtr->HpdPulseHandler( + InstancePtr->HpdPulseCallbackRef); + } + } +} diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c new file mode 100644 index 00000000..78151b3f --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c @@ -0,0 +1,103 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_selftest.c + * + * This file contains a diagnostic self-test function for the XDptx driver. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  05/17/14 Initial release.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xstatus.h" + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * This function runs a self-test on the XDptx driver/device. The test attempts + * to intialize the DisplayPort TX core, train the main link at the highest + * common capabilities between the core and the sink, and checks the status + * of the link after training. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return + * - XST_SUCCESS if the self-test passed. The main link has been + * trained and established successfully. + * - XST_FAILURE otherwise. + * +*******************************************************************************/ +u32 XDptx_SelfTest(XDptx *InstancePtr) +{ + XDptx_Config *ConfigPtr; + u32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Obtain the capabilities of the sink by reading the DPCD. */ + Status = XDptx_GetSinkCapabilities(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Configure the main link attributes. */ + Status = XDptx_CfgMainLinkMax(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Attempt to establish a link at the maximum common capabilities + * between the DisplayPort TX core and the sink. */ + XDptx_EstablishLink(InstancePtr); + + /* Return whether or not the link has been successfully trained. */ + Status = XDptx_CheckLinkStatus(InstancePtr, + InstancePtr->LinkConfig.LaneCount); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c new file mode 100644 index 00000000..90e690b3 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c @@ -0,0 +1,89 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_sinit.c + * + * This file contains static initialization methods for the XDptx driver. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  05/17/14 Initial release.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xparameters.h" + +/*************************** Variable Declarations ****************************/ + +/** + * A table of configuration structures containing the configuration information + * for each DisplayPort TX core in the system. + */ +extern XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES]; + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * This function looks for the device configuration based on the unique device + * ID. The table XDptx_ConfigTable[] contains the configuration information for + * each device in the system. + * + * @param DeviceId is the unique device ID of the device being looked up. + * + * @return A pointer to the configuration table entry corresponding to the + * given device ID, or NULL if no match is found. + * +*******************************************************************************/ +XDptx_Config *XDptx_LookupConfig(u16 DeviceId) +{ + XDptx_Config *CfgPtr; + u32 Index; + + for (Index = 0; Index < XPAR_XDPTX_NUM_INSTANCES; Index++) { + if (XDptx_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XDptx_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +} diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c new file mode 100644 index 00000000..f47c3731 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c @@ -0,0 +1,561 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_spm.c + * + * This file contains the stream policy maker functions for the XDptx driver. + * These functions set up the DisplayPort TX core's main stream attributes that + * determine how a video stream will be displayed. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  05/17/14 Initial release.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx.h" +#include "xdptx_hw.h" +#include "xstatus.h" + +/**************************** Function Prototypes *****************************/ + +static void XDptx_ClearMsaValues(XDptx *InstancePtr); +static void XDptx_SetMsaValues(XDptx *InstancePtr, + XDptx_MainStreamAttributes *MsaConfig); + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * This function calculates the following main stream attributes: + * - Transfer unit size + * - User pixel width + * - NVid + * - Horizontal start + * - Vertical start + * - Horizontal total clock + * - Vertical total clock + * - Misc0 + * - Misc1 + * - Data per lane + * - Average number of bytes per transfer unit + * - Number of initial wait cycles + * These values are derived from: + * - Bits per color + * - MVid + * - Horizontal sync polarity + * - Vertical sync polarity + * - Horizontal sync pulse width + * - Vertical sync pulse width + * - Horizontal resolution + * - Vertical resolution + * - Vertical back porch + * - Vertical front porch + * - Horizontal back porch + * - Horizontal front porch + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @note The MsaConfig structure is modified with the new, calculated + * values. The main stream attributes that were used to derive the + * calculated values are untouched in the MsaConfig structure. + * +*******************************************************************************/ +void XDptx_CfgMsaRecalculate(XDptx *InstancePtr) +{ + u32 VideoBw; + u32 BitsPerPixel; + XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig; + XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + /* For SST. */ + MsaConfig->TransferUnitSize = 64; + + /* Set the user pixel width to handle clocks that exceed the + * capabilities of the DisplayPort TX core. */ + if ((MsaConfig->MVid > 150000) && (LinkConfig->LaneCount == 4)) { + MsaConfig->UserPixelWidth = 4; + } + else if ((MsaConfig->MVid > 80000) && (LinkConfig->LaneCount == 2)) { + MsaConfig->UserPixelWidth = 2; + } + else { + MsaConfig->UserPixelWidth = 1; + } + + /* Compute the rest of the MSA values. */ + MsaConfig->NVid = (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS) ? + 540000 : + (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ? + 270000 : + 162000; + MsaConfig->HStart = MsaConfig->HSyncPulseWidth + MsaConfig->HBackPorch; + MsaConfig->VStart = MsaConfig->VSyncPulseWidth + MsaConfig->VBackPorch; + MsaConfig->HClkTotal = (MsaConfig->HSyncPulseWidth + + MsaConfig->HBackPorch + MsaConfig->HFrontPorch + + MsaConfig->HResolution); + MsaConfig->VClkTotal = (MsaConfig->VSyncPulseWidth + + MsaConfig->VBackPorch + MsaConfig->VFrontPorch + + MsaConfig->VResolution); + MsaConfig->Misc0 = (MsaConfig->BitsPerColor == 6) ? 0x00 : + (MsaConfig->BitsPerColor == 8) ? 0x01 : + (MsaConfig->BitsPerColor == 10) ? 0x02 : + (MsaConfig->BitsPerColor == 12) ? 0x03 : + (MsaConfig->BitsPerColor == 16) ? 0x04 : + 0x00; + MsaConfig->Misc0 = MsaConfig->Misc0 << + XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT; + MsaConfig->Misc0 = MsaConfig->Misc0 | (LinkConfig->ComponentFormat << + XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) | + (LinkConfig->DynamicRange << + XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) | + (LinkConfig->YCbCrColorimetry << + XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) | + (LinkConfig->SynchronousClockMode & + XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK); + MsaConfig->Misc1 = 0; + MsaConfig->DataPerLane = (MsaConfig->HResolution * + MsaConfig->BitsPerColor * 3 / 16) - LinkConfig->LaneCount; + + /* If RGB | YCbCr444, * 3 ; If YCbCr422, * 2 ; If YOnly, * 1. */ + BitsPerPixel = (LinkConfig->ComponentFormat == 1) ? + MsaConfig->BitsPerColor * 2 : + MsaConfig->BitsPerColor * 3; + VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8; + + MsaConfig->AvgBytesPerTU = (VideoBw * MsaConfig->TransferUnitSize) / + (LinkConfig->LaneCount * (MsaConfig->NVid / 1000)); + + /* The number of initial wait cycles at the start of a new line by the + * framing logic. This allows enough data to be buffered in the input + * FIFO before video is sent. */ + MsaConfig->InitWait = (MsaConfig->TransferUnitSize - + (MsaConfig->AvgBytesPerTU / 1000)); + if ((MsaConfig->AvgBytesPerTU / 1000) > MsaConfig->TransferUnitSize) { + MsaConfig->InitWait = 0; + } + else if (MsaConfig->InitWait > 10) { + MsaConfig->InitWait -= 10; + } + else { + MsaConfig->InitWait = 0; + } +} + +/******************************************************************************/ +/** + * This function sets the main stream attribute values in the configuration + * structure to match one of the standard display mode timings from the + * XDptx_DmtModes[] table. THe XDptx_VideoMode enumeration in xdptx.h lists + * the available video modes. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param VideoMode is one of the enumerated standard video modes that is + * used to determine the main stream attributes to be used. + * + * @return + * - XST_INVALID_PARAM if the supplied video mode isn't in the DMT + * table. + * - XST_SUCCESS otherwise. + * + * @note The InstancePtr->MsaConfig structure is modified to reflect the + * main stream attribute values associated to the specified video + * mode. + * +*******************************************************************************/ +u32 XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, + XDptx_VideoMode VideoMode) +{ + XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + if (VideoMode > XDPTX_VM_LAST) { + return XST_INVALID_PARAM; + } + + /* Configure the main stream attribute values from the display monitor + * timing (DMT) table. */ + MsaConfig->MVid = XDptx_DmtModes[VideoMode].PixelClkKhz; + MsaConfig->HSyncPolarity = XDptx_DmtModes[VideoMode].HSyncPolarity; + MsaConfig->VSyncPolarity = XDptx_DmtModes[VideoMode].VSyncPolarity; + MsaConfig->HSyncPulseWidth = XDptx_DmtModes[VideoMode].HSyncPulseWidth; + MsaConfig->VSyncPulseWidth = XDptx_DmtModes[VideoMode].VSyncPulseWidth; + MsaConfig->HResolution = XDptx_DmtModes[VideoMode].HResolution; + MsaConfig->VResolution = XDptx_DmtModes[VideoMode].VResolution; + MsaConfig->VBackPorch = XDptx_DmtModes[VideoMode].VBackPorch; + MsaConfig->VFrontPorch = XDptx_DmtModes[VideoMode].VFrontPorch; + MsaConfig->HBackPorch = XDptx_DmtModes[VideoMode].HBackPorch; + MsaConfig->HFrontPorch = XDptx_DmtModes[VideoMode].HFrontPorch; + + /* Calculate the rest of the MSA values. */ + XDptx_CfgMsaRecalculate(InstancePtr); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the main stream attribute values in the configuration + * structure to match the preferred timing of the sink monitor. This preferred + * timing information is stored in the sink's extended display identification + * data (EDID). + * + * @param InstancePtr is a pointer to the XDptx instance + * + * @note The InstancePtr->MsaConfig structure is modified to reflect the + * main stream attribute values associated to the preferred timing + * of the sink monitor. + * +*******************************************************************************/ +void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr) +{ + XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig; + u8 *Ptm = &InstancePtr->RxConfig.Edid[XDPTX_EDID_PTM]; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + /* Configure the MSA values with the preferred timing mode (PTM) as + * specified by the preferred detailed timing descriptor of the + * monitor's EDID. + * Note, the PTM is only required for EDID versions 1.3 a newer. Earlier + * versions may not contain this information. */ + u16 HBlank = ((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] & + XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) | + Ptm[XDPTX_EDID_DTD_HBLANK_LSB]; + + u16 VBlank = ((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] & + XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) | + Ptm[XDPTX_EDID_DTD_VBLANK_LSB]; + + MsaConfig->MVid = ((Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB] << 8) | + Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10; + + MsaConfig->HSyncPulseWidth = + (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] & + XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >> + XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) | + Ptm[XDPTX_EDID_DTD_HSPW_LSB]; + + MsaConfig->VSyncPulseWidth = + ((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] & + XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) | + (Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] & + XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK); + + MsaConfig->HResolution = + (((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] & + XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >> + XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XDPTX_EDID_DTD_HRES_LSB]; + + MsaConfig->VResolution = (((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] & + XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >> + XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XDPTX_EDID_DTD_VRES_LSB]; + + MsaConfig->VFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] & + XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >> + XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) | + ((Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] & + XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >> + XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT); + + MsaConfig->HFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] & + XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >> + XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) | + Ptm[XDPTX_EDID_DTD_HFPORCH_LSB]; + + MsaConfig->HSyncPolarity = (Ptm[XDPTX_EDID_DTD_SIGNAL] & + XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK) >> + XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT; + + MsaConfig->VSyncPolarity = Ptm[XDPTX_EDID_DTD_SIGNAL] & + XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK >> + XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT; + + MsaConfig->VBackPorch = VBlank - + (MsaConfig->VFrontPorch + MsaConfig->VSyncPulseWidth); + + MsaConfig->HBackPorch = HBlank - + (MsaConfig->HFrontPorch + MsaConfig->HSyncPulseWidth); + + /* Calculate the rest of the MSA values. */ + XDptx_CfgMsaRecalculate(InstancePtr); +} + +/******************************************************************************/ +/** + * This function takes a the main stream attributes from MsaConfigCustom and + * copies them into InstancePtr->MsaConfig. If desired, given a base set of + * attributes, the rest of the attributes may be derived. The minimal required + * main stream attributes that must be contained in the MsaConfigCustom + * structure are: + * - MVid + * - Horizontal sync polarity + * - Vertical sync polarity + * - Horizontal sync pulse width + * - Vertical sync pulse width + * - Horizontal resolution + * - Vertical resolution + * - Vertical back porch + * - Vertical front porch + * - Horizontal back porch + * - Horizontal front porch + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param MsaConfigCustom is the structure that will be used to copy the + * main stream attributes from (into InstancePtr->MsaConfig). + * @param Recalculate is a boolean enable that determines whether or not + * the main stream attributes should be recalculated. + * + * @note The InstancePtr-> MsaConfig structure is modified with the new + * values. + * +*******************************************************************************/ +void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, + XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate) +{ + XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(MsaConfigCustom != NULL); + + /* Copy the MSA values from the user configuration structure. */ + MsaConfig->MVid = MsaConfigCustom->MVid; + MsaConfig->HSyncPolarity = MsaConfigCustom->HSyncPolarity; + MsaConfig->VSyncPolarity = MsaConfigCustom->VSyncPolarity; + MsaConfig->HSyncPulseWidth = MsaConfigCustom->HSyncPulseWidth; + MsaConfig->VSyncPulseWidth = MsaConfigCustom->VSyncPulseWidth; + MsaConfig->HResolution = MsaConfigCustom->HResolution; + MsaConfig->VResolution = MsaConfigCustom->VResolution; + + MsaConfig->VBackPorch = MsaConfigCustom->VBackPorch; + MsaConfig->VFrontPorch = MsaConfigCustom->VFrontPorch; + MsaConfig->HBackPorch = MsaConfigCustom->HBackPorch; + MsaConfig->HFrontPorch = MsaConfigCustom->HFrontPorch; + + if (Recalculate) { + /* Calculate the rest of the MSA values. */ + XDptx_CfgMsaRecalculate(InstancePtr); + } + else { + /* Use the custom values for the rest. */ + MsaConfig->TransferUnitSize = MsaConfigCustom->TransferUnitSize; + MsaConfig->UserPixelWidth = MsaConfigCustom->UserPixelWidth; + MsaConfig->NVid = MsaConfigCustom->NVid; + MsaConfig->HStart = MsaConfigCustom->HStart; + MsaConfig->VStart = MsaConfigCustom->VStart; + MsaConfig->HClkTotal = MsaConfigCustom->HClkTotal; + MsaConfig->VClkTotal = MsaConfigCustom->VClkTotal; + MsaConfig->Misc0 = MsaConfigCustom->Misc0; + MsaConfig->Misc1 = MsaConfigCustom->Misc1; + MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane; + MsaConfig->AvgBytesPerTU = MsaConfigCustom->AvgBytesPerTU; + MsaConfig->InitWait = MsaConfigCustom->InitWait; + } +} + +/******************************************************************************/ +/** + * This function sets the bits per color value of the video stream. + * + * @param InstancePtr is a pointer to the XDptx instance + * @param BitsPerColor is the new number of bits per color to use. + * + * @note The InstancePtr->MsaConfig structure is modified to reflect the + * new main stream attributes associated with a new bits per color + * value. + * + * @return + * - XST_INVALID_PARAM if the supplied bits per color value is not + * either 6, 8, 10, 12, or 16. + * - XST_SUCCESS otherwise. + * +*******************************************************************************/ +u32 XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + switch (BitsPerColor) { + case 6: + case 8: + case 10: + case 12: + case 16: + break; + default: + return XST_INVALID_PARAM; + } + + InstancePtr->MsaConfig.BitsPerColor = BitsPerColor; + + /* Calculate the rest of the MSA values. */ + XDptx_CfgMsaRecalculate(InstancePtr); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function clears the main stream attributes registers of the DisplayPort + * TX core and sets them to the values specified in the main stream attributes + * configuration structure. + * + * @param InstancePtr is a pointer to the XDptx instance + * +*******************************************************************************/ +void XDptx_SetVideoMode(XDptx *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + XDptx_ClearMsaValues(InstancePtr); + XDptx_SetMsaValues(InstancePtr, &InstancePtr->MsaConfig); +} + +/******************************************************************************/ +/** + * This function clears the main stream attributes registers of the DisplayPort + * TX core. + * + * @param InstancePtr is a pointer to the XDptx instance. + * +*******************************************************************************/ +static void XDptx_ClearMsaValues(XDptx *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + XDptx_Config *TxConfig = &InstancePtr->TxConfig; + + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_POLARITY, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HRES, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VRES, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSTART, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSTART, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC0, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC1, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_TU_SIZE, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_PIXEL_WIDTH, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_M_VID, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_N_VID, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MIN_BYTES_PER_TU, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_FRAC_BYTES_PER_TU, 0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_INIT_WAIT, 0); +} + +/******************************************************************************/ +/** + * This function sets the main stream attributes registers of the DisplayPort TX + * core with the values specified in the main stream attributes configuration + * structure. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param MsaConfig is a pointer to the main stream attributes + * configuration structure. + * +*******************************************************************************/ +static void XDptx_SetMsaValues(XDptx *InstancePtr, + XDptx_MainStreamAttributes *MsaConfig) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(MsaConfig != NULL); + + XDptx_Config *TxConfig = &InstancePtr->TxConfig; + + /* Set the main stream attributes to the associated DisplayPort TX core + * registers. */ + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL, + MsaConfig->HClkTotal); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL, + MsaConfig->VClkTotal); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_POLARITY, + MsaConfig->HSyncPolarity | (MsaConfig->VSyncPolarity << + XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT)); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH, + MsaConfig->HSyncPulseWidth); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH, + MsaConfig->VSyncPulseWidth); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HRES, + MsaConfig->HResolution); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VRES, + MsaConfig->VResolution); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSTART, + MsaConfig->HStart); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSTART, + MsaConfig->VStart); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC0, + MsaConfig->Misc0); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC1, + MsaConfig->Misc1); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_M_VID, + MsaConfig->MVid); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_N_VID, + MsaConfig->NVid); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_PIXEL_WIDTH, + MsaConfig->UserPixelWidth); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE, + MsaConfig->DataPerLane); + + /* Set the transfer unit values to the associated DisplayPort TX core + * registers. */ + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_TU_SIZE, + MsaConfig->TransferUnitSize); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MIN_BYTES_PER_TU, + MsaConfig->AvgBytesPerTU / 1000); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_FRAC_BYTES_PER_TU, + MsaConfig->AvgBytesPerTU % 1000); + XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_INIT_WAIT, + MsaConfig->InitWait); +} diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c new file mode 100644 index 00000000..41af9e19 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c @@ -0,0 +1,234 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_vidmodetable.c + * + * Contains display monitor timing (DMT) modes for various standard resolutions. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a als  05/17/14 Initial release.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xil_types.h" +#include "xdptx.h" + +/**************************** Variable Definitions ****************************/ + +/** + * This table contains the main stream attributes for various standard + * resolutions. + */ +XDptx_DmtMode XDptx_DmtModes[] = +{ + {XDPTX_VM_640x480_60_P, 0x04, 640, 480, 25175, + 0, 1, 1, 8, 96, 40, 2, 2, 25}, + {XDPTX_VM_800x600_60_P, 0x09, 800, 600, 40000, + 0, 0, 0, 40, 128, 88, 1, 4, 23}, + {XDPTX_VM_848x480_60_P, 0x0E, 848, 480, 33750, + 0, 0, 0, 16, 112, 112, 6, 8, 23}, + {XDPTX_VM_1024x768_60_P, 0x10, 1024, 768, 65000, + 0, 1, 1, 24, 136, 160, 3, 6, 29}, + {XDPTX_VM_1280x768_60_P_RB, 0x16, 1280, 768, 68250, + 0, 0, 1, 48, 32, 80, 3, 7, 12}, + {XDPTX_VM_1280x768_60_P, 0x17, 1280, 768, 79500, + 0, 1, 0, 64, 128, 192, 3, 7, 20}, + {XDPTX_VM_1280x800_60_P_RB, 0x1B, 1280, 800, 71000, + 0, 0, 1, 48, 32, 80, 3, 6, 14}, + {XDPTX_VM_1280x800_60_P, 0x1C, 1280, 800, 83500, + 0, 1, 0, 72, 128, 200, 3, 6, 22}, + {XDPTX_VM_1280x960_60_P, 0x20, 1280, 960, 108000, + 0, 0, 0, 96, 112, 312, 1, 3, 36}, + {XDPTX_VM_1280x1024_60_P, 0x23, 1280, 1024, 108000, + 0, 0, 0, 48, 112, 248, 1, 3, 38}, + {XDPTX_VM_1360x768_60_P, 0x27, 1360, 768, 85500, + 0, 0, 0, 64, 112, 256, 3, 6, 18}, + {XDPTX_VM_1400x1050_60_P_RB, 0x29, 1400, 1050, 101000, + 0, 0, 1, 48, 32, 80, 3, 4, 23}, + {XDPTX_VM_1400x1050_60_P, 0x2A, 1400, 1050, 121750, + 0, 1, 0, 88, 144, 232, 3, 4, 32}, + {XDPTX_VM_1440x900_60_P_RB, 0x2E, 1440, 900, 88750, + 0, 0, 1, 48, 32, 80, 3, 6, 17}, + {XDPTX_VM_1440x900_60_P, 0x2F, 1440, 900, 106500, + 0, 1, 0, 80, 152, 232, 3, 6, 25}, + {XDPTX_VM_1600x1200_60_P, 0x33, 1600, 1200, 162000, + 0, 0, 0, 64, 192, 304, 1, 3, 46}, + {XDPTX_VM_1680x1050_60_P_RB, 0x39, 1680, 1050, 119000, + 0, 1, 0, 48, 32, 80, 3, 6, 21}, + {XDPTX_VM_1680x1050_60_P, 0x3A, 1680, 1050, 146250, + 0, 1, 0, 104, 176, 280, 3, 6, 30}, + {XDPTX_VM_1792x1344_60_P, 0x3E, 1792, 1344, 204750, + 0, 1, 0, 128, 200, 328, 1, 3, 46}, + {XDPTX_VM_1856x1392_60_P, 0x41, 1856, 1392, 218250, + 0, 1, 0, 96, 224, 352, 1, 3, 43}, + {XDPTX_VM_1920x1200_60_P_RB, 0x44, 1920, 1200, 154000, + 0, 0, 1, 48, 32, 80, 3, 6, 26}, + {XDPTX_VM_1920x1200_60_P, 0x45, 1920, 1200, 193250, + 0, 1, 0, 136, 200, 336, 3, 6, 36}, + {XDPTX_VM_1920x1440_60_P, 0x49, 1920, 1440, 234000, + 0, 1, 0, 128, 208, 344, 1, 3, 56}, + {XDPTX_VM_2560x1600_60_P_RB, 0x4C, 2560, 1600, 268500, + 0, 0, 1, 48, 32, 80, 3, 6, 37}, + {XDPTX_VM_2560x1600_60_P, 0x4D, 2560, 1600, 348500, + 0, 1, 0, 192, 280, 472, 3, 6, 49}, + {XDPTX_VM_800x600_56_P, 0x08, 800, 600, 36000, + 0, 0, 0, 24, 72, 128, 1, 2, 22}, + {XDPTX_VM_1600x1200_65_P, 0x34, 1600, 1200, 175500, + 0, 0, 0, 64, 192, 304, 1, 3, 46}, + {XDPTX_VM_1600x1200_70_P, 0x35, 1600, 1200, 189000, + 0, 0, 0, 64, 192, 304, 1, 3, 46}, + {XDPTX_VM_1024x768_70_P, 0x11, 1024, 768, 75000, + 0, 1, 1, 24, 136, 144, 3, 6, 29}, + {XDPTX_VM_640x480_72_P, 0x05, 640, 480, 31500, + 0, 1, 1, 16, 40, 120, 1, 3, 20}, + {XDPTX_VM_800x600_72_P, 0x0A, 800, 600, 50000, + 0, 0, 0, 56, 120, 64, 37, 6, 23}, + {XDPTX_VM_640x480_75_P, 0x06, 640, 480, 31500, + 0, 1, 1, 16, 64, 120, 1, 3, 16}, + {XDPTX_VM_800x600_75_P, 0x0B, 800, 600, 49500, + 0, 0, 0, 16, 80, 160, 1, 3, 21}, + {XDPTX_VM_1024x768_75_P, 0x12, 1024, 768, 78750, + 0, 0, 0, 16, 96, 176, 1, 3, 28}, + {XDPTX_VM_1152x864_75_P, 0x15, 1152, 864, 108000, + 0, 0, 0, 64, 128, 256, 1, 3, 32}, + {XDPTX_VM_1280x768_75_P, 0x18, 1280, 768, 102250, + 0, 1, 0, 80, 128, 208, 3, 7, 27}, + {XDPTX_VM_1280x800_75_P, 0x1D, 1280, 800, 106500, + 0, 1, 0, 80, 128, 208, 3, 6, 29}, + {XDPTX_VM_1280x1024_75_P, 0x24, 1280, 1024, 135000, + 0, 0, 0, 16, 144, 248, 1, 3, 38}, + {XDPTX_VM_1400x1050_75_P, 0x2B, 1400, 1050, 156000, + 0, 1, 0, 104, 144, 248, 3, 4, 42}, + {XDPTX_VM_1440x900_75_P, 0x30, 1440, 900, 136750, + 0, 1, 0, 96, 152, 31, 3, 6, 33}, + {XDPTX_VM_1600x1200_75_P, 0x36, 1600, 1200, 202500, + 0, 0, 0, 64, 192, 304, 1, 3, 46}, + {XDPTX_VM_1680x1050_75_P, 0x3B, 1680, 1050, 187000, + 0, 1, 0, 120, 176, 37, 3, 6, 40}, + {XDPTX_VM_1792x1344_75_P, 0x3F, 1792, 1344, 261000, + 0, 1, 0, 96, 216, 352, 1, 3, 69}, + {XDPTX_VM_1856x1392_75_P, 0x42, 1856, 1392, 288000, + 0, 1, 0, 128, 224, 352, 1, 3, 104}, + {XDPTX_VM_1920x1200_75_P, 0x46, 1920, 1200, 245250, + 0, 1, 0, 136, 208, 344, 3, 6, 46}, + {XDPTX_VM_1920x1440_75_P, 0x4A, 1920, 1440, 297000, + 0, 1, 0, 144, 224, 352, 1, 3, 56}, + {XDPTX_VM_2560x1600_75_P, 0x4E, 2560, 1600, 443250, + 0, 1, 0, 208, 280, 488, 3, 6, 63}, + {XDPTX_VM_640x350_85_P, 0x01, 640, 350, 31500, + 0, 0, 1, 32, 64, 96, 32, 3, 60}, + {XDPTX_VM_640x400_85_P, 0x02, 640, 400, 31500, + 0, 1, 0, 32, 64, 96, 1, 3, 41}, + {XDPTX_VM_720x400_85_P, 0x03, 720, 400, 35500, + 0, 1, 0, 36, 72, 108, 1, 3, 42}, + {XDPTX_VM_640x480_85_P, 0x07, 640, 480, 36000, + 0, 1, 1, 56, 56, 80, 1, 3, 25}, + {XDPTX_VM_800x600_85_P, 0x0C, 800, 600, 56250, + 0, 0, 0, 32, 64, 152, 1, 3, 27}, + {XDPTX_VM_1024x768_85_P, 0x13, 1024, 768, 94500, + 0, 0, 0, 48, 96, 208, 1, 3, 36}, + {XDPTX_VM_1280x768_85_P, 0x19, 1280, 768, 117500, + 0, 1, 0, 80, 136, 216, 3, 7, 31}, + {XDPTX_VM_1280x800_85_P, 0x1E, 1280, 800, 122500, + 0, 1, 0, 80, 136, 216, 3, 6, 34}, + {XDPTX_VM_1280x960_85_P, 0x21, 1280, 960, 148500, + 0, 0, 0, 64, 160, 224, 1, 3, 47}, + {XDPTX_VM_1280x1024_85_P, 0x25, 1280, 1024, 157500, + 0, 0, 0, 64, 160, 224, 1, 3, 44}, + {XDPTX_VM_1400x1050_85_P, 0x2C, 1400, 1050, 179500, + 0, 1, 0, 104, 152, 256, 3, 4, 48}, + {XDPTX_VM_1440x900_85_P, 0x31, 1440, 900, 157000, + 0, 1, 0, 104, 152, 32, 3, 6, 39}, + {XDPTX_VM_1600x1200_85_P, 0x37, 1600, 1200, 229500, + 0, 0, 0, 64, 192, 304, 1, 3, 46}, + {XDPTX_VM_1680x1050_85_P, 0x3C, 1680, 1050, 214750, + 0, 1, 0, 128, 176, 304, 3, 6, 46}, + {XDPTX_VM_1920x1200_85_P, 0x47, 1920, 1200, 281250, + 0, 1, 0, 144, 208, 352, 3, 6, 53}, + {XDPTX_VM_2560x1600_85_P, 0x4F, 2560, 1600, 505250, + 0, 1, 0, 208, 280, 488, 3, 6, 73}, + {XDPTX_VM_800x600_120_P_RB, 0x0D, 800, 600, 73250, + 0, 0, 1, 48, 32, 80, 3, 4, 29}, + {XDPTX_VM_1024x768_120_P_RB, 0x14, 1024, 768, 115500, + 0, 0, 1, 48, 32, 80, 3, 4, 38}, + {XDPTX_VM_1280x768_120_P_RB, 0x1A, 1280, 768, 140250, + 0, 0, 1, 48, 32, 80, 3, 7, 35}, + {XDPTX_VM_1280x800_120_P_RB, 0x1F, 1280, 800, 146250, + 0, 0, 1, 48, 32, 80, 3, 6, 38}, + {XDPTX_VM_1280x960_120_P_RB, 0x22, 1280, 960, 175500, + 0, 0, 1, 48, 32, 80, 3, 4, 50}, + {XDPTX_VM_1280x1024_120_P_RB, 0x26, 1280, 1024, 187250, + 0, 0, 1, 48, 32, 80, 3, 7, 50}, + {XDPTX_VM_1360x768_120_P_RB, 0x28, 1360, 768, 148250, + 0, 0, 1, 48, 32, 80, 3, 5, 37}, + {XDPTX_VM_1400x1050_120_P_RB, 0x2D, 1400, 1050, 208000, + 0, 0, 1, 48, 32, 80, 3, 4, 55}, + {XDPTX_VM_1440x900_120_P_RB, 0x32, 1440, 900, 182750, + 0, 0, 1, 48, 32, 80, 3, 6, 44}, + {XDPTX_VM_1600x1200_120_P_RB, 0x38, 1600, 1200, 268250, + 0, 0, 1, 48, 32, 80, 3, 4, 64}, + {XDPTX_VM_1680x1050_120_P_RB, 0x3D, 1680, 1050, 245500, + 0, 0, 1, 48, 32, 80, 3, 6, 53}, + {XDPTX_VM_1792x1344_120_P_RB, 0x40, 1792, 1344, 333250, + 0, 0, 1, 48, 32, 80, 3, 4, 72}, + {XDPTX_VM_1856x1392_120_P_RB, 0x43, 1856, 1392, 356500, + 0, 0, 1, 48, 32, 80, 3, 4, 75}, + {XDPTX_VM_1920x1200_120_P_RB, 0x48, 1920, 1200, 317000, + 0, 0, 1, 48, 32, 80, 3, 6, 62}, + {XDPTX_VM_1920x1440_120_P_RB, 0x4B, 1920, 1440, 380500, + 0, 0, 1, 48, 32, 80, 3, 4, 78}, + {XDPTX_VM_2560x1600_120_P_RB, 0x50, 2560, 1600, 552750, + 0, 0, 1, 48, 32, 80, 3, 6, 85}, + {XDPTX_VM_1366x768_60_P, 0x00, 1366, 768, 72000, + 0, 0, 0, 14, 56, 64, 1, 3, 28}, + {XDPTX_VM_1920x1080_60_P, 0x00, 1920, 1080, 148500, + 0, 1, 1, 88, 44, 148, 4, 5, 36}, + {XDPTX_VM_UHD_30_P, 0x00, 3840, 2160, 297000, 0, 0, 1, 176, + 88, 296, 20, 10, 60}, + {XDPTX_VM_720_60_P, 0x00, 1280, 720, 74250, 0, 1, 1, 110, + 40, 220, 5, 5, 20}, + {XDPTX_VM_480_60_P, 0x00, 720, 480, 27027, 0, 1, 1, 16, 62, + 60, 9, 6, 30}, + {XDPTX_VM_UHD2_60_P, 0x00, 1920, 2160, 297000, 0, 0, 1, 88, + 44, 148, 20, 10, 60}, + {XDPTX_VM_UHD_60, 0x00, 3840, 2160, 594000, 0, 0, 1, 176, + 88, 296, 20, 10, 60} +};