Copyright � 2010-14 Xilinx, Inc. All rights reserved.
+ + diff --git a/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_interrupt_example.c b/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_interrupt_example.c new file mode 100644 index 00000000..27a77729 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_interrupt_example.c @@ -0,0 +1,435 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xdcfg_interrupt_example.c +* +* This file contains a interrupt mode design example for the Device +* Configuration Interface. This example downloads a given bitstream to the FPGA +* fabric. +* +* BIT_STREAM_LOCATION specifies the memory location of the bitstream. +* BIT_STREAM_SIZE_WORDS specifies the size of the bitstream in words. +* User has to define these correctly for this example to work. +* +* @note None +* +* +* MODIFICATION HISTORY: +* +*+* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +* 1.00a nm 11/26/11 Holding FPGA in reset before download and +* releasing it after bitstream download. This code +* is not checking bitstream download errors. +* If the bitstream download fails, this test hangs. +* 2.00a nm 05/31/12 Updated the notes in the example for CR 660139 to add +* information that the 2 LSBs of the Source/Destination +* address when equal to 2�b01 indicate the last DMA command +* of an overall transfer. +* Updated the example for CR 660835 so that input length for +* source/destination to the XDcfg_Transfer APIs is words +* (32 bit) and not bytes. +* 2.01a nm 11/21/12 Fixed CR# 688146. Modified the bitstream address. +* 2.02a nm 01/31/13 Fixed CR# 679335. +* Removed disabling and enabling AXI interface. +* Clearing the interrupts before the transfer. +* Added support for partial reconfiguration. +* 3.00a kpc 02/10/14 Fixed the compilation error +* 3.1 kpc 04/22/14 Fixed CR#780203. Enable the pcap clock if it is not set. +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xil_exception.h" +#include "xscugic.h" +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are only defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID +#define DCFG_INTR_ID XPAR_XDCFG_0_INTR + +/* + * The BIT_STREAM_LOCATION is a dummy address and BIT_STREAM_SIZE_WORDS is a + * dummy size. This has to replaced with the actual location of the bitstream. + * + * The 2 LSBs of the Source/Destination address when equal to 2�b01 indicates + * the last DMA command of an overall transfer. + * The 2 LSBs of the BIT_STREAM_LOCATION in this example is set to 2b01 + * indicating that this is the last DMA transfer (and the only one). + */ +#define BIT_STREAM_LOCATION 0x00400001 /* Bitstream location */ +#define BIT_STREAM_SIZE_WORDS 0xF6EC0 /* Size in Words (32 bit)*/ + +/* + * SLCR registers + */ +#define SLCR_LOCK 0xF8000004 /**< SLCR Write Protection Lock */ +#define SLCR_UNLOCK 0xF8000008 /**< SLCR Write Protection Unlock */ +#define SLCR_LVL_SHFTR_EN 0xF8000900 /**< SLCR Level Shifters Enable */ +#define SLCR_PCAP_CLK_CTRL XPAR_PS7_SLCR_0_S_AXI_BASEADDR + 0x168 /**< SLCR + * PCAP clock control register address + */ + +#define SLCR_PCAP_CLK_CTRL_EN_MASK 0x1 +#define SLCR_LOCK_VAL 0x767B +#define SLCR_UNLOCK_VAL 0xDF0D + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +int XDcfgInterruptExample(XScuGic *IntcInstPtr, XDcfg * DcfgInstance, + u16 DeviceId, u16 DcfgIntrId); +static int SetupInterruptSystem(XScuGic *IntcInstancePtr, + XDcfg *DcfgInstPtr, + u16 DcfgIntrId); + +static void DcfgIntrHandler(void *CallBackRef, u32 IntrStatus); + +/************************** Variable Definitions *****************************/ + +XDcfg DcfgInstance; /* Device Configuration Interface Instance */ +XScuGic IntcInstance; /* Instance of the Interrupt Controller driver */ + +volatile int DmaDone; +volatile int DmaPcapDone; +volatile int FpgaProgrammed; + +/*****************************************************************************/ +/** +* Main function to call the polled mode example. +* +* @param None. +* +* @return XST_SUCCESS if successful, XST_FAILURE if unsuccessful. +* +* @note None. +* +******************************************************************************/ +int main(void) +{ + int Status; + + /* + * Call the example , specify the device ID and vector ID that is + * generated in xparameters.h. + */ + Status = XDcfgInterruptExample(&IntcInstance, &DcfgInstance, + DCFG_DEVICE_ID, DCFG_INTR_ID); + if (Status != XST_SUCCESS) { + xil_printf("Dcfg Interrupt Example Test Failed\r\n"); + return XST_FAILURE; + } + + xil_printf("Successfully ran Dcfg Interrupt Example Test\r\n"); + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* This function downloads the Non secure bit stream to the FPGA fabric +* using the Device Configuration Interface. +* +* @param IntcInstPtr is a pointer to the instance of the Scu GIC driver. +* @param DcfgInstPtr is a pointer to the instance of XDcfg driver. +* @param DeviceId is the unique device id of the device. +* @param DcfgIntrId is the interrupt Id. +* +* @return XST_SUCCESS if successful, otherwise XST_FAILURE. +* +* @note None +* +****************************************************************************/ +int XDcfgInterruptExample(XScuGic *IntcInstPtr, XDcfg * DcfgInstPtr, + u16 DeviceId, u16 DcfgIntrId) +{ + int Status; + u32 IntrStsReg = 0; + u32 StatusReg; + u32 PartialCfg = 0; + + XDcfg_Config *ConfigPtr; + + /* + * Initialize the Device Configuration Interface driver. + */ + ConfigPtr = XDcfg_LookupConfig(DeviceId); + + /* + * This is where the virtual address would be used, this example + * uses physical address. + */ + Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr, + ConfigPtr->BaseAddr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + Status = XDcfg_SelfTest(DcfgInstPtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Setup the interrupt system + */ + Status = SetupInterruptSystem(IntcInstPtr, DcfgInstPtr, DcfgIntrId); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + XDcfg_SetHandler(DcfgInstPtr, (void *)DcfgIntrHandler, DcfgInstPtr); + + DmaDone = FALSE; + DmaPcapDone = FALSE; + FpgaProgrammed = FALSE; + + /* + * Check first time configuration or partial reconfiguration + */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + if (IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) { + PartialCfg = 1; + } + + /* + * Enable the pcap clock. + */ + StatusReg = Xil_In32(SLCR_PCAP_CLK_CTRL); + if (!(StatusReg & SLCR_PCAP_CLK_CTRL_EN_MASK)) { + Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); + Xil_Out32(SLCR_PCAP_CLK_CTRL, + (StatusReg | SLCR_PCAP_CLK_CTRL_EN_MASK)); + Xil_Out32(SLCR_UNLOCK, SLCR_LOCK_VAL); + } + + /* + * Disable the level-shifters from PS to PL. + */ + if (!PartialCfg) { + Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); + Xil_Out32(SLCR_LVL_SHFTR_EN, 0xA); + Xil_Out32(SLCR_LOCK, SLCR_LOCK_VAL); + } + + /* + * Select PCAP interface for partial reconfiguration + */ + if (PartialCfg) { + XDcfg_EnablePCAP(DcfgInstPtr); + XDcfg_SetControlRegister(DcfgInstPtr, XDCFG_CTRL_PCAP_PR_MASK); + } + + /* + * Clear the interrupt status bits + */ + XDcfg_IntrClear(DcfgInstPtr, (XDCFG_IXR_PCFG_DONE_MASK | + XDCFG_IXR_D_P_DONE_MASK | + XDCFG_IXR_DMA_DONE_MASK)); + + /* Check if DMA command queue is full */ + StatusReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_STATUS_OFFSET); + if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK) { + return XST_FAILURE; + } + + /* + * Enable the DMA done, DMA_PCAP Done and PCFG Done interrupts. + */ + XDcfg_IntrEnable(DcfgInstPtr, (XDCFG_IXR_DMA_DONE_MASK | + XDCFG_IXR_D_P_DONE_MASK | + XDCFG_IXR_PCFG_DONE_MASK)); + + /* + * Download bitstream in non secure mode + */ + XDcfg_Transfer(DcfgInstPtr, (u8 *)BIT_STREAM_LOCATION, + BIT_STREAM_SIZE_WORDS, + (u8 *)XDCFG_DMA_INVALID_ADDRESS, + 0, XDCFG_NON_SECURE_PCAP_WRITE); + + while (!DmaDone); + + if (PartialCfg) { + while (!DmaPcapDone); + } else { + while (!FpgaProgrammed); + /* + * Enable the level-shifters from PS to PL. + */ + Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); + Xil_Out32(SLCR_LVL_SHFTR_EN, 0xF); + Xil_Out32(SLCR_LOCK, SLCR_LOCK_VAL); + } + + Status = XST_SUCCESS; + + XDcfg_IntrDisable(DcfgInstPtr, (XDCFG_IXR_DMA_DONE_MASK | + XDCFG_IXR_D_P_DONE_MASK | + XDCFG_IXR_PCFG_DONE_MASK)); + + XScuGic_Disable(IntcInstPtr, DcfgIntrId); + + XScuGic_Disconnect(IntcInstPtr, DcfgIntrId); + + return Status; +} + +/*****************************************************************************/ +/** +* +* Callback function (called from interrupt handler) to handle Device +* configuration interrupt. +* +* @param CallBackRef is the callback reference passed from the interrupt +* handler, which in our case is a pointer to the driver instance. +* @param IntrStatus is a bit mask indicating the cause of the interrupt. +* The mask values are defined in xdcfg_hw.h. +* +* @return None. +* +* @note This function is called by the driver within interrupt context. +* +******************************************************************************/ +static void DcfgIntrHandler(void *CallBackRef, u32 IntrStatus) +{ + + if (IntrStatus & XDCFG_IXR_DMA_DONE_MASK) { + DmaDone = TRUE; + } + + if (IntrStatus & XDCFG_IXR_D_P_DONE_MASK) { + DmaPcapDone = TRUE; + } + + if (IntrStatus & XDCFG_IXR_PCFG_DONE_MASK) { + /* + * Disable PCFG DONE interrupt as this bit will remain set and will + * cause continuous interrupts. + */ + XDcfg_IntrDisable(&DcfgInstance, XDCFG_IXR_PCFG_DONE_MASK); + FpgaProgrammed = TRUE; + } +} + + +/*****************************************************************************/ +/** +* +* This function sets up the interrupt system so interrupts can occur for the +* Device Configuration. +* +* @param IntcInstancePtr is a pointer to the instance of GIC. +* @param DevcfgInstancePtr contains a pointer to the instance of the DCFG +* which is going to be connected to the interrupt +* controller. +* @param DcfgIntrId is the interrupt Id. +* +* @return XST_SUCCESS if successful, otherwise XST_FAILURE. +* +* @note None. +* +****************************************************************************/ +static int SetupInterruptSystem(XScuGic *IntcInstancePtr, + XDcfg *DcfgInstancePtr, + u16 DcfgIntrId) +{ + int Status; + + XScuGic_Config *IntcConfig; + + Xil_ExceptionInit(); + + /* + * Initialize the interrupt controller driver so that it is ready to + * use. + */ + IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID); + if (NULL == IntcConfig) { + return XST_FAILURE; + } + + Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, + IntcConfig->CpuBaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + + /* + * Connect the interrupt controller interrupt handler to the hardware + * interrupt handling logic in the processor. + */ + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, + (Xil_ExceptionHandler)XScuGic_InterruptHandler, + IntcInstancePtr); + + /* + * Connect the device driver handler that will be called when an + * interrupt for the device occurs, the handler defined above performs + * the specific interrupt processing for the device. + */ + Status = XScuGic_Connect(IntcInstancePtr, DcfgIntrId, + (Xil_InterruptHandler)XDcfg_InterruptHandler, + (void *)DcfgInstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Enable the interrupt for the DCFG. + */ + XScuGic_Enable(IntcInstancePtr, DcfgIntrId); + + /* + * Enable interrupts in the Processor. + */ + Xil_ExceptionEnable(); + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_polled_example.c b/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_polled_example.c new file mode 100644 index 00000000..c580417a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_polled_example.c @@ -0,0 +1,286 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xdcfg_polled_example.c +* +* This file contains a polled mode design example for the Device Configuration +* Interface. This example downloads a given bitstream to the FPGA fabric. +* +* BIT_STREAM_LOCATION specifies the memory location of the bitstream. +* BIT_STREAM_SIZE_WORDS specifies the size of the bitstream in words. +* User has to define these correctly for this example to work. +* +* @note None. +* +* MODIFICATION HISTORY: +* +*
+* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------- +* 1.00a hvm 11/19/10 First release +* 1.00a nm 11/26/11 Holding FPGA in reset before download and +* releasing it after bitstream download. This code +* is not checking bitstream download errors. +* 2.00a nm 05/31/12 Updated the notes in the example for CR 660139 to add +* information that the 2 LSBs of the Source/Destination +* address when equal to 2�b01 indicate the last DMA command +* of an overall transfer. +* Updated the example for CR 660835 so that input length for +* source/destination to the XDcfg_Transfer APIs is words +* (32 bit) and not bytes. +* 2.01a nm 11/21/12 Fixed CR# 688146. Modified the bitstream address. +* 2.02a nm 01/31/13 Fixed CR# 679335. +* Removed disabling and enabling AXI interface. +* Clearing the interrupts before the transfer. +* Added support for partial reconfiguration. +* 3.00a kpc 02/20/14 Renamed the DcfgInstance variable name to DcfgInstPtr +* 3.1 kpc 04/22/14 Fixed CR#780203. Enable the pcap clock if it is not set. +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are only defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID + +/* + * The BIT_STREAM_LOCATION is a dummy address and BIT_STREAM_SIZE_WORDS is a + * dummy size. This has to replaced with the actual location/size of the bitstream. + * + * The 2 LSBs of the Source/Destination address when equal to 2�b01 indicate + * the last DMA command of an overall transfer. + * The 2 LSBs of the BIT_STREAM_LOCATION in this example is set to 2b01 + * indicating that this is the last DMA transfer (and the only one). + */ +#define BIT_STREAM_LOCATION 0x00400001 /* Bitstream location */ +#define BIT_STREAM_SIZE_WORDS 0xF6EC0 /* Size in Words (32 bit)*/ + +/* + * SLCR registers + */ +#define SLCR_LOCK 0xF8000004 /**< SLCR Write Protection Lock */ +#define SLCR_UNLOCK 0xF8000008 /**< SLCR Write Protection Unlock */ +#define SLCR_LVL_SHFTR_EN 0xF8000900 /**< SLCR Level Shifters Enable */ +#define SLCR_PCAP_CLK_CTRL XPAR_PS7_SLCR_0_S_AXI_BASEADDR + 0x168 /**< SLCR + * PCAP clock control register address + */ + +#define SLCR_PCAP_CLK_CTRL_EN_MASK 0x1 +#define SLCR_LOCK_VAL 0x767B +#define SLCR_UNLOCK_VAL 0xDF0D + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +int XDcfgPolledExample(XDcfg * DcfgInstance, u16 DeviceId); + +/************************** Variable Definitions *****************************/ + +XDcfg DcfgInstance; /* Device Configuration Interface Instance */ + +/*****************************************************************************/ +/** +* +* Main function to call the polled mode example. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful +* - XST_FAILURE if unsuccessful +* +* @note None. +* +******************************************************************************/ +int main(void) +{ + int Status; + + /* + * Call the example , specify the device ID that is generated in + * xparameters.h. + */ + Status = XDcfgPolledExample(&DcfgInstance, DCFG_DEVICE_ID); + if (Status != XST_SUCCESS) { + xil_printf("Dcfg Polled Example Test Failed\r\n"); + return XST_FAILURE; + } + + xil_printf("Successfully ran Dcfg Polled Example Test\r\n"); + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* This function downloads the Non secure bit stream to the FPGA fabric +* using the Device Configuration Interface. +* +* @param DcfgInstPtr is a pointer to the instance of XDcfg driver. +* @param DeviceId is the unique device id of the device. +* +* @return +* - XST_SUCCESS if successful +* - XST_FAILURE if unsuccessful +* +* @note None +* +****************************************************************************/ +int XDcfgPolledExample(XDcfg *DcfgInstPtr, u16 DeviceId) +{ + int Status; + u32 IntrStsReg = 0; + u32 StatusReg; + u32 PartialCfg = 0; + + XDcfg_Config *ConfigPtr; + + /* + * Initialize the Device Configuration Interface driver. + */ + ConfigPtr = XDcfg_LookupConfig(DeviceId); + + /* + * This is where the virtual address would be used, this example + * uses physical address. + */ + Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr, + ConfigPtr->BaseAddr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + + Status = XDcfg_SelfTest(DcfgInstPtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Check first time configuration or partial reconfiguration + */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + if (IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) { + PartialCfg = 1; + } + + /* + * Enable the pcap clock. + */ + StatusReg = Xil_In32(SLCR_PCAP_CLK_CTRL); + if (!(StatusReg & SLCR_PCAP_CLK_CTRL_EN_MASK)) { + Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); + Xil_Out32(SLCR_PCAP_CLK_CTRL, + (StatusReg | SLCR_PCAP_CLK_CTRL_EN_MASK)); + Xil_Out32(SLCR_UNLOCK, SLCR_LOCK_VAL); + } + + /* + * Disable the level-shifters from PS to PL. + */ + if (!PartialCfg) { + Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); + Xil_Out32(SLCR_LVL_SHFTR_EN, 0xA); + Xil_Out32(SLCR_LOCK, SLCR_LOCK_VAL); + } + + /* + * Select PCAP interface for partial reconfiguration + */ + if (PartialCfg) { + XDcfg_EnablePCAP(DcfgInstPtr); + XDcfg_SetControlRegister(DcfgInstPtr, XDCFG_CTRL_PCAP_PR_MASK); + } + + /* + * Clear the interrupt status bits + */ + XDcfg_IntrClear(DcfgInstPtr, (XDCFG_IXR_PCFG_DONE_MASK | + XDCFG_IXR_D_P_DONE_MASK | + XDCFG_IXR_DMA_DONE_MASK)); + + /* Check if DMA command queue is full */ + StatusReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_STATUS_OFFSET); + if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK) { + return XST_FAILURE; + } + + /* + * Download bitstream in non secure mode + */ + XDcfg_Transfer(DcfgInstPtr, (u8 *)BIT_STREAM_LOCATION, + BIT_STREAM_SIZE_WORDS, + (u8 *)XDCFG_DMA_INVALID_ADDRESS, + 0, XDCFG_NON_SECURE_PCAP_WRITE); + + /* Poll IXR_DMA_DONE */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) != + XDCFG_IXR_DMA_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + } + + if (PartialCfg) { + /* Poll IXR_D_P_DONE */ + while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + } + } else { + /* Poll IXR_PCFG_DONE */ + while ((IntrStsReg & XDCFG_IXR_PCFG_DONE_MASK) != + XDCFG_IXR_PCFG_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + } + /* + * Enable the level-shifters from PS to PL. + */ + Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); + Xil_Out32(SLCR_LVL_SHFTR_EN, 0xF); + Xil_Out32(SLCR_LOCK, SLCR_LOCK_VAL); + } + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_reg_readback_example.c b/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_reg_readback_example.c new file mode 100644 index 00000000..43f03dde --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_reg_readback_example.c @@ -0,0 +1,464 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xdevcfg_reg_readback_example.c +* +* This file contains a design example using the DevCfg driver and hardware +* device. +* +* This example prints out the values of all the configuration registers in the +* FPGA. +* +* This example assumes that there is a UART Device or STDIO Device in the +* hardware system. +* +* @note None. +* +* MODIFICATION HISTORY: +* +*
+* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------- +* 3.1 sb 08/25/14 First Release +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xdevcfg.h" +#include "xil_cache.h" +/************************** Constant Definitions *****************************/ +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are only defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID + +/** + * @name Configuration Type1 packet headers masks + * @{ + */ +#define XDC_TYPE_SHIFT 29 +#define XDC_REGISTER_SHIFT 13 +#define XDC_OP_SHIFT 27 +#define XDC_TYPE_1 1 +#define OPCODE_READ 1 +/* @} */ + +/* + * Addresses of the Configuration Registers + */ +#define CRC 0 /* Status Register */ +#define FAR 1 /* Frame Address Register */ +#define FDRI 2 /* FDRI Register */ +#define FDRO 3 /* FDRO Register */ +#define CMD 4 /* Command Register */ +#define CTL0 5 /* Control Register 0 */ +#define MASK 6 /* MASK Register */ +#define STAT 7 /* Status Register */ +#define LOUT 8 /* LOUT Register */ +#define COR0 9 /* Configuration Options Register 0 */ +#define MFWR 10 /* MFWR Register */ +#define CBC 11 /* CBC Register */ +#define IDCODE 12 /* IDCODE Register */ +#define AXSS 13 /* AXSS Register */ +#define COR1 14 /* Configuration Options Register 1 */ +#define WBSTAR 15 /* Warm Boot Start Address Register */ +#define TIMER 16 /* Watchdog Timer Register */ +#define BOOTSTS 17 /* Boot History Status Register */ +#define CTL1 18 /* Control Register 1 */ + +/* + * Mask For IDCODE + */ +#define IDCODE_MASK 0x0FFFFFFF + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +int XDcfgRegReadExample(u16 DeviceId); +int XDcfg_GetConfigReg(XDcfg *InstancePtr, u32 ConfigReg, u32 *RegData); +u32 XDcfg_RegAddr(u8 Register,u8 OpCode, u8 Size); +/************************** Variable Definitions *****************************/ + +XDcfg DcfgInstance; /* Device Configuration Interface Instance */ + +/*****************************************************************************/ +/** +* +* Main function to call the DevCfg Reg Read example. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful +* - XST_FAILURE if unsuccessful +* +* @note None. +* +******************************************************************************/ +int main(void) +{ + int Status; + xil_printf("Dev Cfg Register Read back example\r\n"); + + Xil_DCacheDisable(); + Xil_ICacheDisable(); + + /* + * Call the example , specify the device ID that is generated in + * xparameters.h. + */ + Status = XDcfgRegReadExample(DCFG_DEVICE_ID); + if (Status != XST_SUCCESS) { + xil_printf("Dev Cfg Register Read back example Failed\r\n"); + return XST_FAILURE; + } + + xil_printf("Successfully ran Dev Cfg Register Read back example\r\n"); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function reads the configuration registers inside the FPGA. +* +* @param DeviceId is the unique device id of the device. +* +* @return +* - XST_SUCCESS if successful +* - XST_FAILURE if unsuccessful +* +* @note None. +* +******************************************************************************/ +int XDcfgRegReadExample(u16 DeviceId) +{ + int Status; + unsigned int ValueBack; + + XDcfg_Config *ConfigPtr; + + /* + * Initialize the Device Configuration Interface driver. + */ + ConfigPtr = XDcfg_LookupConfig(DeviceId); + + /* + * This is where the virtual address would be used, this example + * uses physical address. + */ + Status = XDcfg_CfgInitialize(&DcfgInstance, ConfigPtr, + ConfigPtr->BaseAddr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Run the Self test. + */ + Status = XDcfg_SelfTest(&DcfgInstance); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + xil_printf("Value of the Configuration Registers. \r\n\r\n"); + + if (XDcfg_GetConfigReg(&DcfgInstance, CRC, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" CRC -> \t %x \t\r\n", ValueBack); + + + if (XDcfg_GetConfigReg(&DcfgInstance, FAR, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" FAR -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, FDRI, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" FDRI -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, FDRO, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" FDRO -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, CMD, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" CMD -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, CTL0, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" CTL0 -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, MASK, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" MASK -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, STAT, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" STAT -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, LOUT, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" LOUT -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, COR0, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" COR0 -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, MFWR, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" MFWR -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, CBC, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" CBC -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, IDCODE, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" IDCODE -> \t %x \t\r\n", ValueBack & IDCODE_MASK); + + if (XDcfg_GetConfigReg(&DcfgInstance, AXSS, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" AXSS -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, COR1, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" COR1 -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, WBSTAR, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" WBSTAR -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, TIMER, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" TIMER -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, BOOTSTS, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" BOOTSTS -> \t %x \t\r\n", ValueBack); + + if (XDcfg_GetConfigReg(&DcfgInstance, CTL1, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + xil_printf(" CTL1 -> \t %x \t\r\n", ValueBack); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function returns the value of the specified configuration register. +* +* @param InstancePtr is a pointer to the XHwIcap instance. +* @param ConfigReg is a constant which represents the configuration +* register value to be returned. +* @param RegData is the value of the specified configuration +* register. +* +* @return +* - XST_SUCCESS if successful +* - XST_FAILURE if unsuccessful +* +* @note None. +* +****************************************************************************/ +int XDcfg_GetConfigReg(XDcfg *DcfgInstancePtr, u32 ConfigReg, u32 *RegData) +{ + u32 IntrStsReg; + u32 StatusReg; + unsigned int CmdIndex; + unsigned int CmdBuf[18]; + + /* + * Clear the interrupt status bits + */ + XDcfg_IntrClear(DcfgInstancePtr, (XDCFG_IXR_PCFG_DONE_MASK | + XDCFG_IXR_D_P_DONE_MASK | XDCFG_IXR_DMA_DONE_MASK)); + + /* Check if DMA command queue is full */ + StatusReg = XDcfg_ReadReg(DcfgInstancePtr->Config.BaseAddr, + XDCFG_STATUS_OFFSET); + if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK) { + return XST_FAILURE; + } + + /* + * Register Readback in non secure mode + * Create the data to be written to read back the + * Configuration Registers from PL Region. + */ + CmdIndex = 0; + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0x000000BB; /* Bus Width Sync Word */ + CmdBuf[CmdIndex++] = 0x11220044; /* Bus Width Detect */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xAA995566; /* Sync Word */ + CmdBuf[CmdIndex++] = 0x20000000; /* Type 1 NOOP Word 0 */ + CmdBuf[CmdIndex++] = XDcfg_RegAddr(ConfigReg,OPCODE_READ,0x1); + CmdBuf[CmdIndex++] = 0x20000000; /* Type 1 NOOP Word 0 */ + CmdBuf[CmdIndex++] = 0x20000000; /* Type 1 NOOP Word 0 */ + + XDcfg_Transfer(&DcfgInstance, (&CmdBuf[0]), + CmdIndex, RegData, 1, XDCFG_PCAP_READBACK); + + /* Poll IXR_DMA_DONE */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) != + XDCFG_IXR_DMA_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + } + + /* Poll IXR_D_P_DONE */ + while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + } + + CmdIndex = 0; + CmdBuf[CmdIndex++] = 0x30008001; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0x0000000D; /* Bus Width Sync Word */ + CmdBuf[CmdIndex++] = 0x20000000; /* Bus Width Detect */ + CmdBuf[CmdIndex++] = 0x20000000; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0x20000000; /* Bus Width Detect */ + CmdBuf[CmdIndex++] = 0x20000000; /* Dummy Word */ + + XDcfg_InitiateDma(DcfgInstancePtr, (u32)(&CmdBuf[0]), + XDCFG_DMA_INVALID_ADDRESS, CmdIndex, 0); + + /* Poll IXR_DMA_DONE */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) != + XDCFG_IXR_DMA_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + } + + /* Poll IXR_D_P_DONE */ + while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + } + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* Generates a Type 1 packet header that reads back the requested Configuration +* register. +* +* @param Register is the address of the register to be read back. +* @param OpCode is the read/write operation code. +* @param Size is the size of the word to be read. +* +* @return Type 1 packet header to read the specified register +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_RegAddr(u8 Register, u8 OpCode, u8 Size) +{ + /* + * Type 1 Packet Header Format + * The header section is always a 32-bit word. + * + * HeaderType | Opcode | Register Address | Reserved | Word Count + * [31:29] [28:27] [26:13] [12:11] [10:0] + * -------------------------------------------------------------- + * 001 xx RRRRRRRRRxxxxx RR xxxxxxxxxxx + * + * �R� means the bit is not used and reserved for future use. + * The reserved bits should be written as 0s. + * + * Generating the Type 1 packet header which involves sifting of Type 1 + * Header Mask, Register value and the OpCode which is 01 in this case + * as only read operation is to be carried out and then performing OR + * operation with the Word Length. + */ + return ( ((XDC_TYPE_1 << XDC_TYPE_SHIFT) | + (Register << XDC_REGISTER_SHIFT) | + (OpCode << XDC_OP_SHIFT)) | Size); +} diff --git a/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_selftest_example.c b/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_selftest_example.c new file mode 100644 index 00000000..a832ff6a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/examples/xdevcfg_selftest_example.c @@ -0,0 +1,166 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/******************************************************************************/ +/** +* @file xdevcfg_selftest_example.c +* +* This file contains an self test example showing the usage of the Device +* Configuration Interface Hardware and driver (XDevCfg). +* +* +* @note +* +* None +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ----------------------------------------------- +* 1.00 sdm 05/25/11 First release. +*+* +*******************************************************************************/ + +/***************************** Include Files **********************************/ + +#include "xparameters.h" +#include "xdevcfg.h" +#include "xil_printf.h" + +/************************** Constant Definitions ******************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are only defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID + + +/**************************** Type Definitions ********************************/ + +/***************** Macros (Inline Functions) Definitions **********************/ + +/************************** Function Prototypes *******************************/ + +int DcfgSelfTestExample(u16 DeviceId); + +/************************** Variable Definitions ******************************/ + +XDcfg DcfgInstance; /* Device Configuration Interface Instance */ + +/******************************************************************************/ +/** +* +* Main function to call the Device Configuration Interface Selftest example. +* +* @param None +* +* @return +* - XST_SUCCESS if successful +* - XST_FAILURE if unsuccessful +* +* @note None +* +*******************************************************************************/ +#ifndef TESTAPP_GEN +int main(void) +{ + int Status; + + xil_printf("DevCfg Selftest Example \r\n"); + + /* + * Call the example, specify the device ID that is generated in + * xparameters.h + */ + Status = DcfgSelfTestExample(DCFG_DEVICE_ID); + if (Status != XST_SUCCESS) { + xil_printf("DevCfg Selftest Example Failed\r\n"); + return XST_FAILURE; + } + + xil_printf("Successfully ran DevCfg Selftest Example\r\n"); + return XST_SUCCESS; +} +#endif + +/*****************************************************************************/ +/** +* +* This function does a selftest on the Device Configuration device and +* XDevCfg driver as an example. The purpose of this function is to illustrate +* the usage of the XDevCfg driver. +* +* +* @param DeviceId is the XPAR_
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for +* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer +* APIs is words (32 bit) and not bytes. +* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs +* to add information that 2 LSBs of the Source/Destination +* address when equal to 2�b01 indicate the last DMA command +* of an overall transfer. +* Updated the XDcfg_Transfer function to use the +* Destination Address passed to this API for secure transfers +* instead of using 0xFFFFFFFF for CR 662197. This issue was +* resulting in the failure of secure transfers of +* non-bitstream images. +* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the +* QUARTER_PCAP_RATE_EN bit in the control register for +* non secure writes for CR 675543. +* 2.02a nm 01/31/13 Fixed CR# 679335. +* Added Setting and Clearing the internal PCAP loopback. +* Removed code for enabling/disabling AES engine as BootROM +* locks down this setting. +* Fixed CR# 681976. +* Skip Checking the PCFG_INIT in case of non-secure DMA +* loopback. +* Fixed CR# 699558. +* XDcfg_Transfer fails to transfer data in loopback mode. +* 2.03a nm 04/19/13 Fixed CR# 703728. +* Updated the register definitions as per the latest TRM +* version UG585 (v1.4) November 16, 2012. +* 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister +* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function +* updated driver code with != instead of ==, +* while checking for Interrupt Status with DMA and +* PCAP Done Mask +* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, +* XDCFG_INT_STS_OFFSET) & +* XDCFG_IXR_D_P_DONE_MASK) != +* XDCFG_IXR_D_P_DONE_MASK); +* +* +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* Initialize the Device Config Interface driver. This function +* must be called before other functions of the driver are called. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param ConfigPtr is the config structure. +* @param EffectiveAddress is the base address for the device. It could be +* a virtual address if address translation is supported in the +* system, otherwise it is the physical address. +* +* @return +* - XST_SUCCESS if initialization was successful. +* - XST_DEVICE_IS_STARTED if the device has already been started. +* +* @note The very first APB access to the Device Configuration Interface +* block needs to be a write to the UNLOCK register with the value +* of 0x757BDF0D. This step is to be done once after reset, any +* other APB access has to come after this. The APB access is +* considered illegal if the step is not done or if it is done +* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high, +* the following additional actions would be carried out. +* In other words, if all bits are low, the following steps are not +* done. +* 1. AES is disabled +* 2. All APB writes disabled +* 3. SoC debug fully enabled +* +******************************************************************************/ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * If the device is started, disallow the initialize and return a + * status indicating it is started. This allows the user to stop the + * device and reinitialize, but prevents a user from inadvertently + * initializing. + */ + if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Copy configuration into instance. + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + + /* + * Save the base address pointer such that the registers of the block + * can be accessed and indicate it has not been started yet. + */ + InstancePtr->Config.BaseAddr = EffectiveAddress; + InstancePtr->IsStarted = 0; + + + /* Unlock the Device Configuration Interface */ + XDcfg_Unlock(InstancePtr); + + /* + * Indicate the instance is ready to use, successfully initialized. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* The functions enables the PCAP interface by setting the PCAP mode bit in the +* control register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note Enable FPGA programming from PCAP interface. Enabling this bit +* disables all the external interfaces from programming of FPGA +* except for ICAP. The user needs to ensure that the FPGA is +* programmed through either PCAP or ICAP. +* +*****************************************************************************/ +void XDcfg_EnablePCAP(XDcfg *InstancePtr) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK)); + +} + +/****************************************************************************/ +/** +* +* The functions disables the PCAP interface by clearing the PCAP mode bit in +* the control register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_DisablePCAP(XDcfg *InstancePtr) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK))); + +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the 32 bit mask data to be written to the Register. +* The mask definitions are defined in the xdevcfg_hw.h file. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg | Mask)); + +} + +/****************************************************************************/ +/** +* +* The function Clears the specified bit positions of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the 32 bit value which holds the bit positions to be cleared. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg & ~Mask)); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Control +* Register. +* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Control Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Lock Register. These bits +* can only be set to a 1. They will be cleared after a Power On Reset. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Lock Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Lock +* Register. +* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Lock Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Configuration Register with the +* given value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Configuration Register with the +* given value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Config +* Register. +* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET); + +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Status +* Register. +* Use the XDCFG_STATUS_*_MASK constants defined in +* xdevcfg_hw.h to interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Status Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the ROM Shadow Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note This register is can only be written and is used to control the +* RAM shadow of 32 bit 4K page ROM pages in user mode +* +*****************************************************************************/ +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET, + Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Software ID Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return 32 Bit boot software ID. +* +* @note This register is locked for write once the system enters +* usermode. Hence API for reading the register only is provided. +* +*****************************************************************************/ +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Software ID Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the bit mask for the feature in Miscellaneous Control +* Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the feature to be set. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegData; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET, + (RegData | Mask)); +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return 32 Bit boot software ID. +* +* @note This register is locked for write once the system enters +* usermode. Hence API to reading the register only is provided. +* +*****************************************************************************/ +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Miscellaneous Control Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET); +} + +/******************************************************************************/ +/** +* +* This function checks if DMA command queue is full. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return XST_SUCCESS is the DMA is busy +* XST_FAILURE if the DMA is idle +* +* @note The DMA queue has a depth of two. +* +****************************************************************************/ +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr) +{ + + u32 RegData; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Read the PCAP status register for DMA status */ + RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_STATUS_OFFSET); + + if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK){ + return XST_SUCCESS; + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** +* +* This function initiates the DMA transfer. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* +* @return None. +* +* @note It is the responsibility of the caller function to ensure that +* correct values are passed to this function. +* +* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) +* address when equal to 2�b01 indicates the last DMA command of +* an overall transfer. +* +****************************************************************************/ +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength) +{ + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_SRC_ADDR_OFFSET, + SourcePtr); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_DEST_ADDR_OFFSET, + DestPtr); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_SRC_LEN_OFFSET, + SrcWordLength); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_DEST_LEN_OFFSET, + DestWordLength); +} + +/******************************************************************************/ +/** +* +* This function Implements the DMA Read Command. This command is used to +* transfer the image data from FPGA to the external memory. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* +* @return - XST_INVALID_PARAM if source address/length is invalid. +* - XST_SUCCESS if DMA transfer initiated properly. +* +* @note None. +* +****************************************************************************/ +static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, + u32 SrcWordLength, u32 DestPtr, + u32 DestWordLength) +{ + u32 IntrReg; + + /* + * Send READ Frame command to FPGA + */ + XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS, + SrcWordLength, 0); + + /* + * Store the enabled interrupts to enable before the actual read + * transfer is initiated and Disable all the interrupts temporarily. + */ + IntrReg = XDcfg_IntrGetEnabled(InstancePtr); + XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK); + + /* + * Wait till you get the DMA done for the read command sent + */ + while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET) & + XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK); + /* + * Enable the previously stored Interrupts . + */ + XDcfg_IntrEnable(InstancePtr, IntrReg); + + /* + * Initiate the DMA write command. + */ + XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr, + 0, DestWordLength); + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** +* +* This function starts the DMA transfer. This function only starts the +* operation and returns before the operation may be completed. +* If the interrupt is enabled, an interrupt will be generated when the +* operation is completed, otherwise it is necessary to poll the Status register +* to determine when it is completed. It is the responsibility of the caller to +* determine when the operation is completed by handling the generated interrupt +* or polling the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* @param TransferType contains the type of PCAP transfer being requested. +* The definitions can be found in the xdevcfg.h file. +* @return +* - XST_SUCCESS.if DMA transfer initiated successfully +* - XST_DEVICE_BUSY if DMA is busy +* - XST_INVALID_PARAM if invalid Source / Destination address +* is sent or an invalid Source / Destination length is +* sent +* +* @note It is the responsibility of the caller to ensure that the cache +* is flushed and invalidated both before the DMA operation is +* started and after the DMA operation completes if the memory +* pointed to is cached. The caller must also ensure that the +* pointers contain physical address rather than a virtual address +* if address translation is being used. +* +* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) +* address when equal to 2�b01 indicates the last DMA command of +* an overall transfer. +* +*****************************************************************************/ +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType) +{ + + u32 CtrlReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) { + return XST_DEVICE_BUSY; + } + + /* + * Check whether the fabric is in initialized state + */ + if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET) + & XDCFG_STATUS_PCFG_INIT_MASK) == 0) { + /* + * We don't need to check PCFG_INIT to be high for + * non-encrypted loopback transfers. + */ + if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) { + return XST_FAILURE; + } + } + + if ((TransferType == XDCFG_SECURE_PCAP_WRITE) || + (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) { + + /* Check for valid source pointer and length */ + if ((!SourcePtr) || (SrcWordLength == 0)) { + return XST_INVALID_PARAM; + } + + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) { + /* + * Clear QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every clock + */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + + } + if (TransferType == XDCFG_SECURE_PCAP_WRITE) { + /* + * AES engine handles only 8 bit data every clock cycle. + * Hence, Encrypted PCAP data which is 32 bit data can + * only be sent in every 4 clock cycles. Set the control + * register QUARTER_PCAP_RATE_EN bit to achieve this + * operation. + */ + XDcfg_SetControlRegister(InstancePtr, + XDCFG_CTRL_PCAP_RATE_EN_MASK); + } + + XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, + (u32)DestPtr, SrcWordLength, DestWordLength); + + } + + if (TransferType == XDCFG_PCAP_READBACK) { + + if ((!DestPtr) || (DestWordLength == 0)) { + + return XST_INVALID_PARAM; + } + + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + /* + * For PCAP readback of FPGA configuration register or memory, + * the read command is first sent (written) to the FPGA fabric + * which responds by returning the required read data. Read data + * from the FPGA is captured if pcap_radata_v is active.A DMA + * read transfer is required to obtain the readback command, + * which is then sent to the FPGA, followed by a DMA write + * transfer to support this mode of operation. + */ + return XDcfg_PcapReadback(InstancePtr, + (u32)SourcePtr, SrcWordLength, + (u32)DestPtr, DestWordLength); + } + + + if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) || + (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) { + + if ((!SourcePtr) || (SrcWordLength == 0) || + (!DestPtr) || (DestWordLength == 0)) { + return XST_INVALID_PARAM; + } + + if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) { + /* Enable internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg | + XDCFG_MCTRL_PCAP_LPBK_MASK)); + + /* + * Clear QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every clock + */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + + } + if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) { + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + /* + * Set the QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every 4 clock + * cycles, this is required for encrypted data. + */ + XDcfg_SetControlRegister(InstancePtr, + XDCFG_CTRL_PCAP_RATE_EN_MASK); + } + + XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, + (u32)DestPtr, SrcWordLength, DestWordLength); + } + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg.h b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg.h new file mode 100644 index 00000000..3902ed43 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg.h @@ -0,0 +1,392 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.h +* +* The is the main header file for the Device Configuration Interface of the Zynq +* device. The device configuration interface has three main functionality. +* 1. AXI-PCAP +* 2. Security Policy +* 3. XADC +* This current version of the driver supports only the AXI-PCAP and Security +* Policy blocks. There is a separate driver for XADC. +* +* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. +* DMA embedded in the AXI PCAP provides the master interface to +* the Device configuration block for any DMA transfers. The data transfer can +* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip +* RAM/DDR/peripheral memory). +* +* The current driver only supports the downloading the FPGA bitstream and +* readback of the decrypted image (sort of loopback). +* The driver does not know what information needs to be written to the FPGA to +* readback FPGA configuration register or memory data. The application above the +* driver should take care of creating the data that needs to be downloaded to +* the FPGA so that the bitstream can be readback. +* This driver also does not support the reading of the internal registers of the +* PCAP. The driver has no knowledge of the PCAP internals. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Device Configuration device. +* +* XDcfg_CfgInitialize() API is used to initialize the Device Configuration +* Interface. The user needs to first call the XDcfg_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XDcfg_CfgInitialize() API. +* +* Interrupts +* The Driver implements an interrupt handler to support the interrupts provided +* by this interface. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XDcfg driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for +* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer +* APIs is words (32 bit) and not bytes. +* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs +* to add information that 2 LSBs of the Source/Destination +* address when equal to 2�b01 indicate the last DMA command +* of an overall transfer. +* Destination Address passed to this API for secure transfers +* instead of using 0xFFFFFFFF for CR 662197. This issue was +* resulting in the failure of secure transfers of +* non-bitstream images. +* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly +* set the mask instead of oring it with the +* value read from the interrupt status register +* Added defines for the PS Version bits, +* removed the FIFO Flush bits from the +* Miscellaneous Control Reg. +* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface +* and XDcfg_SelectPcapInterface APIs for CR 643295 +* The user has to call the XDcfg_SelectIcapInterface API +* for the PL reconfiguration using AXI HwIcap. +* Updated the XDcfg_Transfer API to clear the +* QUARTER_PCAP_RATE_EN bit in the control register for +* non secure writes for CR 675543. +* 2.02a nm 01/31/13 Fixed CR# 679335. +* Added Setting and Clearing the internal PCAP loopback. +* Removed code for enabling/disabling AES engine as BootROM +* locks down this setting. +* Fixed CR# 681976. +* Skip Checking the PCFG_INIT in case of non-secure DMA +* loopback. +* Fixed CR# 699558. +* XDcfg_Transfer fails to transfer data in loopback mode. +* Fixed CR# 701348. +* Peripheral test fails with Running +* DcfgSelfTestExample() in SECURE bootmode. +* 2.03a nm 04/19/13 Fixed CR# 703728. +* Updated the register definitions as per the latest TRM +* version UG585 (v1.4) November 16, 2012. +* 3.0 adk 10/12/13 Updated as per the New Tcl API's +* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister +* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function +* updated driver code with != instead of ==, +* while checking for Interrupt Status with DMA and +* PCAP Done Mask +* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, +* XDCFG_INT_STS_OFFSET) & +* XDCFG_IXR_D_P_DONE_MASK) != +* XDCFG_IXR_D_P_DONE_MASK); +* A new example has been added to read back the +* configuration registers from the PL region. +* xdevcfg_reg_readback_example.c +* +*+* +******************************************************************************/ +#ifndef XDCFG_H /* prevent circular inclusions */ +#define XDCFG_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" +#include "xstatus.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* Types of PCAP transfers */ + +#define XDCFG_NON_SECURE_PCAP_WRITE 1 +#define XDCFG_SECURE_PCAP_WRITE 2 +#define XDCFG_PCAP_READBACK 3 +#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 +#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 + + +/**************************** Type Definitions *******************************/ +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* unimportant to the driver component, so it is a void pointer. +* @param Status is the Interrupt status of the XDcfg device. +*/ +typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XDcfg_Config; + +/** + * The XDcfg driver instance data. + */ +typedef struct { + XDcfg_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device Configuration Interface + * is running + */ + XDcfg_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XDcfg; + +/****************************************************************************/ +/** +* +* Unlock the Device Config Interface block. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_Unlock(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_Unlock(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + + + +/****************************************************************************/ +/** +* +* Get the version number of the PS from the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return Version of the PS. +* +* @note C-style signature: +* void XDcfg_GetPsVersion(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_GetPsVersion(InstancePtr) \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MCTRL_OFFSET)) & \ + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + + + +/****************************************************************************/ +/** +* +* Read the multiboot config register value. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_ReadMultiBootConfig(InstancePtr) \ + XDcfg_ReadReg((InstancePtr)->Config.BaseAddr + \ + XDCFG_MULTIBOOT_ADDR_OFFSET) + + +/****************************************************************************/ +/** +* +* Selects ICAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectIcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + +/****************************************************************************/ +/** +* +* Selects PCAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectPcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) + + + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xdevcfg_sinit.c. + */ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xdevcfg_selftest.c + */ +int XDcfg_SelfTest(XDcfg *InstancePtr); + +/* + * Interface functions in xdevcfg.c + */ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + +void XDcfg_EnablePCAP(XDcfg *InstancePtr); + +void XDcfg_DisablePCAP(XDcfg *InstancePtr); + +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); + +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); + +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); + +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); + +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); + +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); + +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); + +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength); + +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); + +/* + * Interrupt related function prototypes implemented in xdevcfg_intr.c + */ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); + +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); + +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_InterruptHandler(XDcfg *InstancePtr); + +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_g.c b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_g.c new file mode 100644 index 00000000..d00fca60 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_g.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_g.c +* +* This file contains a table that specifies the configuration of the Device +* Configuration Interface device in the system. Each device should have an entry +* in the table. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Prototypes ******************************/ + +/** + * This table contains configuration information for each Device Config + * Interface instance in the system. + */ +XDcfg_Config XDcfg_ConfigTable[1] = { + { + XPAR_XDCFG_0_DEVICE_ID, + XPAR_XDCFG_0_BASEADDR, + } +}; diff --git a/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_hw.c b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_hw.c new file mode 100644 index 00000000..f5b2f68e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_hw.c @@ -0,0 +1,110 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.c +* +* This file contains the implementation of the interface reset functionality +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 2.04a kpc 10/07/13 First release +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** +* This function perform the reset sequence to the given devcfg interface by +* configuring the appropriate control bits in the devcfg specifc registers +* the devcfg reset squence involves the following steps +* Disable all the interuupts +* Clear the status +* Update relevant config registers with reset values +* Disbale the looopback mode and pcap rate enable +* +* @param BaseAddress of the interface +* +* @return N/A +* +* @note +* This function will not modify the slcr registers that are relavant for +* devcfg controller +******************************************************************************/ +void XDcfg_ResetHw(u32 BaseAddr) +{ + u32 Regval = 0; + + /* Mask the interrupts */ + XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET, + XDCFG_IXR_ALL_MASK); + /* Clear the interuupt status */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET); + XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval); + /* Clear the source address register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0); + /* Clear the destination address register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0); + /* Clear the source length register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0); + /* Clear the destination length register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0); + /* Clear the loopback enable bit */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET); + Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK; + XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval); + /*Reset the configuration register to reset value */ + XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET, + XDCFG_CONFIG_RESET_VALUE); + /*Disable the PCAP rate enable bit */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET); + Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK; + XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval); + +} diff --git a/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_hw.h b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_hw.h new file mode 100644 index 00000000..33443495 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_hw.h @@ -0,0 +1,392 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.h +* +* This file contains the hardware interface to the Device Config Interface. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +* 2.01a nm 08/01/12 Added defines for the PS Version bits, +* removed the FIFO Flush bits from the +* Miscellaneous Control Reg +* 2.03a nm 04/19/13 Fixed CR# 703728. +* Updated the register definitions as per the latest TRM +* version UG585 (v1.4) November 16, 2012. +* 2.04a kpc 10/07/13 Added function prototype. +* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value. +*+* +******************************************************************************/ +#ifndef XDCFG_HW_H /* prevent circular inclusions */ +#define XDCFG_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ +#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ +#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ +#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ +#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ +#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ + +/* @} */ + +/** @name Control Register Bit definitions + * @{ + */ + +#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into + * Secure Reset + */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to + * Reset FPGA + */ +#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ +#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data + * to FPGA every 4 PCAP + * cycles + */ +#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ +#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ +#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ +#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ +#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure + * Status mask + */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive + * Debug Enable + */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive + * Debug Enable + */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ + +/* @} */ + +/** @name Lock register bit definitions + * @{ + */ + +#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ +#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and + * USER_MODE + */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks + * security config + * including: DAP_En, + * DBGEN,, + * NIDEN, SPNIEN + */ +/*@}*/ + + + +/** @name Config Register Bit definitions + * @{ + */ +#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO + * Threshold Mask + */ +#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold + * Mask + */ +#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active + * clock edge + */ +#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active + * clock edge + */ +#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address + * increment mask + */ +#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination + * address increment + * mask + */ +/* @} */ + + +/** @name Interrupt Status/Mask Register Bit definitions + * @{ + */ +#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during + * HIZ + */ +#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration + * done + */ +#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ +#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during + * configuration + */ +#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration + * reset + */ +#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address + * or Data or response + * timeout + */ +#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response + * error + */ +#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or + * response timeout + */ +#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response + * error + */ +#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ +#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than + * threshold */ +#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than + * threshold */ +#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ +#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue + * overflow + */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ +#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP + * transfers Done + */ +#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer + * length error + */ +#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ +#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ +#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ +#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ +#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge + * of Init Signal + */ +#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge + * of Init Signal + */ +#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + + +#define XDCFG_IXR_ALL_MASK 0x00F7F8EF + + + +/* @} */ + + +/** @name Status Register Bit definitions + * @{ + */ +#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command + * Queue full + */ +#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command + * Queue empty + */ +#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of + * completed DMA + * transfers + */ +#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ +#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ + +#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO + * during HIZ + */ +#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config + * done + */ +#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ +#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during + * config + */ +#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset + * POR Status + */ +#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB + * access + */ +#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config + * reset status + */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init + * Status + */ +#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 + /**< BBRAM key + * disable + */ +#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security + * Enable Status + */ +#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG + * Disable + * status + */ +/* @} */ + + +/** @name DMA Source/Destination Transfer Length Register Bit definitions + * @{ + */ +#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ +/*@}*/ + + + + +/** @name Miscellaneous Control Register Bit definitions + * @{ + */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ +/* @} */ + +/** @name FIFO Threshold Bit definitions + * @{ + */ + +#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ +#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ +#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ +#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ +/* @}*/ + + +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ +#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ +#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base + * address + */ +#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XDcfg_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the devcfg interface + */ +void XDcfg_ResetHw(u32 BaseAddr); +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_intr.c b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_intr.c new file mode 100644 index 00000000..ae77685f --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_intr.c @@ -0,0 +1,307 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_intr.c +* +* Contains the implementation of interrupt related functions of the XDcfg +* driver. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly +* set the mask instead of oring it with the +* value read from the interrupt status register +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* This function enables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be enabled. +* Bit positions of 1 will be enabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XDCFG_INT_* bits defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Enable the specified interrupts in the Interrupt Mask Register. + */ + RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET); + RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET, + RegValue); +} + + +/****************************************************************************/ +/** +* +* This function disables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be disabled. +* Bit positions of 1 will be disabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XDCFG_INT_* bits defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Disable the specified interrupts in the Interrupt Mask Register. + */ + RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET); + RegValue |= (Mask & XDCFG_IXR_ALL_MASK); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET, + RegValue); +} +/****************************************************************************/ +/** +* +* This function returns the enabled interrupts read from the Interrupt Mask +* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the IMR. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Mask Register. + */ + return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET)); +} + +/****************************************************************************/ +/** +* +* This function returns the interrupt status read from Interrupt Status +* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Interrupt +* Status register. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Status register. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function clears the specified interrupts in the Interrupt Status +* Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be cleared. +* Bit positions of 1 will be cleared. Bit positions of 0 will not +* change the previous interrupt status. This mask is formed by +* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET, + Mask); + +} + +/*****************************************************************************/ +/** +* The interrupt handler for the Device Config Interface. +* +* Events are signaled to upper layer for proper handling. +* +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XDcfg_InterruptHandler(XDcfg *InstancePtr) +{ + u32 IntrStatusReg; + + /* + * Assert validates the input arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Interrupt status register. + */ + IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET); + + /* + * Write the status back to clear the interrupts so that no + * subsequent interrupts are missed while processing this interrupt. + * This also does the DMA acknowledgment automatically. + */ + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET, IntrStatusReg); + + /* + * Signal application that there are events to handle. + */ + InstancePtr->StatusHandler(InstancePtr->CallBackRef, + IntrStatusReg); + +} + +/****************************************************************************/ +/** +* +* This function sets the handler that will be called when an event (interrupt) +* occurs that needs application's attention. +* +* @param InstancePtr is a pointer to the XDcfg instance +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return None. +* +* @note None. +* +* +*****************************************************************************/ +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef) +{ + /* + * Asserts validate the input arguments + * CallBackRef not checked, no way to know what is valid + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallBackFunc != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc; + InstancePtr->CallBackRef = CallBackRef; +} diff --git a/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_selftest.c b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_selftest.c new file mode 100644 index 00000000..97caebe1 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_selftest.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_selftest.c +* +* Contains diagnostic self-test functions for the XDcfg driver. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +* 2.02a nm 02/27/13 Fixed CR# 701348. +* Peripheral test fails with Running +* DcfgSelfTestExample() in SECURE bootmode. +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* Run a self-test on the Device Configuration Interface. This test does a +* control register write and reads back the same value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return +* - XST_SUCCESS if self-test was successful. +* - XST_FAILURE if fails. +* +* @note None. +* +******************************************************************************/ +int XDcfg_SelfTest(XDcfg *InstancePtr) +{ + u32 OldCfgReg; + u32 CfgReg; + int Status = XST_SUCCESS; + + /* + * Assert to ensure the inputs are valid and the instance has been + * initialized. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + OldCfgReg = XDcfg_GetControlRegister(InstancePtr); + + XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK); + + CfgReg = XDcfg_GetControlRegister(InstancePtr); + + if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) { + + Status = XST_FAILURE; + } + + /* + * Restore the original values of the register + */ + XDcfg_SetControlRegister(InstancePtr, OldCfgReg); + + return Status; +} diff --git a/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_sinit.c b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_sinit.c new file mode 100644 index 00000000..9b8d779a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg_sinit.c @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdevcfg_sinit.c +* +* This file contains method for static initialization (compile-time) of the +* driver. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* Lookup the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId) +{ + extern XDcfg_Config XDcfg_ConfigTable[]; + XDcfg_Config *CfgPtr = NULL; + int Index; + + for (Index = 0; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) { + if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XDcfg_ConfigTable[Index]; + break; + } + } + + return (CfgPtr); +}