From fd5e7146a117bec045d20225e18204a6b0ece61d Mon Sep 17 00:00:00 2001 From: Kinjal Pravinbhai Patel Date: Wed, 13 May 2015 12:43:24 +0530 Subject: [PATCH] bsp: a9: change in asm_vectors and xil_exception This patch modifies asm_vectors.s and xil_exception.c to print the address for instruction causing data abort and prefetch abort in default handler Signed-off-by: Kinjal Pravinbhai Patel --- .../src/cortexa9/armcc/asm_vectors.s | 13 ++++++++++-- .../standalone/src/cortexa9/gcc/asm_vectors.S | 20 +++++++++---------- .../src/cortexa9/iccarm/asm_vectors.s | 12 ++++++++++- .../standalone/src/cortexa9/xil_exception.c | 11 ++++++++-- 4 files changed, 40 insertions(+), 16 deletions(-) diff --git a/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s b/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s index 681a23af..9ef820da 100644 --- a/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s +++ b/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s @@ -44,6 +44,9 @@ ; 3.11a asa 9/17/13 Added support for neon. ; 4.00 pkp 01/22/14 Modified return addresses for interrupt ; handlers +; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data +; abort and prefetch abort into DataAbortAddr and +; PrefetchAbortAddr for further use to fix CR#854523 ; ; ; @note @@ -62,6 +65,8 @@ IMPORT SWInterrupt IMPORT DataAbortInterrupt IMPORT PrefetchAbortInterrupt + IMPORT DataAbortAddr + IMPORT PrefetchAbortAddr AREA |.vectors|, CODE REQUIRE8 {TRUE} @@ -137,18 +142,22 @@ SVCHandler ; SWI handler ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code movs pc, lr ; adjust return - DataAbortHandler ; Data Abort handler stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldr r0, =DataAbortAddr + sub r1, lr,#8 + str r1, [r0] ;Address of instruction causing data abort bl DataAbortInterrupt ;DataAbortInterrupt :call C function here ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code subs pc, lr, #8 ; adjust return PrefetchAbortHandler ; Prefetch Abort handler stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldr r0, =PrefetchAbortAddr + sub r1, lr,#4 + str r1, [r0] ;Address of instruction causing prefetch abort bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code subs pc, lr, #4 ; adjust return - END diff --git a/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S b/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S index 9db6f766..a154aaee 100644 --- a/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S +++ b/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S @@ -47,6 +47,9 @@ * 4.00a pkp 22/01/14 Modified return addresses for interrupt * handlers (DataAbortHandler and SVCHandler) * to fix CR#767251 +* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data +* abort and prefetch abort into DataAbortAddr and +* PrefetchAbortAddr for further use to fix CR#854523 * * * @note @@ -61,18 +64,8 @@ .org 0 .text -.globl _boot .globl _vector_table -.globl FIQInterrupt -.globl IRQInterrupt -.globl SWInterrupt -.globl DataAbortInterrupt -.globl PrefetchAbortInterrupt - -.globl IRQHandler -.globl prof_pc - .section .vectors _vector_table: B _boot @@ -176,6 +169,9 @@ DataAbortHandler: /* Data Abort handler */ dsb #endif stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =DataAbortAddr + sub r1, lr, #8 + str r1, [r0] /* Stores instruction causing data abort */ bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */ @@ -188,6 +184,9 @@ PrefetchAbortHandler: /* Prefetch Abort handler */ dsb #endif stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =PrefetchAbortAddr + sub r1, lr, #4 + str r1, [r0] /* Stores instruction causing prefetch abort */ bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */ @@ -195,5 +194,4 @@ PrefetchAbortHandler: /* Prefetch Abort handler */ subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */ - .end diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s b/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s index 311b002b..c66e1879 100644 --- a/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s +++ b/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s @@ -43,6 +43,9 @@ ; 1.00a Initial version ; 4.2 pkp 06/27/14 Modified return addresses for interrupt ; handlers +; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data +; abort and prefetch abort into DataAbortAddr and +; PrefetchAbortAddr for further use to fix CR#854523 ; ; ; @note @@ -80,6 +83,8 @@ IMPORT SWInterrupt IMPORT DataAbortInterrupt IMPORT PrefetchAbortInterrupt + IMPORT DataAbortAddr + IMPORT PrefetchAbortAddr _vector_table ARM @@ -135,15 +140,20 @@ SVCHandler ; SWI handler ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code movs pc, lr ; adjust return - DataAbortHandler ; Data Abort handler stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldr r0, =DataAbortAddr + sub r1, lr,#8 + str r1, [r0] ;Address of instruction causing data abort bl DataAbortInterrupt ;DataAbortInterrupt :call C function here ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code subs pc, lr, #8 ; adjust return PrefetchAbortHandler ; Prefetch Abort handler stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldr r0, =PrefetchAbortAddr + sub r1, lr,#4 + str r1, [r0] ;Address of instruction causing prefetch abort bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code subs pc, lr, #4 ; adjust return diff --git a/lib/bsp/standalone/src/cortexa9/xil_exception.c b/lib/bsp/standalone/src/cortexa9/xil_exception.c index 5e813553..0cf089c4 100644 --- a/lib/bsp/standalone/src/cortexa9/xil_exception.c +++ b/lib/bsp/standalone/src/cortexa9/xil_exception.c @@ -50,6 +50,8 @@ * DataAbortHandler and PrefetchAbortHandler respectively * Both handlers are registers in vector table entries * using XExc_VectorTable +* 5.1 pkp 05/13/15 Added debugging message to print address of instruction +* causing data abort and prefetch abort * * *****************************************************************************/ @@ -89,6 +91,9 @@ XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = {Xil_ExceptionNullHandler, NULL}, }; +u32 DataAbortAddr; /* Address of instruction causing data abort */ +u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */ + /*****************************************************************************/ /****************************************************************************/ @@ -209,7 +214,8 @@ void Xil_DataAbortHandler(void *CallBackRef){ { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); FaultStatus = Reg; } #endif - xdbg_printf(XDBG_DEBUG_ERROR, "Data abort with Data Fault Status Register %x\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr); while(1) { ; } @@ -238,7 +244,8 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){ { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); FaultStatus = Reg; } #endif - xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr); while(1) { ; }