From fe56ba6ef0cb2c11ede6a4f4aba591581f18ebde Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Thu, 15 Jan 2015 11:05:21 -0800 Subject: [PATCH] dp: rx: Added interrupt registers. Signed-off-by: Andrei-Liviu Simion --- .../drivers/dp/src/xdprx_hw.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h b/XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h index b7295cbc..d540e512 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h +++ b/XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h @@ -106,6 +106,28 @@ recent AUX request. */ /* @} */ +/** @name DPRX core registers: Interrupt registers. + * @{ + */ +#define XDPRX_INTERRUPT_CAUSE 0x040 /**< Indicates the cause of + pending host interrupts + for stream 1, training, + payload allocation, and + for the AUX channel. */ +#define XDPRX_INTERRUPT_MASK_1 0x044 /**< Masks the specified + interrupt sources. */ +#define XDPRX_INTERRUPT_CAUSE_1 0x048 /**< Indicates the cause of a + pending host interrupts + for streams 2, 3, 4. */ +#define XDPRX_HSYNC_WIDTH 0x050 /**< Controls the timing of the + active-high horizontal + sync pulse generated + by the display timing + generator (DTG). */ +#define XDPRX_FAST_I2C_DIVIDER 0x060 /**< Fast I2C mode clock divider + value. */ +/* @} */ + /******************* Macros (Inline Functions) Definitions ********************/ /** @name Register access macro definitions.