This patch adds support for iar compiler into standalone BSP for cortexa9
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Some of the LWIP options like memp_num_tcpip_msg, memp_num_api_msg
are configurable from LWIP settings, but they are not actually
set when compiling the LWIP library. This patch modifies the LWIP
tcl to update them.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Currently, the AXI Ethernet adapter is configured to support only
Marvel PHYs which exist on all Xilinx boards. This patch allows
to get the auto-negotiation speed of any PHY using IEEE specification.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Change CR_RESET_STATE defintion to include required bits to be set and
reset. When writing to the configuration register, read the register and
OR the required value to leave the reserved bits untouched.
Changes done in XQspiPs_Reset function and HW reset function.
The default value written was expanded to include setting hold bit and
using manual chip select (This is recommended and already explicitly
followed in all the examples).
Removed check for register values in selftest because a reset is done
in just the previous step where default values are already written.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
