- Code cleanup to remove interrupt handler registration.
Subsystem does not have interrupts
- Updated sub-core init routines to load default filter
coefficients for scaler and chroma resamplers
- Added layer 2 registers for chroma resamplers
- Updated VDMA Read/Write interface to work with color depth
instead of Bytes/Pixel
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
- IP updated to add multiple pixel/clk support.
- Added default filter coefficient table for 6/8/10/12 taps
- Added API to load default coefficients or allow user to load
externally defined coefficients
- Peformed code cleanup to remove coefficient generation logic
(scaler to use fixed coefficients)
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
-Added filter coefficient table for 4/6/8/10 taps.
-Added API to load the default coefficients
-Added API to allow user to load coefficients
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
- IP updated to add multiple pixel/clk support.
- Added default filter coefficient table for 6/8/10/12 taps
- Added API to load default coefficients or allow user to load
externally defined coefficients
- Peformed code cleanup to remove coefficient generation logic
(scaler to use fixed coefficients)
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
-Added filter coefficient table for 4/6/8/10 taps.
-Added API to load the default coefficients
-Added API to allow user to load coefficients
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
IP updated to add multiple pixels per clock support resulting in
API changes in driver.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This patch adds copyright info to HLS generated mdd file
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This patch removes the unnecessary check in the lwip tcl
it is causing the compilation issues in few ethernetlite based designs.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
As in JTAG bootmode, watchdog is not initialized, avoided stopping of
watchdog in JTAG bootmode.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch use MB_Sleep API for microblaze design
and removed sleep.h inclusion in xsdps.h file.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
BUFFNA is not an error and hence the status bit is cleared by the
driver. But the error handler callback is called with a zero error
code in this case. Correct the same.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch use --create option for armcc compiler
instead of rc option.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch modifies standalone bsp tcl to generate 32bit/64bit
a53 bsp by keeping compiler check in the tcl to copy the
appropriate source file while generating standalone bsp
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the buswidth in dummy phase as
in data phase.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch added Tx/Rx flags in qspi message format
according to qspipsu driver changes.
Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
When building xilsecure with '-rR' as arguments to make causes this error:
Compiling Xilsecure Library
make[1]: *** No rule to make target 'xsecure_sha.o', needed by 'libxilsecure.a'. Stop.
Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs' failed
make: *** [psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs] Error 2
Fixing this by adding a pattern rules matching the required object files.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Bhavik Ameta <bameta@xilinx.com>
This patch fixes the issue AXI Ethernet with FIFO will fail to
create the BSP if the interrupt pin on the FIFO is unconnected.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch adds lwip support for the axi ethernet with fifo
combination on zynq.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch converts the three line comments to single line
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch adds common routines by removing the possible redundant
code from the functions.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This change is to reduce the size of the static bbt table size
from 8KB to 4KB because so far we have not identified the
flash part that has more than 16K blocks and also it will
reduce the bsp size.
Driver warns if the device has more number of blocks than the
defined value so that this can be incremented in future and if
there is a part available.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
As per the csurom, Bbt signature is always stored in oob area.
So, to sync with csurom, removing the NO_OOB(Bbt signature stores
in page area) functionality.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Controller supports only 8 bit mode. So, no need to configure
this value as this is the only option supported.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies openamp rpc_demo application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies openamp echo_test application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies openamp matrix_multiply application to
remove the hardcoded shared memory region and support for the
memory region configuration as per requirement of the code
in MPU region settings
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch adds vdma application to demonstrate how to use the VDMA triple buffer API.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch adds support for 64 bit vdma.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch updates the driver to support 64-bit addressing.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch updates the driver to support 64-bit addressing.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
UPPER_32_BITS(x) macro to handle shifts that may be >= the width of
the data type.
LOWER_32_BITS(x) macro to handle masking of 32-bit data types.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch adds various memory attribute definition
which can be used along with xil_settlbattributes API to
mark certain memory region with required attributes
such as cacheable or non-cacheable, inner/outer/non shareable
or executable or not etc.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch inclues memory attributes like device memory and
write through cacheable memory attributes to memory
attribute index register in boot.S
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
When building xilffs with '-rR' as arguments to make causes this error:
Compiling XilFFs Library
gmake[2]: *** No rule to make target 'ff.o', needed by 'libxilffs.a'. Stop.
Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilffs_v3_1/src/make.libs' failed
gmake[1]: *** [psu_cortexa53_0/libsrc/xilffs_v3_1/src/make.libs] Error 2
Fixing this by adding a pattern rules matching the required object files.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
-GpuPP now has its own PmSlave derived structure and the FSM
(new structure is added because there is no peripheral with
exactly the same behavior - Usbs have also their own power island,
but compared to them GpuPPs do not have wake-up capabilities
through GIC Proxy, and GpuPPs depend on FPD while LPD is
considered always-on)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Tested-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
The ROM handlers and hooks have a different signature.
Fixes: aea3444396c3 'ROM interface: Add ROM hook table'
Cc: Kristopher Bechamp <kristop@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
