Commit graph

693 commits

Author SHA1 Message Date
Kedareswara rao Appana
ec3aa65779 axiethernet: Add support for Hier IP
The axiethernet ip contains 3 inbuilt blocks init
--> Axi Ethernet MAC
--> Axi Etherent BUF
--> PCS/PMA Core

During the vivado version < 2015.2 the axiethernet ip
being exported to hdf in flat mode and the hsi opens this in flat mode.
But from 2015.3 build onwards the axiethernet ip is tagged as core in the vivado
and hsi will open the ip in hier IP mode(hierarchy) means for user only
top level axiethernet instance will be visible and it will contains all
the properties related to the sub-cores.

In order to allow backward compatabilty
---> If a xml/hdf file which got created with the vivado version < 2015.3 being exported to
the sdk >= 2015.3.
---> Two drivers will be active to resolve this issue.
---> axiethernet_v4_4 will be attached to BUF this will fix the backward compatabilty issue.
---> axiethernet_v5_0 will be attached to top level block for newer features.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
2015-06-20 13:08:14 +05:30
Sarat Chand Savitala
3b07202f16 sw_apps:zynqmp_fsbl: Added PL bitstream support
PL bitstream download support added.
Both secure and non-secure bitstreams are supported.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-06-20 13:08:13 +05:30
P L Sai Krishna
e0c1612b9e qspipsu: Removed NULL checks for Rx/Tx buffers.
This patch removes NULL pointer checks for Rx/Tx
buffers since writing/reading from 0x0 is permitted.
Used Tx/Rx flags to check for Writing/reading.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
2015-06-20 13:08:13 +05:30
Punnaiah Choudary Kalluri
d29f063136 nandpsu: Fix timeout error for erase operation on slower devices
The current timeout value is not enough for erase operation on slower
devices. so increasing the timeout value and also added usleep for
timeout routine to have a precise timeout.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2015-06-20 13:08:12 +05:30
Kedareswara rao Appana
29f2ea0237 lwip: Add lwip141_v1_2 and Deprecate lwip141_v1_1
This patch adds new version of the lwip and deprecates the older
version of the lwip.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
2015-06-20 13:08:11 +05:30
Kedareswara rao Appana
72d89bdf72 axiethernet: Add axiethernet_v5_0 and Deprecate axiethernet_v4_4
This patch Adds axiethernet_v5_0 and deprecates axiethernet_v4_4.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
2015-06-20 13:08:10 +05:30
Sarat Chand Savitala
a01d2a94ac sw_services:xilsecure: Fix to avoid clearing of AES key
Clearing the CSU_AES_KEY_CLEAR register to avoid clearing of AES key.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-06-19 17:57:08 +05:30
P L Sai Krishna
7fab5b8308 qspips: Support for Macronix part in g128 example.
This patch add support for Macronix 512Mb flash and
corrected the if condition logic, by replacing equal-to
operator with equality operator.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
2015-06-17 15:20:30 +05:30
Venkata Naga Sai Krishna Kolapalli
b07d492a65 Standalone BSP : Add Coresight DCC support in .mld
This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
2015-06-17 15:13:24 +05:30
Venkata Naga Sai Krishna Kolapalli
bc29600582 Coresight : Add support for Zynq Ultrascale+ MP.
This patch adds coresight DCC driver support for
Zynq Ultrascale+ MP platform.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
2015-06-17 15:13:24 +05:30
Venkata Naga Sai Krishna Kolapalli
372c9797d2 coresight : Add new version and deprecate old one.
This patch creates a new v1.1 of coresight driver and
deprecates older v1.0.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
2015-06-17 15:13:22 +05:30
P L Sai Krishna
32bcd2b1fc qspipsu: Modified if condition logic for ReadId API in examples.
This patch modifies the if condition logic for ReadId
function in examples by replacing equal-to operator
with equality.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
2015-06-17 15:02:55 +05:30
P L Sai Krishna
fdf41ec349 qspipsu: Modified Bus width during dummy phase in examples.
This patch modifies the Bus width value during dummy phase
in examples since it is recommended to be same as in
data phase.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
2015-06-17 15:02:53 +05:30
Kinjal Pravinbhai Patel
3459d888f6 bsp: r5: removes Init_Uart call from boot flow
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-06-17 14:50:51 +05:30
Kinjal Pravinbhai Patel
46c5e55478 bsp: a53: removes Init_Uart call from boot flow
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-06-17 14:50:51 +05:30
Kinjal Pravinbhai Patel
d0c41612d8 bsp: r5: enabling the asynchronous abort in boot code
This patch unmasks the A bit in CPSR to enable the
asynchronous abort in boot.S

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-06-17 14:50:50 +05:30
Kinjal Pravinbhai Patel
3f2478472f bsp: a53: enabling the SError exception in boot code
This patch enables Serror exception in boot flow for catching the
asynchronous aborts

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-06-17 14:50:50 +05:30
Kinjal Pravinbhai Patel
99a46157eb bsp: a53: added support for 64bit addressing mode
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-06-17 14:50:50 +05:30
Soren Brinkmann
c4df8f0dd2 PMUFW: lscript: Add section for ROM extension table
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2015-06-17 14:24:09 +05:30
Soren Brinkmann
d185a3a6d1 PMUFW: lscript: Sync memory definition with PMUFW repo
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2015-06-17 14:24:08 +05:30
Soren Brinkmann
368c173e5d PMUFW: lscript: Remove redundant blank lines
Sync with PMUFW sources.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2015-06-17 14:24:08 +05:30
Nava kishore Manne
146cd64c83 Doxygen changes for drivers 2015-06-12 12:50:09 +05:30
Venkata Naga Sai Krishna Kolapalli
6769624eed rtcpsu_v1_0 : Add new driver to RTC module.
This patch adds new driver for RTC component.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
2015-06-10 21:06:46 +05:30
Sarat Chand Savitala
fd800dfb46 sw_apps:zynqmp_fsbl: Removed redundant calls to Xil_DCacheFlush()
Xil_DCacheDisable() function internally has call to Xil_DCacheFlush().
Hence removing redundant calls to Xil_DCacheFlush from FSBL.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-06-10 20:36:58 +05:30
Sarat Chand Savitala
4766bcb9f6 sw_apps:zynqmp_fsbl: Registering exception handlers
Exception handlers are now registered unconditionally for both A53 and R5
Removed enabling of IRQ from FSBL(to be enabled in user application)

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-06-10 20:36:57 +05:30
Sarat Chand Savitala
83eaa550d6 sw_apps:zynqmp_fsbl: Updated release version to 2015.3
Updated release version from 2015.1 SW Beta2 to 2015.3

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
2015-06-10 20:36:56 +05:30
naga sureshkumar relli
d9923bc7bf xilflash_v4_1: Fix Write buffer programming for IntelStrataFlash
This patch fixes the writebufer programming for IntelStrataFlash.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
2015-06-10 20:36:54 +05:30
naga sureshkumar relli
3b8769e4f8 xilflash_v4_1: Fix warnings.
This patch fixes the warnings.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
2015-06-10 20:36:52 +05:30
naga sureshkumar relli
cc85685a73 xilflash_v4_1: Fix Spansion write buffer programming.
This patch fixes the spansion write buffer programming
issue.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
2015-06-10 20:36:51 +05:30
naga sureshkumar relli
6c21998270 xilflash_v4_0: deprecated version 4.0 and created new version 4.1
This patch deprecates the xilflash_v4_0 and
creates new version xilflash_v4_1.

Signed-off-by: naga sureshkumar relli <nagasure@xilinx.com>
2015-06-10 20:36:49 +05:30
Kinjal Pravinbhai Patel
7307299d94 bsp: a9: modified translation_table.s for DDR-less system
This patch modifies translation_table.S to put check whether
the DDR is present or not to fix the compilation error in
case of DDR-less system

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-06-10 20:18:18 +05:30
VNSL Durga
71f3adb973 Deinterlacer: Modified ip version in mdd file
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
2015-06-09 16:42:43 +05:30
Rohit Consul
3f2d727105 vprocss: Update to use subcore model parameters
Underlying subcores now use model parameters to get the static
configuration. Update the subsystem drivers to use this
information. Also user defined scaler cofficient table is moved
to application code

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:26:45 +05:30
Rohit Consul
d75c905bab v_vscaler: Update tcl to include model parameters
Updated tcl file to include model parameters. Also updated the
code to use new parameters instead of hard-coded values defined
earlier

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:26:43 +05:30
Rohit Consul
ebb231f6f7 v_vcresampler: Update tcl to include model parameters
Updated the tcl and mdd files to define model parameters. Updated
the code to use new parameters instead of hard-coded values
defined earlier

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:26:42 +05:30
Rohit Consul
68e90be08d v_letterbox: Update tcl to include model parameters
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:26:40 +05:30
Rohit Consul
965a8ffb21 v_hscaler: Update tcl to include model parameters
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:26:38 +05:30
Rohit Consul
10caed69b1 v_hcresampler: Update tcl to include model parameters
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:26:36 +05:30
Rohit Consul
de7b447b0e v_deinterlacer: Update tcl to include model parameters
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:26:35 +05:30
Rohit Consul
b35e6556b3 v_csc: Update tcl to include model parameters
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:26:33 +05:30
Rohit Consul
06de4b6538 vprocss: Added video processing subsystem driver
Video processing subsystem driver is added to the repo. This
driver currently is associated with a non-HIP version of the
IP. No makefile available. Hard-coded g.c file used, but not
included.

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:25:58 +05:30
Rohit Consul
a93e316656 v_letterbox: Added new driver
HLS generated driver along with manually written layer 2. Driver
tcl update is pending

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:25:57 +05:30
Rohit Consul
531499fd65 v_vcresampler: Added new driver
HLS generated driver along with manually written layer 2. Driver
tcl update is pending

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:25:56 +05:30
Rohit Consul
f37b5011ea v_hcresampler: Added new driver
HLS generated driver along with manually written layer 2. Driver
tcl update is pending

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:25:55 +05:30
Rohit Consul
1de32ec506 v_vscaler: Added new driver
HLS generated driver along with manually written layer 2. Driver
tcl update is pending

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:25:54 +05:30
Rohit Consul
53e26fcadc v_hscaler: Added new driver
HLS generated driver along with manually written layer 2. Driver
tcl update pending

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:25:53 +05:30
Rohit Consul
a88d54eb11 v_deinterlacer: Added new driver
HLS generated driver along with manually written layer 2. driver
tcl update pending

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:25:52 +05:30
Rohit Consul
c9796ae1ff v_csc: Driver for CSC core
HLS generated Layer 1 driver for csc core along with
manually written layer 2. Pending update of driver tcl

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
2015-06-09 16:25:51 +05:30
Kinjal Pravinbhai Patel
4baf4b5e6e bsp: a53: added src files for cortex-a53 32bit mode
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-06-08 12:07:35 +05:30
Kinjal Pravinbhai Patel
6b6e985817 bsp: r5: removed xmpu, slcr, xppu header files from cortexr5 folder
This patch removes xmpu, slcr, xppu header files from cortexr5 folder
and standalone tcl has been modified to copy the header files from
cortexa53/includes_ps. Makefile has been modified to include the
header files in include folder while compilation

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
2015-06-08 12:07:33 +05:30