The axiethernet ip contains 3 inbuilt blocks init
--> Axi Ethernet MAC
--> Axi Etherent BUF
--> PCS/PMA Core
During the vivado version < 2015.2 the axiethernet ip
being exported to hdf in flat mode and the hsi opens this in flat mode.
But from 2015.3 build onwards the axiethernet ip is tagged as core in the vivado
and hsi will open the ip in hier IP mode(hierarchy) means for user only
top level axiethernet instance will be visible and it will contains all
the properties related to the sub-cores.
In order to allow backward compatabilty
---> If a xml/hdf file which got created with the vivado version < 2015.3 being exported to
the sdk >= 2015.3.
---> Two drivers will be active to resolve this issue.
---> axiethernet_v4_4 will be attached to BUF this will fix the backward compatabilty issue.
---> axiethernet_v5_0 will be attached to top level block for newer features.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch removes NULL pointer checks for Rx/Tx
buffers since writing/reading from 0x0 is permitted.
Used Tx/Rx flags to check for Writing/reading.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
The current timeout value is not enough for erase operation on slower
devices. so increasing the timeout value and also added usleep for
timeout routine to have a precise timeout.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch add support for Macronix 512Mb flash and
corrected the if condition logic, by replacing equal-to
operator with equality operator.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies the if condition logic for ReadId
function in examples by replacing equal-to operator
with equality.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies the Bus width value during dummy phase
in examples since it is recommended to be same as in
data phase.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Xil_DCacheDisable() function internally has call to Xil_DCacheFlush().
Hence removing redundant calls to Xil_DCacheFlush from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Exception handlers are now registered unconditionally for both A53 and R5
Removed enabling of IRQ from FSBL(to be enabled in user application)
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch modifies translation_table.S to put check whether
the DDR is present or not to fix the compilation error in
case of DDR-less system
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Underlying subcores now use model parameters to get the static
configuration. Update the subsystem drivers to use this
information. Also user defined scaler cofficient table is moved
to application code
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated tcl file to include model parameters. Also updated the
code to use new parameters instead of hard-coded values defined
earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters. Updated
the code to use new parameters instead of hard-coded values
defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Updated the tcl and mdd files to define model parameters.
Updated the code to use new parameters instead of hard-coded
values defined earlier
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Video processing subsystem driver is added to the repo. This
driver currently is associated with a non-HIP version of the
IP. No makefile available. Hard-coded g.c file used, but not
included.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
HLS generated Layer 1 driver for csc core along with
manually written layer 2. Pending update of driver tcl
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
This patch removes xmpu, slcr, xppu header files from cortexr5 folder
and standalone tcl has been modified to copy the header files from
cortexa53/includes_ps. Makefile has been modified to include the
header files in include folder while compilation
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
