/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xaxicdma_example_sg_intr.c
*
* This file demonstrates how to use the xaxicdma driver on the Xilinx AXI
* CDMA core (AXICDMA) to transfer packets in scatter gather transfer mode
* through interrupt.
*
* This example assumes that the system has an interrupt controller.
*
* To see the debug print, you need a Uart16550 or uartlite in your system,
* and please set "-DDEBUG" in your compiler options for the example, also
* comment out the "#undef DEBUG" in xdebug.h. You need to rebuild your
* software executable.
*
* Make sure that MEMORY_BASE is defined properly as per the HW system.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 07/27/10 First release
* 2.01a rkv 01/28/11 Changed function prototype of XAxiCdma_SgIntrExample to
* a function taking arguments interrupt instance,device
* instance,device id,device interrupt id.
* Added interrupt support for Cortex A9
* 2.01a srt 03/05/12 Modified interrupt support for Zynq.
* Added V7 DDR Base Address to fix CR 649405.
* Modified Flushing and Invalidation of Caches to fix CRs
* 648103, 648701.
* 2.02a srt 03/01/13 Updated DDR base address for IPI designs (CR 703656).
* </pre>
*
****************************************************************************/
#include "xaxicdma.h"
#include "xdebug.h"
#include "xil_exception.h"
#include "xil_cache.h"
#include "xparameters.h"
#ifdef XPAR_INTC_0_DEVICE_ID
#include "xintc.h"
#else
#include "xscugic.h"
#endif
#ifndef __MICROBLAZE__
#include "xpseudo_asm_gcc.h"
#include "xreg_cortexa9.h"
#endif
#ifdef XPAR_UARTNS550_0_BASEADDR
#include "xuartns550_l.h" /* to use uartns550 */
#endif
#ifndef DEBUG
extern void xil_printf(const char *format, ...);
#endif
/******************** Constant Definitions **********************************/
/*
* Device hardware build related constants.
*/
#ifndef TESTAPP_GEN
#ifdef XPAR_INTC_0_DEVICE_ID
#define DMA_CTRL_DEVICE_ID XPAR_AXICDMA_0_DEVICE_ID
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#define DMA_CTRL_IRPT_INTR XPAR_INTC_0_AXICDMA_0_VEC_ID
#else
#define DMA_CTRL_DEVICE_ID XPAR_AXICDMA_0_DEVICE_ID
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define DMA_CTRL_IRPT_INTR XPAR_FABRIC_AXICDMA_0_VEC_ID
#endif
#endif
#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
#define MEMORY_BASE XPAR_V6DDR_0_S_AXI_BASEADDR
#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
#define MEMORY_BASE XPAR_S6DDR_0_S0_AXI_BASEADDR
#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
#define MEMORY_BASE XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
#elif XPAR_MIG7SERIES_0_BASEADDR
#define MEMORY_BASE XPAR_MIG7SERIES_0_BASEADDR
#else
#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
DEFAULT SET TO 0x01000000
#define MEMORY_BASE 0x01000000
#endif
#define BD_SPACE_BASE (MEMORY_BASE + 0x03000000)
#define BD_SPACE_HIGH (MEMORY_BASE + 0x03001FFF)
#define TX_BUFFER_BASE (MEMORY_BASE + 0x00630000)
#define RX_BUFFER_BASE (MEMORY_BASE + 0x00660000)
#define RX_BUFFER_HIGH (MEMORY_BASE + 0x0068FFFF)
#define MAX_PKT_LEN 1024
/* Number of BDs in the transfer example
* We show how to submit multiple BDs for one transmit.
* The receive side gets one completion per transfer
*/
#define NUMBER_OF_BDS_TO_TRANSFER 30
/* The interrupt coalescing threshold and delay timer threshold
* Valid range is 1 to 255 for coalescing and 0 to 255 for delay timer
*/
#define COALESCING_COUNT 5
#define DELAY_COUNT 5
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#if defined(XPAR_UARTNS550_0_BASEADDR)
static void Uart550_Setup(void);
#endif
static void Example_CallBack(void *CallBackRef, u32 IrqMask, int *NumBdPtr);
static int SetupTransfer(XAxiCdma * InstancePtr);
static int DoTransfer(XAxiCdma * InstancePtr);
static int CheckData(u8 *SrcPtr, u8 *DestPtr, int Length);
#ifdef XPAR_INTC_0_DEVICE_ID
static int SetupIntrSystem(XIntc *IntcInstancePtr, XAxiCdma *InstancePtr,
u32 IntrId);
static void DisableIntrSystem(XIntc *IntcInstancePtr, u32 IntrId);
int XAxiCdma_SgIntrExample(XIntc *IntcInstancePtr, XAxiCdma *InstancePtr,
u16 DeviceId,u32 IntrId);
#else
static int SetupIntrSystem(XScuGic *IntcInstancePtr, XAxiCdma *InstancePtr,
u32 IntrId);
static void DisableIntrSystem(XScuGic *IntcInstancePtr, u32 IntrId);
int XAxiCdma_SgIntrExample(XScuGic *IntcInstancePtr, XAxiCdma *InstancePtr,
u16 DeviceId,u32 IntrId);
#endif
/************************** Variable Definitions *****************************/
#ifndef TESTAPP_GEN
static XAxiCdma Engine; /* Instance of the XAxiCdma */
#ifdef XPAR_INTC_0_DEVICE_ID
static XIntc IntcController; /* Instance of the Interrupt Controller */
#else
static XScuGic IntcController; /* Instance of the Interrupt Controller */
#endif
#endif
/* Transmit buffer for DMA transfer.
*/
static u32 *TransmitBufferPtr = (u32 *) TX_BUFFER_BASE;
static u32 *ReceiveBufferPtr = (u32 *) RX_BUFFER_BASE;
/* Shared variables used to test the callbacks.
*/
volatile static int Done = 0; /* Dma transfer is done */
volatile static int Error = 0; /* Dma Bus Error occurs */
/*****************************************************************************/
/*
* The entry point for this example. It sets up uart16550 if one is available,
* invokes the example function, and reports the execution status.
*
* @param None.
*
* @return
* - XST_SUCCESS if example finishes successfully
* - XST_FAILURE if example fails.
*
* @note None.
*
******************************************************************************/
#ifndef TESTAPP_GEN
int main()
{
int Status;
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
/* Run the interrupt example for simple transfer
*/
Status = XAxiCdma_SgIntrExample(&IntcController, &Engine,
DMA_CTRL_DEVICE_ID, DMA_CTRL_IRPT_INTR);
if (Status != XST_SUCCESS) {
xil_printf("XAxiCdma_SgIntrExample: Failed\r\n");
return XST_FAILURE;
}
xil_printf("XAxiCdma_SgIntrExample: Passed\r\n");
xil_printf("--- Exiting main() --- \r\n");
return 0;
}
#endif
#ifdef XPAR_UARTNS550_0_BASEADDR
/*****************************************************************************/
/*
* This function setup the baudrate to 9600 and data bits to 8 in Uart16550
*
* @param None
*
* @return None
*
* @note None.
*
******************************************************************************/
static void Uart550_Setup(void)
{
XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
XPAR_XUARTNS550_CLOCK_HZ, 9600);
XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
XUN_LCR_8_DATA_BITS);
}
#endif
/*****************************************************************************/
/*
* Callback function for the scatter gather transfer.
* It is called by the driver's interrupt handler.
*
* @param CallBackRef is the reference pointer registered through
* transfer submission. In this case, it is the pointer to the
* driver instance
* @param IrqMask is the interrupt mask the driver interrupt handler
* passes to the callback function.
* @param NumBdPtr is the pointer to number of BDs this handler handles
*
* @return None
*
* @note None.
*
******************************************************************************/
static void Example_CallBack(void *CallBackRef, u32 IrqMask, int *NumBdPtr)
{
XAxiCdma *InstancePtr;
int BdCount;
XAxiCdma_Bd *BdPtr;
int Status;
int Tmp;
InstancePtr = (XAxiCdma *)CallBackRef;
Tmp = *NumBdPtr;
/* If error interrupt happened, the driver interrupt handler
* has already reset the hardware
*/
if (IrqMask & XAXICDMA_XR_IRQ_ERROR_MASK) {
Error = 1;
}
if (IrqMask & XAXICDMA_XR_IRQ_IOC_MASK) {
/* Get all processed BDs from hardware
*/
BdCount = XAxiCdma_BdRingFromHw(InstancePtr, Tmp, &BdPtr);
/* Release finished BDs
*
* It is ok if BdCount is zero as a previous callback may
* have ripen all finished BDs
*/
if(BdCount > 0) {
Status = XAxiCdma_BdRingFree(InstancePtr,
BdCount, BdPtr);
if(Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Error free BD %x\r\n", Status);
Error = 1;
return;
}
Done += BdCount;
*NumBdPtr = Tmp - BdCount;
}
}
return;
}
/******************************************************************************/
/*
* Setup the interrupt system, including:
* - Initialize the interrupt controller,
* - Register the XAxiCdma interrupt handler to the interrupt controller
* - Enable interrupt
*
* @param IntcInstancePtr is a pointer to the instance of the INTC
* @param InstancePtr is a pointer to the instance of the XAxiCdma
* @param IntrId is the interrupt Id for XAxiCdma
*
* @return
* - XST_SUCCESS if interrupt system setup successfully
* - XST_FAILURE if error occurs
*
* @note None.
*
*******************************************************************************/
#ifdef XPAR_INTC_0_DEVICE_ID
static int SetupIntrSystem(XIntc *IntcInstancePtr, XAxiCdma *InstancePtr,
u32 IntrId)
{
int Status;
#ifndef TESTAPP_GEN
/*
* Initialize the interrupt controller driver
*/
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Interrupt controller intialization failed %d\r\n",Status);
return XST_FAILURE;
}
#endif
/*
* Connect the driver interrupt handler to intc.
* It will call the example callback upon transfer completion
*/
Status = XIntc_Connect(IntcInstancePtr, IntrId,
(XInterruptHandler)XAxiCdma_IntrHandler, (void *)InstancePtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Interrupt handler registration failed %d\r\n", Status);
return XST_FAILURE;
}
#ifndef TESTAPP_GEN
/*
* Start the interrupt controller such that interrupts are enabled for
* all devices that cause interrupts. Specify real mode so that the DMA
* engine can generate interrupts through the interrupt controller
*/
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
/*
* Enable the interrupt for the DMA engine
*/
XIntc_Enable(IntcInstancePtr, IntrId);
#ifndef TESTAPP_GEN
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_InterruptHandler,
(void *)IntcInstancePtr);
Xil_ExceptionEnable();
#endif /* TESTAPP_GEN */
return XST_SUCCESS;
}
#else
static int SetupIntrSystem(XScuGic *IntcInstancePtr, XAxiCdma *InstancePtr,
u32 IntrId)
{
int Status;
#ifndef TESTAPP_GEN
/*
* Initialize the interrupt controller driver
*/
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
XScuGic_SetPriorityTriggerType(IntcInstancePtr, IntrId, 0xA0, 0x3);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, IntrId,
(Xil_InterruptHandler)XAxiCdma_IntrHandler,
InstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the DMA device.
*/
XScuGic_Enable(IntcInstancePtr, IntrId);
#ifndef TESTAPP_GEN
Xil_ExceptionInit();
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
IntcInstancePtr);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnable();
#endif /* TESTAPP_GEN */
return XST_SUCCESS;
}
#endif
/*****************************************************************************/
/*
*
* This function disables the interrupt for the XAxiCdma device
*
* @param IntcInstancePtr is the pointer to the instance of the INTC
* @param IntrId is the interrupt Id for the XAxiCdma instance
*
* @return None.
*
* @note None.
*
******************************************************************************/
#ifdef XPAR_INTC_0_DEVICE_ID
static void DisableIntrSystem(XIntc *IntcInstancePtr, u32 IntrId)
{
/* Disconnect the interrupt
*/
XIntc_Disconnect(IntcInstancePtr, IntrId);
}
#else
static void DisableIntrSystem(XScuGic *IntcInstancePtr, u32 IntrId)
{
/* Disconnect the interrupt
*/
XScuGic_Disable(IntcInstancePtr, IntrId);
XScuGic_Disconnect(IntcInstancePtr, IntrId);
}
#endif
/*****************************************************************************/
/**
*
* This function sets up the DMA engine to be ready for scatter gather transfer
*
* @param InstancePtr is the pointer to the instance of the DMA engine.
*
* @return
* - XST_SUCCESS if the setup is successful
* - XST_FAILURE if following error occurs:
* BD buffer address is not aligned
* BD ring creation failed
* BD ring clone failed
* Set coalescing failed
*
* @note None.
*
******************************************************************************/
static int SetupTransfer(XAxiCdma * InstancePtr)
{
int Status;
XAxiCdma_Bd BdTemplate;
int BdCount;
u8 *SrcBufferPtr;
int Index;
/* Disable all interrupts
*/
XAxiCdma_IntrDisable(InstancePtr, XAXICDMA_XR_IRQ_ALL_MASK);
/* Setup BD ring */
BdCount = XAxiCdma_BdRingCntCalc(XAXICDMA_BD_MINIMUM_ALIGNMENT,
BD_SPACE_HIGH - BD_SPACE_BASE + 1,
(u32)BD_SPACE_BASE);
if (BdCount < 1) {
xdbg_printf(XDBG_DEBUG_ERROR, "Invalid buffer %x\r\n",
(unsigned int)BD_SPACE_BASE);
return XST_FAILURE;
}
Status = XAxiCdma_BdRingCreate(InstancePtr, BD_SPACE_BASE,
BD_SPACE_BASE, XAXICDMA_BD_MINIMUM_ALIGNMENT, BdCount);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Create BD ring failed %d\r\n",
Status);
return XST_FAILURE;
}
/*
* Setup a BD template to copy to every BD.
*/
XAxiCdma_BdClear(&BdTemplate);
Status = XAxiCdma_BdRingClone(InstancePtr, &BdTemplate);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Clone BD ring failed %d\r\n",
Status);
return XST_FAILURE;
}
/* Initialize receive buffer to 0's and transmit buffer with pattern
*/
memset((void *)ReceiveBufferPtr, 0,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
SrcBufferPtr = (u8 *)TransmitBufferPtr;
for(Index = 0; Index < MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER;
Index++) {
SrcBufferPtr[Index] = Index & 0xFF;
}
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TransmitBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
Status = XAxiCdma_SetCoalesce(InstancePtr, COALESCING_COUNT,
DELAY_COUNT);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Set coalescing failed %d\r\n", Status);
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/*
*
* This function non-blockingly transmits all packets through the DMA engine.
*
* @param InstancePtr points to the DMA engine instance
*
* @return
* - XST_SUCCESS if the DMA accepts all the packets successfully,
* - XST_FAILURE if following error occurs
* BD ring allocation failed
* One of the buffer transfer length is invalid
* Submission to hardware failed
*
* @note None.
*
******************************************************************************/
static int DoTransfer(XAxiCdma * InstancePtr)
{
XAxiCdma_Bd *BdPtr;
XAxiCdma_Bd *BdCurPtr;
int Status;
int Index;
u32 SrcBufferAddr;
u32 DstBufferAddr;
static int Counter = 0;
Status = XAxiCdma_BdRingAlloc(InstancePtr,
NUMBER_OF_BDS_TO_TRANSFER, &BdPtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Failed bd alloc\r\n");
return XST_FAILURE;
}
SrcBufferAddr = (u32)TransmitBufferPtr;
DstBufferAddr = (u32)ReceiveBufferPtr;
BdCurPtr = BdPtr;
/* Set up the BDs
*/
for(Index = 0; Index< NUMBER_OF_BDS_TO_TRANSFER; Index++) {
Counter += 1;
Status = XAxiCdma_BdSetSrcBufAddr(BdCurPtr, SrcBufferAddr);
if(Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Set src addr failed %d, %x/%x\r\n",
Status, (unsigned int)BdCurPtr,
(unsigned int)SrcBufferAddr);
return XST_FAILURE;
}
Status = XAxiCdma_BdSetDstBufAddr(BdCurPtr, DstBufferAddr);
if(Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Set dst addr failed %d, %x/%x\r\n",
Status, (unsigned int)BdCurPtr,
(unsigned int)DstBufferAddr);
return XST_FAILURE;
}
Status = XAxiCdma_BdSetLength(BdCurPtr, MAX_PKT_LEN);
if(Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Set BD length failed %d\r\n", Status);
return XST_FAILURE;
}
SrcBufferAddr += MAX_PKT_LEN;
DstBufferAddr += MAX_PKT_LEN;
BdCurPtr = XAxiCdma_BdRingNext(InstancePtr, BdCurPtr);
}
/* Give the BDs to hardware */
Status = XAxiCdma_BdRingToHw(InstancePtr,
NUMBER_OF_BDS_TO_TRANSFER, BdPtr, Example_CallBack,
(void *)InstancePtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Failed to hw %d\r\n", Status);
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/*
* This function checks that two buffers have the same data
*
* @param SrcPtr is the source buffer
* @param DestPtr is the destination buffer
* @param Length is the length of the buffer to check
*
* @return
* - XST_SUCCESS if the two buffer matches
* - XST_FAILURE otherwise
*
* @note None.
*
******************************************************************************/
static int CheckData(u8 *SrcPtr, u8 *DestPtr, int Length)
{
int Index;
/* Invalidate the DestBuffer before receiving the data, in case the
* Data Cache is enabled
*/
Xil_DCacheInvalidateRange((u32)DestPtr, Length);
for (Index = 0; Index < Length; Index++) {
if ( DestPtr[Index] != SrcPtr[Index]) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Data check failure %d: %x/%x\r\n",
Index, (unsigned int)DestPtr[i],
(unsigned int)SrcPtr[i]);
return XST_FAILURE;
}
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* The example to do the scatter gather transfer through interrupt.
*
* @param IntcInstancePtr is a pointer to the INTC instance
* @param InstancePtr is a pointer to the XAxiCdma instance
* @param DeviceId is the Device Id of the XAxiCdma instance
* @param IntrId is the interrupt Id for the XAxiCdma instance in build
*
* @return
* - XST_SUCCESS if example finishes successfully
* - XST_FAILURE if error occurs during transfer setup or transfer
* has errors
*
* @note If the hardware build has problems with interrupt,
* then this function hangs
*
******************************************************************************/
#ifdef XPAR_INTC_0_DEVICE_ID
int XAxiCdma_SgIntrExample(XIntc *IntcInstancePtr, XAxiCdma *InstancePtr,
u16 DeviceId,u32 IntrId)
#else
int XAxiCdma_SgIntrExample(XScuGic *IntcInstancePtr, XAxiCdma *InstancePtr,
u16 DeviceId,u32 IntrId)
#endif
{
XAxiCdma_Config *CfgPtr;
int Status;
u8 *SrcPtr;
u8 *DstPtr;
SrcPtr = (u8 *)TransmitBufferPtr;
DstPtr = (u8 *)ReceiveBufferPtr;
/* Initialize the XAxiCdma device.
*/
CfgPtr = XAxiCdma_LookupConfig(DeviceId);
if (!CfgPtr) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Cannot find config structure for device %d\r\n",
XPAR_AXICDMA_0_DEVICE_ID);
return XST_FAILURE;
}
Status = XAxiCdma_CfgInitialize(InstancePtr, CfgPtr,
CfgPtr->BaseAddress);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Initialization failed with %d\r\n", Status);
return XST_FAILURE;
}
/* Setup the BD ring
*/
Status = SetupTransfer(InstancePtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Setup BD ring failed with %d\r\n", Status);
return XST_FAILURE;
}
/* Setup the interrupt system
*/
Status = SetupIntrSystem(IntcInstancePtr, InstancePtr, IntrId);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Setup Intr system failed with %d\r\n", Status);
return XST_FAILURE;
}
/* Enable completion and error interrupts
*/
XAxiCdma_IntrEnable(InstancePtr, XAXICDMA_XR_IRQ_ALL_MASK);
/* Start the DMA transfer
*/
Status = DoTransfer(InstancePtr);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR,
"Do transfer failed with %d\r\n", Status);
return XST_FAILURE;
}
/* Wait until the DMA transfer is done
*/
while ((Done < NUMBER_OF_BDS_TO_TRANSFER) && !Error) {
/* Wait */
}
if(Error) {
xdbg_printf(XDBG_DEBUG_ERROR, "Transfer has error %x\r\n",
(unsigned int)XAxiCdma_GetError(InstancePtr));
DisableIntrSystem(IntcInstancePtr, IntrId);
return XST_FAILURE;
}
/* Transfer completes successfully, check data
*/
Status = CheckData(SrcPtr, DstPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
if (Status != XST_SUCCESS) {
xdbg_printf(XDBG_DEBUG_ERROR, "Check data failed for sg "
"transfer\r\n");
DisableIntrSystem(IntcInstancePtr, IntrId);
return XST_FAILURE;
}
/* Test finishes successfully, clean up and return
*/
DisableIntrSystem(IntcInstancePtr, IntrId);
return XST_SUCCESS;
}