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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<ul>
<li>XWdtTb_ReadReg
: <a class="el" href="xwdttb__l_8h.html#6f2e49719af7dcf1bf6f4205e1fa2705">xwdttb_l.h</a><li>XWdtTb_WriteReg
: <a class="el" href="xwdttb__l_8h.html#4fc2b4ddd68876097caa8d8b57d71686">xwdttb_l.h</a><li>XWT_CSR0_EWDT1_MASK
: <a class="el" href="xwdttb__l_8h.html#de5e43c4abe7050348a79d40a66b8ed5">xwdttb_l.h</a><li>XWT_CSR0_WDS_MASK
: <a class="el" href="xwdttb__l_8h.html#77f7707fc376bc4d78bcbfcd5725d1b4">xwdttb_l.h</a><li>XWT_CSR0_WRS_MASK
: <a class="el" href="xwdttb__l_8h.html#81387426fea67f24dc512c7e0958bb41">xwdttb_l.h</a><li>XWT_CSRX_EWDT2_MASK
: <a class="el" href="xwdttb__l_8h.html#a8ba0ab70db58a951844c764dfe7f66b">xwdttb_l.h</a><li>XWT_TBR_OFFSET
: <a class="el" href="xwdttb__l_8h.html#2dc23d0eb5f6972f2c23b5f537e99200">xwdttb_l.h</a><li>XWT_TWCSR0_OFFSET
: <a class="el" href="xwdttb__l_8h.html#97655d116629a7fb87dd637323994115">xwdttb_l.h</a><li>XWT_TWCSR1_OFFSET
: <a class="el" href="xwdttb__l_8h.html#6486b65eba30183f000524ca5e72f7fd">xwdttb_l.h</a></ul>
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