;/******************************************************************************
;*
;* Copyright (C) 2012 - 2014 Xilinx, Inc.  All rights reserved.
;* 
;* Permission is hereby granted, free of charge, to any person obtaining a copy
;* of this software and associated documentation files (the "Software"), to deal 
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;* copies of the Software, and to permit persons to whom the Software is 
;* furnished to do so, subject to the following conditions:
;*
;* The above copyright notice and this permission notice shall be included in 
;* all copies or substantial portions of the Software.
;*
;* Use of the Software is limited solely to applications: 
;* (a) running on a Xilinx device, or 
;* (b) that interact with a Xilinx device through a bus or interconnect.  
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;* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
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;*
;******************************************************************************/

LOAD_OCM_1 0x00000000 0x00030000
{
    VECTORS +0
    {
    	* (.vectors, +FIRST)
     	* (InRoot$$Sections)
    }
    
    RO_CODE +0
    {
        * (+RO)    
    }
    RW_DATA +0
    {
        * (+RW)
    }
    
    RSA_AC +0 ALIGN 0x40 EMPTY 0x1000 {}
    
    ZI_DATA +0
    {
        * (+ZI)
    }
	
	ARM_LIB_HEAP  +0 ALIGN 0x10 EMPTY 0x2000 {}	
}

LOAD_OCM_2 0xFFFF0000 0x0000FE00
{
    ARM_LIB_STACK +0 ALIGN 0x10 EMPTY 0x4000 {}
    IRQ_STACK     +0 ALIGN 0x10 EMPTY 0x6000 {}
    SPV_STACK     +0 ALIGN 0x10 EMPTY 2048 {}
    ABORT_STACK   +0 ALIGN 0x10 EMPTY 1024 {}
}