xcsudma.h File Reference

Overview

CSU_DMA allows the CSU to move data efficiently between the memory (32 bit AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure Stream Switch (SSS).

The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC (read) channel and DST (write) channel. The DMA is effectively able to transfer data:

• From PS-side to the SSS-side (SRC DMA only)
• From SSS-side to the PS-side (DST DMA only)
• Simultaneous PS-side to SSS_side and SSS-side to the PS-side

Initialization & Configuration

The device driver enables higher layer software (e.g., an application) to communicate to the CSU_DMA core.

XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core. The user needs to first call the XCsuDma_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XCsuDma_CfgInitialize() API.

Interrupts This driver will not support handling of interrupts user should write handler to handle the interrupts.

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The XCsuDma driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

Data Structures
struct	XCsuDma_Config
struct	XCsuDma
struct	XCsuDma_Configure

Macros
#define	XCsuDma_Reset()
#define	XCsuDma_WaitForDone(InstancePtr, Channel)
#define	XCsuDma_GetDoneCount(InstancePtr, Channel)
#define	XCsuDma_GetFIFOLevel(InstancePtr, Channel)
#define	XCsuDma_GetWROutstandCount(InstancePtr, Channel)
#define	XCsuDma_IsBusy(InstancePtr, Channel)
Ranges of Size

Functions
XCsuDma_Config *	XCsuDma_LookupConfig (u16 DeviceId)
s32	XCsuDma_CfgInitialize (XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, u32 EffectiveAddr)
void	XCsuDma_Transfer (XCsuDma *InstancePtr, XCsuDma_Channel Channel, UINTPTR Addr, u32 Size, u8 EnDataLast)
u64	XCsuDma_GetAddr (XCsuDma *InstancePtr, XCsuDma_Channel Channel)
u32	XCsuDma_GetSize (XCsuDma *InstancePtr, XCsuDma_Channel Channel)
void	XCsuDma_Pause (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_PauseType Type)
s32	XCsuDma_IsPaused (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_PauseType Type)
void	XCsuDma_Resume (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_PauseType Type)
u32	XCsuDma_GetCheckSum (XCsuDma *InstancePtr)
void	XCsuDma_ClearCheckSum (XCsuDma *InstancePtr)
void	XCsuDma_SetConfig (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_Configure *ConfigurValues)
void	XCsuDma_GetConfig (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_Configure *ConfigurValues)
u32	XCsuDma_IntrGetStatus (XCsuDma *InstancePtr, XCsuDma_Channel Channel)
void	XCsuDma_IntrClear (XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
void	XCsuDma_EnableIntr (XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
void	XCsuDma_DisableIntr (XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
u32	XCsuDma_GetIntrMask (XCsuDma *InstancePtr, XCsuDma_Channel Channel)
s32	XCsuDma_SelfTest (XCsuDma *InstancePtr)