- add the first steps to support the (local and IO) APIC
- remove some typos in the comments git-svn-id: http://svn.lfbs.rwth-aachen.de/svn/scc/trunk/MetalSVM@196 315a16e6-25f9-4109-90ae-ca3045a26c18
This commit is contained in:
stefan
parent
01ff479e11
commit
08cbc0a257
7 changed files with 195 additions and 45 deletions
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@ -22,6 +22,7 @@
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#include <metalsvm/stddef.h>
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#include <asm/gdt.h>
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#include <asm/apic.h>
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#ifdef CONFIG_PCI
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#include <asm/pci.h>
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#endif
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@ -65,6 +66,20 @@ inline static void rmb(void) { asm volatile("lfence" ::: "memory"); }
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inline static void wmb(void) { asm volatile("sfence" ::: "memory"); }
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#endif
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inline static uint32_t cpuid(uint32_t code, uint32_t* feature) {
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uint32_t ret;
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asm volatile("cpuid" : "=a"(ret), "=d"(*feature) : "0"(code));
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return ret;
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}
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inline static uint64_t rdmsr(uint32_t msr) {
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uint32_t low, high;
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asm volatile ("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
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return ((uint64_t)high << 32) | low;
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}
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#define NOP1 asm volatile ("nop")
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#define NOP2 asm volatile ("nop;nop")
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#define NOP4 asm volatile ("nop;nop;nop;nop")
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@ -76,6 +91,7 @@ inline static int system_init(void)
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scc_init();
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#endif
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gdt_install();
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apic_init();
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#ifdef CONFIG_PCI
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pci_init();
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#endif
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@ -1,4 +1,4 @@
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C_source = scc.c gdt.c kb.c timer.c irq.c isrs.c idt.c vga.c multiboot.c pci.c
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C_source = scc.c gdt.c kb.c timer.c irq.c isrs.c idt.c vga.c multiboot.c apic.c pci.c
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ASM_source = entry.asm string.asm
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OBJS += $(patsubst %.c, %.o, $(filter %.c, $(C_source)))
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147
arch/x86/kernel/apic.c
Normal file
147
arch/x86/kernel/apic.c
Normal file
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@ -0,0 +1,147 @@
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/*
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* Copyright 2010 Stefan Lankes, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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#include <metalsvm/stddef.h>
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#include <metalsvm/stdio.h>
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#include <metalsvm/string.h>
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#include <metalsvm/errno.h>
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#include <metalsvm/processor.h>
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#include <asm/apic.h>
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#include <asm/multiboot.h>
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#define LAPIC_VERSION 0x0030
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#define LAPIC_SVR 0x00F0
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// 8259 controllers' I/O ports
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#define MAST_8259_APORT 0x20
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#define MAST_8259_DPORT 0x21
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#define SLAV_8259_APORT 0xA0
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#define SLAV_8259_DPORT 0xA1
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static apic_mp_t* apic_mp = NULL;
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static apic_config_table_t* apic_config = NULL;
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static uint32_t ncores = 1;
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int apic_init(void)
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{
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size_t addr;
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uint32_t i, count;
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// searching MP signature in the reserved memory areas
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#ifdef CONFIG_MULTIBOOT
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if (mb_info && (mb_info->flags & (1 << 6))) {
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multiboot_memory_map_t* mmap = (multiboot_memory_map_t*) mb_info->mmap_addr;
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multiboot_memory_map_t* mmap_end = (void*) ((size_t) mb_info->mmap_addr + mb_info->mmap_length);
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while (mmap < mmap_end) {
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if (mmap->type == MULTIBOOT_MEMORY_RESERVED) {
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addr = mmap->addr;
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for(i=0; i<mmap->len; i++, addr++) {
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if (strncmp((void*)addr, "_MP_", 4) == 0) {
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apic_mp = (apic_mp_t*) addr;
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goto found_mp;
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}
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}
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}
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mmap++;
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}
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}
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#endif
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found_mp:
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if (!apic_mp)
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goto out;
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kprintf("System uses Multiprocessing Specification 1.%d\n", apic_mp->version);
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kprintf("MP features 1: %d\n", apic_mp->features[0]);
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if (apic_mp->features[0]) {
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kputs("Currently, MetalSVM supports only multiprocessing via the MP config tables!\n");
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goto out;
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}
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apic_config = (apic_config_table_t*) apic_mp->mp_config;
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if (!apic_config || strncmp((void*) &apic_config->signature, "PCMP", 4) !=0) {
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kputs("Invalid MP config table\n");
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goto out;
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}
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addr = (size_t) apic_config;
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addr += sizeof(apic_config_table_t);
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if (addr % 4)
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addr += 4 - addr % 4;
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for(i=0, count=0; i<apic_config->entry_count; i++) {
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if (*((uint8_t*) addr) == 0) {
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count++;
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addr += 20;
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} else addr += 8;
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}
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kprintf("Found %d cores\n", count);
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if (count > MAX_CORES) {
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kputs("Found too many cores! Increase the macro MAX_CORES!\n");
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goto out;
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}
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ncores = count;
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addr = apic_config->lapic;
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i = *((uint32_t*) (addr+LAPIC_VERSION));
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kprintf("Found LAPIC at 0x%x\n", addr);
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kprintf("Maximum LVT Entry: 0x%x\n", (i >> 16) & 0xFF);
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kprintf("LAPIC Version: 0x%x\n", i & 0xFF);
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#if 0
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cpuid(0x1, &i);
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if (!(i & (1 << 5))) {
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kputs("Unable to use Machine-Specific Registers (MSR)\n");
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goto out;
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}
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if (!(rdmsr(0x1B) & (1 << 11))) {
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kputs("Unable to use APIC Global Enable flag!\n");
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goto out;
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}
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i = *((uint32_t*) (addr+LAPIC_SVR));
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kprintf("Supurious Interrupt Vector Register: %x\n", i);
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i = i | (1 << 8);
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*((uint32_t*) (addr+LAPIC_SVR)) = i;
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// Disable the 8259's because we are going to use the IOAPIC for interrupt processing
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outportb(MAST_8259_DPORT, 0xFF); // OCW1 master: inhibit all interrupts
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udelay(100);
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outportb(SLAV_8259_DPORT, 0xFF); // OCW1 slave: inhibit all interrupts
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return 0;
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#endif
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out:
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apic_mp = NULL;
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apic_config = NULL;
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ncores = 1;
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return -EINVAL;
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}
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int has_apic(void)
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{
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return (apic_mp != NULL);
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}
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@ -24,7 +24,7 @@
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#include <asm/isrs.h>
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/*
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* These are own ISRs that point to our special IRQ handler
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* These are our own ISRs that point to our special IRQ handler
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* instead of the regular 'fault_handler' function
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*/
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extern void irq0(void);
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@ -66,8 +66,8 @@ void irq_uninstall_handler(unsigned int irq)
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* Normally, IRQs 0 to 7 are mapped to entries 8 to 15. This
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* is a problem in protected mode, because IDT entry 8 is a
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* Double Fault! Without remapping, every time IRQ0 fires,
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* you get a Double Fault Exception, which is NOT actually
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* what's happening. We send commands to the Programmable
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* you get a Double Fault Exception, which is NOT what's
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* actually happening. We send commands to the Programmable
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* Interrupt Controller (PICs - also called the 8259's) in
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* order to make IRQ0 to 15 be remapped to IDT entries 32 to
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* 47
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@ -140,8 +140,8 @@ void irq_init(void)
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* the 'fault_handler' in 'isrs.c'. The IRQ Controllers need
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* to be told when you are done servicing them, so you need
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* to send them an "End of Interrupt" command (0x20). There
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* are two 8259 chips: The first exists at 0x20, the second
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* exists at 0xA0. If the second controller (an IRQ from 8 to
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* are two 8259 chips: The first one exists at 0x20, the second
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* one exists at 0xA0. If the second controller (an IRQ from 8 to
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* 15) gets an interrupt, you need to acknowledge the
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* interrupt at BOTH controllers, otherwise, you only send
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* an EOI command to the first controller. If you don't send
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/*
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* Find out if we have a custom handler to run for this
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* IRQ, and then finally, run it
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* IRQ and then finally, run it
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*/
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handler = irq_routines[s->int_no - 32];
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if (handler) {
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@ -27,7 +27,7 @@
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/*
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* These are function prototypes for all of the exception
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* handlers: The first 32 entries in the IDT are reserved
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* by Intel, and are designed to service exceptions!
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* by Intel and are designed to service exceptions!
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*/
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extern void isr0(void);
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extern void isr1(void);
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/*
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* This is a simple string array. It contains the message that
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* corresponds to each and every exception. We get the correct
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* message by accessing like:
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* message by accessing it like this:
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* exception_message[interrupt_number]
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*/
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static const char *exception_messages[] = {
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@ -160,7 +160,7 @@ static const char *exception_messages[] = {
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/*
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* All of our Exception handling Interrupt Service Routines will
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* point to this function. This will tell us what exception has
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* happened! Right now, we simply abort the current task.
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* occured! Right now, we simply abort the current task.
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* All ISRs disable interrupts while they are being
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* serviced as a 'locking' mechanism to prevent an IRQ from
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* happening and messing up kernel data structures
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@ -31,12 +31,12 @@ extern current_task
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; ...
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; } task_t;
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; After an interrupt, the original return address has to push on the stack
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; because we want to comeback...
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; After an interrupt, the original return address has to be pushed
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; on the stack because we want to comeback...
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global schedule_entry
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schedule_entry:
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cli
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sub esp, 4 ; add some space for the retunr address,
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sub esp, 4 ; add some space for the return address,
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; which is stored in current_task->ip
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pushfd
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@ -64,7 +64,7 @@ schedule_entry:
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jmp L1
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; Scheduler, which switchs to the new tasks
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; Scheduler, which switches to the new tasks
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global schedule
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schedule:
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ret
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@ -22,6 +22,7 @@
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#include <metalsvm/tasks.h>
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#include <metalsvm/time.h>
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#include <metalsvm/processor.h>
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#include <asm/apic.h>
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#include <asm/irq.h>
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#include <asm/irqflags.h>
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#include <asm/gdt.h>
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@ -29,11 +30,10 @@
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#include <asm/vga.h>
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/*
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* This will keep track of how many ticks that the system
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* This will keep track of how many ticks the system
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* has been running for
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*/
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static volatile uint64_t timer_ticks = 0;
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static unsigned int curr_timer_freq = 18;
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/*
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* Handles the timer. In this case, it's very simple: We
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@ -66,44 +66,31 @@ void timer_wait(unsigned int ticks)
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reschedule();
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}
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#define LATCH(f) ((CLOCK_TICK_RATE + f/2) / f)
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/*
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* Sets up the system clock by installing the timer handler
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* into IRQ0
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*/
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int timer_init(void)
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{
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uint64_t start;
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/* Installs 'timer_handler' to IRQ0 */
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irq_install_handler(0, timer_handler);
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return 0;
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}
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#define LATCH(f) ((CLOCK_TICK_RATE + f/2) / f)
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int timer_set_frequency(unsigned int freq)
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{
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irq_disable();
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/* set the timer frequency */
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#ifdef CONFIG_LAPICTIMER
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/* Use LAPIC timer instead of 8254 PIT */
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#else
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outportb(0x43, 0x34);
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udelay(10);
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outportb(0x40, LATCH(freq) & 0xFF); /* low byte */
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udelay(10);
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outportb(0x40, LATCH(freq) >> 8); /* high byte */
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#endif
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curr_timer_freq = freq;
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irq_enable();
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if (!has_apic()) {
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/* set default timer */
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outportb(0x43, 0x34);
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start = rdtsc();
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while(rdtsc() - start < 1000000)
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;
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outportb(0x40, LATCH(TIMER_FREQ) & 0xFF); /* low byte */
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start = rdtsc();
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while(rdtsc() - start < 1000000)
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;
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outportb(0x40, LATCH(TIMER_FREQ) >> 8); /* high byte */
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}
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return 0;
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}
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unsigned int timer_get_frequency(void)
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{
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return curr_timer_freq;
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}
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