Merge branch 'master' of git.lfbs.rwth-aachen.de:metalsvm into mailbox_integration
This commit is contained in:
Simon Pickartz
commit
39b79506bf
18 changed files with 927 additions and 64 deletions
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@ -26,9 +26,9 @@ MAKE = make
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NASMFLAGS = -felf32 -g
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INCLUDE = -I$(TOPDIR)/include -I$(TOPDIR)/arch/$(ARCH)/include -I$(TOPDIR)/lwip/src/include -I$(TOPDIR)/lwip/src/include/ipv4 -I$(TOPDIR)/drivers
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# Compiler options for final code
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CFLAGS = -g -m32 -march=i586 -Wall -O2 -fno-zero-initialized-in-bss -fno-builtin -fstrength-reduce -fomit-frame-pointer -finline-functions -nostdinc $(INCLUDE) -fno-stack-protector
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CFLAGS = -g -m32 -march=i586 -Wall -O2 -fno-builtin -fstrength-reduce -fomit-frame-pointer -finline-functions -nostdinc $(INCLUDE) -fno-stack-protector
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# Compiler options for debuuging
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#CFLAGS = -g -O -m32 -march=i586 -Wall -fno-zero-initialized-in-bss -fno-builtin -DWITH_FRAME_POINTER -nostdinc $(INCLUDE) -fno-stack-protector
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#CFLAGS = -g -O -m32 -march=i586 -Wall -fno-builtin -DWITH_FRAME_POINTER -nostdinc $(INCLUDE) -fno-stack-protector
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ARFLAGS = rsv
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RM = rm -rf
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LDFLAGS = -T link.ld -z max-page-size=4096 --defsym __BUILD_DATE=$(shell date +'%Y%m%d') --defsym __BUILD_TIME=$(shell date +'%H%M%S')
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@ -155,6 +155,9 @@
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#define CRB_X5_Y3 0xf7000000
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#define CRB_OWN 0xf8000000
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// FPGA registers
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#define FPGA_BASE 0xf9000000
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// Symbol for RPC
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#define RPC_BASE 0xfb000000
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@ -73,7 +73,7 @@ stublet:
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; clears the current pgd entry
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xor eax, eax
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mov cr3, eax
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; disable SSE support (TODO)
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; at this stage, we disable the SSE support
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mov eax, cr4
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and eax, 0xfffbf9ff
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mov cr4, eax
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@ -28,10 +28,10 @@
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gdt_ptr_t gp;
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static tss_t task_state_segments[MAX_TASKS] __attribute__ ((aligned (PAGE_SIZE)));
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static unsigned char kstacks[MAX_TASKS][KERNEL_STACK_SIZE] __attribute__ ((aligned (PAGE_SIZE)));
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static unsigned char kstacks[MAX_TASKS][KERNEL_STACK_SIZE] __attribute__ ((aligned (PAGE_SIZE), section (".data")));
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// currently, our kernel has full access to the ioports
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static gdt_entry_t gdt[GDT_ENTRIES] = {[0 ... GDT_ENTRIES-1] = {0, 0, 0, 0, 0, 0}};
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unsigned char* default_stack_pointer = kstacks[0] + KERNEL_STACK_SIZE - sizeof(size_t);
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unsigned char* default_stack_pointer __attribute__ ((section (".data"))) = kstacks[0] + KERNEL_STACK_SIZE - sizeof(size_t);
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/*
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* This is in start.asm. We use this to properly reload
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@ -37,7 +37,7 @@
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*/
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/** Global multiboot information structure pointer */
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multiboot_info_t* mb_info = NULL;
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multiboot_info_t* mb_info __attribute__ ((section (".data"))) = NULL;
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#endif
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/** @brief initialization procedure for Multiboot information structure
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@ -733,6 +733,10 @@ int arch_paging_init(void)
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// map SCC's message passing buffers
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viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+16*1024*1024) >> PAGE_SHIFT, MAP_KERNEL_SPACE|MAP_MPE);
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kprintf("Map message passing buffers at 0x%x\n", viraddr);
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// map the FPGA registers
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viraddr = map_region(FPGA_BASE, FPGA_BASE, 0x10000 >> PAGE_SHIFT, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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kprintf("Map FPGA regsiters at 0x%x\n", viraddr);
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#endif
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/* enable paging */
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@ -132,6 +132,7 @@ int icc_init(void)
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RCCE_barrier(&RCCE_COMM_WORLD);
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#if 0
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kputs("RCCE test...\t");
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if (my_ue == 0)
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msg = 0x4711;
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@ -139,6 +140,7 @@ int icc_init(void)
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kprintf("successfull! (0x%x)\n", msg);
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else
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kprintf("failed! (0x%x)\n", msg);
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#endif
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// reset INTR/LINT0 flag
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z = Z_PID(RC_COREID[my_ue]);
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@ -147,7 +149,7 @@ int icc_init(void)
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SetConfigReg(CRB_OWN + (z==0 ? GLCFG0 : GLCFG1), tmp);
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// set interrupt handler (INTR/LINT0)
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irq_install_handler(124, intr_handler);
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//irq_install_handler(124, intr_handler);
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kputs("Now, the SCC is initialized!\n");
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@ -1,4 +1,4 @@
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C_source := rtl8139.c
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C_source := rtl8139.c rckemac.c
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MODULE := drivers_net
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include $(TOPDIR)/Makefile.inc
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775
drivers/net/rckemac.c
Normal file
775
drivers/net/rckemac.c
Normal file
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@ -0,0 +1,775 @@
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/*
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* Copyright 2011 Stefan Lankes, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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/*
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* This eMAC driver required at least sccKit 1.4.0 and based on
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* the eMAC Driver Description (section 9.6.5) in the
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* SccKit 1.4.0 User’s Guide (Revision 0.92 Part 9).
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*/
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#include <metalsvm/stddef.h>
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#include <metalsvm/stdio.h>
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#include <metalsvm/string.h>
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#include <metalsvm/processor.h>
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#include <metalsvm/mailbox.h>
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#include <metalsvm/page.h>
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#include <metalsvm/time.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/RCCE.h>
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#include <asm/RCCE_lib.h>
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#include <asm/SCC_API.h>
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#if defined(CONFIG_LWIP) && defined(CONFIG_ROCKCREEK)
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#include <lwip/sys.h>
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#include <lwip/stats.h>
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#include <lwip/netif.h>
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#include <netif/etharp.h>
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#include <net/rckemac.h>
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/* Limits */
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#define BUFFER_ORDER 9
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#define BUFFER_NUM (1 << BUFFER_ORDER)
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#define BUFFER_SIZE (BUFFER_NUM * PAGE_SIZE)
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#define EMAC0 0x01
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#define EMAC1 0x02
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#define EMAC2 0x04
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#define EMAC3 0x08
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#define EMAC_IPCONF 0x3200
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#define EMAC_RX_CONTROL 0x9000
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#define EMAC_TX_CONTROL 0x9900
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/* IP configuration - offsets */
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#define CONFIG_FLOW_CONTROL_ADD 0xC0
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#define TRANSMITTER_ADDRESS 0x80
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#define RECEIVER1_ADDRESS 0x40
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#define CONFIG_ADD 0x100
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#define ADD_FILTER_MOD 0x190
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/* EMAC RX */
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#define EMAC_RX_BUFFER_START_ADDRESS 0x0000
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#define EMAC_RX_BUFFER_READ_OFFSET 0x0100
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#define EMAC_RX_BUFFER_WRITE_OFFSET 0x0200
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#define EMAC_RX_BUFFER_SIZE 0x0300
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#define EMAC_RX_BUFFER_THRESHOLD 0x0400
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#define EMAC_RX_MODE 0x0500
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#define EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI 0x0600
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#define EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO 0x0700
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#define EMAC_RX_NETWORK_PORT_ENABLE 0x0800
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/* EMAC TX */
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#define EMAC_TX_BUFFER_START_ADDRESS 0x0000
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#define EMAC_TX_BUFFER_READ_OFFSET 0x0100
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#define EMAC_TX_BUFFER_WRITE_OFFSET 0x0200
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#define EMAC_TX_BUFFER_SIZE 0x0300
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#define EMAC_TX_MODE 0x0400
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#define EMAC_TX_NETWORK_PORT_ENABLE 0x0500
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// Using of LVT1 as interrupt line
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#define EMAC_IRQ_MASK 0x00000001
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#define EMAC_IRQ_NR 3
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#define EMAC_LVT APIC_LVT1
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#define EMAC_IRQ_CONFIG 1
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#define IRQ_STATUS 0xD000
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#define IRQ_MASK 0xD200
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#define IRQ_RESET 0xD400
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#define IRQ_CONFIG 0xD800
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/* Cache line wrappers */
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#define CLINE_SHIFT 5
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#define CLINE_SIZE (1UL << CLINE_SHIFT)
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#define CLINE_MASK (~(CLINE_SIZE - 1))
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#define CLINE_ALIGN(_x) (((_x) + CLINE_SIZE - 1) & CLINE_MASK)
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#define CLINE_PACKETS(_x) (CLINE_ALIGN(_x) >> CLINE_SHIFT)
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/* Flush */
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#define CL1FLUSH __asm__ volatile (".byte 0x0F; .byte 0x0A;\n")
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/* Read 16bit from buffer */
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#define U16(_addr) (256 * (*((uint8_t*) (_addr + 1))) + (*((uint8_t*)(_addr))))
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#define MAC_ADDRESS 0x00454D414331ULL
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#define MAC_HI(_x) ((((_x) >> 32)) & 0xFFFF)
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#define MAC_LO(_x) (((_x) ) & 0xFFFFFFFF)
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static struct netif* mynetif;
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static int read_emac(int num_emac, int offset, int core)
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{
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int ret;
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ret = *((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4));
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/* no error: read twice, as xilinx ip need some time... */
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ret = *((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4));
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return ret;
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}
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static void write_emac(int num_emac, int offset, int core, int value)
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{
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*((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4)) = value;
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}
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/*
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* @return error code
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* - ERR_OK: packet transferred to hardware
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* - ERR_CONN: no link or link failure
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* - ERR_IF: could not transfer to link (hardware buffer full?)
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*/
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static err_t rckemacif_output(struct netif* netif, struct pbuf* p)
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{
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rckemacif_t* rckemacif = netif->state;
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uint32_t i;
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struct pbuf *q;
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void *addr;
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uint16_t read_offset;
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int rest;
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int packets;
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int sum = 0;
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/* check for over/underflow */
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if (BUILTIN_EXPECT((p->tot_len < 20) || (p->tot_len > 1536), 0)) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_output: illegal packet length %d => drop\n", p->len));
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return ERR_IF;
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}
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rckemacif->tx_write_offset++;
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/* check if we need to wrap */
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if (rckemacif->tx_write_offset > rckemacif->tx_buffer_max)
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rckemacif->tx_write_offset = 1;
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packets = CLINE_PACKETS(p->tot_len + 2);
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read_offset = read_emac(rckemacif->num_emac, EMAC_TX_CONTROL+EMAC_TX_BUFFER_READ_OFFSET, rckemacif->core);
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#if 1
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again:
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if (read_offset < rckemacif->tx_write_offset) {
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sum = rckemacif->tx_buffer_max - rckemacif->tx_write_offset + read_offset - 1;
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} else if (read_offset > rckemacif->tx_write_offset) {
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sum = read_offset - rckemacif->tx_write_offset - 1;
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}
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if (sum < packets) {
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LWIP_DEBUGF(NETIF_DEBUG, ("Warning: not enough space available, retrying...\n"));
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goto again;
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}
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#endif
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addr = rckemacif->tx_buffer + rckemacif->tx_write_offset * 32;
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/* Set frame length */
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((uint8_t*)addr)[0] = p->tot_len % 256;
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((uint8_t*)addr)[1] = p->tot_len / 256;
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#if ETH_PAD_SIZE
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pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
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#endif
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if (rckemacif->tx_write_offset + packets - 1 <= rckemacif->tx_buffer_max) {
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/*
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* q traverses through linked list of pbuf's
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* This list MUST consist of a single packet ONLY
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*/
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for (q=p, i=0; q!=0; q=q->next) {
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memcpy(((uint8_t*)addr) + 2 + i, q->payload, q->len);
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i += q->len;
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}
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/* increment write ptr */
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rckemacif->tx_write_offset += packets - 1;
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} else {
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/* wrap in offsets. first copy to the end, second at the starting
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* point
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*/
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int bytes_left = p->tot_len;
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int bytes_to_copy = (rckemacif->tx_buffer_max - rckemacif->tx_write_offset + 1) * 32 - 2;
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int sz = 0;
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if (bytes_left < bytes_to_copy)
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bytes_to_copy = bytes_left;
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LWIP_DEBUGF(NETIF_DEBUG, ("special case: copy last %d bytes\n", bytes_to_copy));
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q = p; i = 0;
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while ((q != 0) && (i < bytes_to_copy)) {
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sz = q->len > bytes_to_copy-i ? bytes_to_copy-i : q->len;
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memcpy(((uint8_t*) addr) + 2 + i, q->payload, sz);
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bytes_left -= sz;
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i += sz;
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if (i < bytes_to_copy)
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q = q->next;
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}
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if (bytes_left != 0) {
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rckemacif->tx_write_offset = 1;
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addr = rckemacif->tx_buffer + 32;
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LWIP_DEBUGF(NETIF_DEBUG, ("special case: copy remaining %d bytes\n", bytes_left));
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i = 0;
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if (sz < q->len) {
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memcpy((uint8_t*) addr, q->payload + sz, q->len - sz);
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bytes_left -= (q->len - sz);
|
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i = q->len - sz;
|
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}
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for(q=q->next; (q != 0); q = q->next) {
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memcpy(((uint8_t*) addr) + i, q->payload, q->len);
|
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i += q->len;
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}
|
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|
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rest = bytes_left % 32;
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if (rest != 0)
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rest = 32 - rest;
|
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|
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LWIP_DEBUGF(NETIF_DEBUG, ("Rest is %d\n", rest));
|
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rckemacif->tx_write_offset += CLINE_PACKETS(bytes_left + rest) - 1;
|
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}
|
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}
|
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|
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*((volatile int*) rckemacif->tx_buffer) = 2;
|
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|
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/* set new write offset */
|
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//LWIP_DEBUGF(NETIF_DEBUG, ("Update tx write offset: %d (read offset %d)\n", rckemacif->tx_write_offset, read_offset));
|
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write_emac(rckemacif->num_emac, EMAC_TX_CONTROL+EMAC_TX_BUFFER_WRITE_OFFSET, rckemacif->core, rckemacif->tx_write_offset);
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|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
|
||||
#endif
|
||||
|
||||
LINK_STATS_INC(link.xmit);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
static void rckemacif_rx_handler(struct netif* netif, unsigned int write_offset)
|
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{
|
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rckemacif_t* rckemacif = netif->state;
|
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unsigned short read_offset;
|
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unsigned int counter;
|
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volatile void *addr;
|
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uint16_t i, length;
|
||||
struct pbuf *p;
|
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struct pbuf* q;
|
||||
|
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if (write_offset > rckemacif->rx_buffer_max) {
|
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LWIP_DEBUGF(NETIF_DEBUG, ("Warning, write offset > buffer max!! (%d > %d)\n", write_offset, rckemacif->rx_buffer_max));
|
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read_offset = 1;
|
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write_emac(rckemacif->num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, rckemacif->core, read_offset);
|
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rckemacif->rx_read_offset = read_offset;
|
||||
return;
|
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}
|
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|
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while(1) {
|
||||
if ((write_offset != 0) && (rckemacif->rx_read_offset != write_offset)) {
|
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read_offset = rckemacif->rx_read_offset;
|
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read_offset++;
|
||||
if (read_offset < 1 || read_offset > rckemacif->rx_buffer_max) {
|
||||
read_offset = 1;
|
||||
}
|
||||
addr = rckemacif->rx_buffer + read_offset * 32;
|
||||
|
||||
length = U16(addr);
|
||||
|
||||
// Check for over/underflow
|
||||
if ((length < 20) || (length > 1536)) {
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_rx_handler(): illegal packet length %d => drop\n", length));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("start read at %d; write_offset at %d; addr: %p, packet len: %d\n", read_offset, write_offset, addr, length));
|
||||
|
||||
read_offset = write_offset;
|
||||
#if 1
|
||||
kprintf("Buffer:\n");
|
||||
for (i = 0; i < 32; i++) {
|
||||
kprintf("%2.2x ", ((char*)addr)[i] & 0xFF);
|
||||
}
|
||||
kprintf("\n");
|
||||
|
||||
kprintf("Buffer0:\n");
|
||||
for (i = 0; i < 32; i++) {
|
||||
kprintf("%2.2x ", ((char*)rckemacif->rx_buffer)[i] & 0xFF);
|
||||
}
|
||||
kprintf("\n");
|
||||
#endif
|
||||
|
||||
LINK_STATS_INC(link.memerr);
|
||||
LINK_STATS_INC(link.drop);
|
||||
|
||||
goto rxDone;
|
||||
}
|
||||
|
||||
#if ETH_PAD_SIZE
|
||||
length += ETH_PAD_SIZE; /* allow room for Ethernet padding */
|
||||
#endif
|
||||
//LWIP_DEBUGF(NETIF_DEBUG, ("length %u, read_offset %u, write_offset %u\n", length, read_offset, write_offset));
|
||||
|
||||
p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
|
||||
if (p) {
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
|
||||
#endif
|
||||
if (read_offset < write_offset) {
|
||||
for (q=p, counter=0; q!=NULL; q=q->next) {
|
||||
for(i=0; i<q->len; i++, counter++) {
|
||||
((uint8_t*) q->payload)[i] = ((uint8_t*)addr)[2 + counter];
|
||||
}
|
||||
}
|
||||
|
||||
read_offset += CLINE_PACKETS(p->len + 2) - 1;
|
||||
} else {
|
||||
int rest;
|
||||
int bytesLeft = length;
|
||||
int bytesToCopy = length;
|
||||
|
||||
/* rest to the end of buffer - 2 bytes length information */
|
||||
rest = (rckemacif->rx_buffer_max - read_offset + 1) * 32 - 2;
|
||||
if (length > rest)
|
||||
bytesToCopy = rest;
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("bytes to copy: %d, bytesLeft: %d\n", bytesToCopy, bytesLeft));
|
||||
|
||||
for (q=p, counter=0; q!=NULL; q=q->next) {
|
||||
for(i=0; i<q->len; i++, counter++) {
|
||||
if (counter < bytesToCopy)
|
||||
((uint8_t*) q->payload)[i] = ((uint8_t*)addr)[2 + counter];
|
||||
else
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
out:
|
||||
bytesLeft -= bytesToCopy;
|
||||
|
||||
if (bytesLeft != 0) {
|
||||
addr = rckemacif->rx_buffer + 0x20;
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("copying from %p, left: %d (%x)\n", addr, bytesLeft, ((uint8_t*)addr)[0]));
|
||||
for(counter=0; (i<q->len) && (counter < bytesLeft); i++, counter++)
|
||||
((uint8_t*) q->payload)[i] = ((uint8_t*)addr)[counter];
|
||||
for(q=q->next; (q!=NULL) && (counter < bytesLeft); q=q->next) {
|
||||
for(i=0; (i<q->len) && (counter < bytesLeft); i++, counter++) {
|
||||
((uint8_t*) q->payload)[i] = ((uint8_t*)addr)[counter];
|
||||
}
|
||||
}
|
||||
read_offset = CLINE_PACKETS(bytesLeft);
|
||||
} else {
|
||||
read_offset += CLINE_PACKETS(p->len + 2) - 1;
|
||||
}
|
||||
}
|
||||
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
|
||||
#endif
|
||||
mailbox_ptr_post(&rckemacif->mbox, (void*)p);
|
||||
LINK_STATS_INC(link.recv);
|
||||
} else {
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_rx_inthandler: not enough memory!\n"));
|
||||
LINK_STATS_INC(link.memerr);
|
||||
LINK_STATS_INC(link.drop);
|
||||
}
|
||||
|
||||
rxDone:
|
||||
/* set new read pointer */
|
||||
//LWIP_DEBUGF(NETIF_DEBUG, ("Update rx read offset: %d\n", read_offset));
|
||||
write_emac(rckemacif->num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, rckemacif->core, read_offset);
|
||||
rckemacif->rx_read_offset = read_offset;
|
||||
} else break;
|
||||
}
|
||||
}
|
||||
|
||||
static void rckemacif_handler(struct state* s)
|
||||
{
|
||||
unsigned int status, tmp;
|
||||
unsigned int write_offset;
|
||||
rckemacif_t* rckemacif = mynetif->state;
|
||||
|
||||
status = *((volatile int*) (FPGA_BASE + IRQ_STATUS + rckemacif->core * 2 * 4));
|
||||
// read twice to be sure
|
||||
status = *((volatile int*) (FPGA_BASE + IRQ_STATUS + rckemacif->core * 2 * 4));
|
||||
if (!(status & (1 << rckemacif->num_emac))) {
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_handler: no interrupt\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
nexttry:
|
||||
/* check for updated write offset */
|
||||
CL1FLUSH;
|
||||
write_offset = *((volatile unsigned int*) (rckemacif->rx_buffer)) & 0xFFFF;
|
||||
//write_offset = read_emac(rckemacif->num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_WRITE_OFFSET, rckemacif->core);
|
||||
if ((write_offset != 0) && (rckemacif->rx_read_offset != write_offset)) {
|
||||
rckemacif_rx_handler(mynetif, write_offset);
|
||||
goto nexttry;
|
||||
}
|
||||
|
||||
/* Set interrupt bit */
|
||||
tmp = *((volatile unsigned int*) rckemacif->irq_address);
|
||||
tmp &= ~(EMAC_IRQ_MASK);
|
||||
*((volatile unsigned int*) rckemacif->irq_address) = tmp;
|
||||
|
||||
/* Reset */
|
||||
*((volatile unsigned*) (FPGA_BASE + IRQ_RESET + rckemacif->core * 2 * 4)) = (1 << rckemacif->num_emac);
|
||||
}
|
||||
|
||||
err_t rckemacif_wait(struct netif* netif, uint32_t poll)
|
||||
{
|
||||
rckemacif_t* rckemacif = netif->state;
|
||||
struct eth_hdr *ethhdr;
|
||||
struct pbuf *p = NULL;
|
||||
err_t err = ERR_OK;
|
||||
|
||||
if (poll) {
|
||||
if (mailbox_ptr_tryfetch(&(rckemacif->mbox), (void**) &p))
|
||||
return err;
|
||||
} else {
|
||||
mailbox_ptr_fetch(&(rckemacif->mbox), (void**) &p);
|
||||
}
|
||||
|
||||
/* points to packet payload, which starts with an Ethernet header */
|
||||
ethhdr = p->payload;
|
||||
|
||||
//LWIP_DEBUGF(NETIF_DEBUG, ("Got packet of type 0x%x!\n", htons(ethhdr->type)));
|
||||
|
||||
switch (htons(ethhdr->type)) {
|
||||
/* IP or ARP packet? */
|
||||
case ETHTYPE_ARP:
|
||||
case ETHTYPE_IP:
|
||||
#if PPPOE_SUPPORT
|
||||
/* PPPoE packet? */
|
||||
case ETHTYPE_PPPOEDISC:
|
||||
case ETHTYPE_PPPOE:
|
||||
#endif /* PPPOE_SUPPORT */
|
||||
/* full packet send to tcpip_thread to process */
|
||||
if ((err = mynetif->input(p, mynetif)) != ERR_OK) {
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_poll: IP input error\n"));
|
||||
pbuf_free(p);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
pbuf_free(p);
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
err_t rckemacif_init(struct netif* netif)
|
||||
{
|
||||
rckemacif_t* rckemacif;
|
||||
int num_emac;
|
||||
int macPorts;
|
||||
int i, tmp, x, y, z, core;
|
||||
uint64_t tile_offset;
|
||||
uint16_t write_offset;
|
||||
uint16_t read_offset;
|
||||
int mode;
|
||||
int subdest;
|
||||
int route;
|
||||
|
||||
LWIP_ASSERT("netif != NULL", (netif != NULL));
|
||||
|
||||
// Find out who I am...
|
||||
tmp = ReadConfigReg(CRB_OWN+MYTILEID);
|
||||
x = (tmp>>3) & 0x0f; // bits 06:03
|
||||
y = (tmp>>7) & 0x0f; // bits 10:07
|
||||
z = (tmp ) & 0x07; // bits 02:00
|
||||
core = 12 * y + 2 * x + z;
|
||||
|
||||
rckemacif = kmalloc(sizeof(rckemacif_t));
|
||||
if (!rckemacif) {
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: out of memory\n"));
|
||||
return ERR_MEM;
|
||||
}
|
||||
memset(rckemacif, 0, sizeof(rckemacif_t));
|
||||
rckemacif->core = core;
|
||||
|
||||
/* allocate the receive buffer */
|
||||
rckemacif->rx_buffer = mem_allocation(BUFFER_SIZE, MAP_KERNEL_SPACE|MAP_NO_CACHE);
|
||||
if (!(rckemacif->rx_buffer)) {
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: out of memory\n"));
|
||||
kfree(rckemacif, sizeof(rckemacif_t));
|
||||
return ERR_MEM;
|
||||
}
|
||||
memset(rckemacif->rx_buffer, 0x00, 0x20);
|
||||
memset(rckemacif->rx_buffer + 0x20, 0xDA, BUFFER_SIZE - 0x20);
|
||||
rckemacif->rx_buffer_max = CLINE_PACKETS(BUFFER_SIZE) - 1;
|
||||
|
||||
/* allocate the send buffers */
|
||||
rckemacif->tx_buffer = mem_allocation(BUFFER_SIZE, MAP_KERNEL_SPACE|MAP_NO_CACHE);
|
||||
if (!(rckemacif->tx_buffer)) {
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: out of memory\n"));
|
||||
kfree(rckemacif->rx_buffer, BUFFER_SIZE);
|
||||
kfree(rckemacif, sizeof(rckemacif_t));
|
||||
return ERR_MEM;
|
||||
}
|
||||
memset(rckemacif->tx_buffer, 0x00, 0x20);
|
||||
memset(rckemacif->tx_buffer + 0x20, 0xDA, BUFFER_SIZE - 0x20);
|
||||
rckemacif->tx_buffer_max = CLINE_PACKETS(BUFFER_SIZE) - 1;
|
||||
|
||||
mailbox_ptr_init(&rckemacif->mbox);
|
||||
netif->state = rckemacif;
|
||||
|
||||
/* Depending on core location read own private data
|
||||
* (offset, subdest, route)
|
||||
*/
|
||||
if (z == 0) {
|
||||
tmp = ReadConfigReg(CRB_OWN + LUT0);
|
||||
rckemacif->irq_address = (void*) (CRB_OWN + GLCFG0);
|
||||
} else {
|
||||
tmp = ReadConfigReg(CRB_OWN + LUT1);
|
||||
rckemacif->irq_address = (void*) (CRB_OWN + GLCFG1);
|
||||
}
|
||||
tile_offset = (uint64_t)((uint64_t) tmp & 0x3FF) << 24;
|
||||
subdest = (tmp >> 10) & 0x07;
|
||||
route = (tmp >> 13) & 0xFF;
|
||||
mode = (subdest << 8) + route;
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("tile_offset = 0x%llx\n", tile_offset));
|
||||
|
||||
/* get fpga/sccKit port settings */
|
||||
tmp = *((volatile int*)(FPGA_BASE + 0x822C));
|
||||
tmp = *((volatile int*)(FPGA_BASE + 0x822C));
|
||||
macPorts = ((tmp >> 9 ) & 0xFF);
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: eMAC0: %s eMAC1: %s eMAC2: %s eMAC3: %s\n",
|
||||
(macPorts & EMAC0) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC1) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC2) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC3) != 0 ? "present" : "-"));
|
||||
|
||||
// determine device and emac number
|
||||
num_emac=0;
|
||||
while (((macPorts & (1 << num_emac)) == 0) && (num_emac < 4))
|
||||
num_emac++;
|
||||
if (num_emac >= 4)
|
||||
return ERR_ARG;
|
||||
mynetif = netif;
|
||||
rckemacif->num_emac = num_emac;
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: used eMAC device %d\n", num_emac));
|
||||
|
||||
tmp = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||||
tmp = read_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0);
|
||||
|
||||
if (core == 0) {
|
||||
/* Only core 0 initialize the xilinx port */
|
||||
int flow_control = 0;
|
||||
int transmitter_addr = 0;
|
||||
int receiver1_addr = 0;
|
||||
int config_add = 0;
|
||||
int add_filter_mod = 0;
|
||||
|
||||
/* Disable tx and rx flow control of eMAC */
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Disabling tx/rx flow control of eMAC%d\n", num_emac));
|
||||
flow_control = read_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0);
|
||||
|
||||
/* Set top 3 bits of the flow control configuration to zero,
|
||||
* therefore disabling tx and rx flow control
|
||||
*/
|
||||
flow_control &= 0x7FFFFFF;
|
||||
write_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0, flow_control);
|
||||
|
||||
/* Sanity check */
|
||||
flow_control = read_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" CONFIG_FLOW_CONTROL_ADD set: 0x%x\n", flow_control));
|
||||
|
||||
/* Setting the tx configuration bit to enable the transmitter and
|
||||
* set to full duplex mode.
|
||||
*/
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Setting rx configuration of eMAC%d\n", num_emac));
|
||||
transmitter_addr = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||||
|
||||
/* Now set the relevant bits and write back into the register:
|
||||
* 26 (half duplex) = 0, 28 (transmit enable) = 1, 31 (reset) = 0
|
||||
*/
|
||||
transmitter_addr &= ~(1 << 31);
|
||||
transmitter_addr &= ~(1 << 26);
|
||||
transmitter_addr |= (1 << 28);
|
||||
write_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0, transmitter_addr);
|
||||
|
||||
transmitter_addr = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TRANSMITTER_ADDRESS set: %x\n", transmitter_addr));
|
||||
|
||||
/* Setting the rx configuration bit to enable the transmitter and
|
||||
* set to full duplex mode.
|
||||
*/
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Setting IP configuration of EMAC%d\n", num_emac));
|
||||
|
||||
/* Read the current config value from the register */
|
||||
receiver1_addr = read_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0);
|
||||
|
||||
/* Now set the relevant bits and write back into the register:
|
||||
* 25 = 1, 26 = 0, 28 = 1, 31 = 0
|
||||
*/
|
||||
/* Length/Type Error Check Disable */
|
||||
receiver1_addr |= (1 << 25);
|
||||
/* Disable Half Duplex => Full Duplex */
|
||||
receiver1_addr &= ~(1 << 26);
|
||||
/* Receiver enable */
|
||||
receiver1_addr |= (1 << 28);
|
||||
/* Reset */
|
||||
receiver1_addr &= ~(1 << 31);
|
||||
write_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0, receiver1_addr);
|
||||
|
||||
receiver1_addr = read_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RECEIVER1_ADDRESS set: %x\n", receiver1_addr));
|
||||
|
||||
/* Setting the speed to eMAC to 1Gb/s */
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Setting speed of EMAC%d to 1Gb/s\n", num_emac));
|
||||
|
||||
/* Read the current config value from register */
|
||||
config_add = read_emac(num_emac, EMAC_IPCONF+CONFIG_ADD, 0);
|
||||
|
||||
/* Now set the relevant bits and write back into the register:
|
||||
* 31 = 1, 30 = 0
|
||||
*/
|
||||
/* MAC Speed Configuration: 00 - 10Mbps, 01 - 100Mbps, 10 - 1Gbps */
|
||||
config_add |= (1 << 31);
|
||||
config_add &= ~(1 << 30);
|
||||
write_emac(num_emac, EMAC_IPCONF+CONFIG_ADD, 0, config_add);
|
||||
|
||||
config_add = read_emac(num_emac, EMAC_IPCONF+CONFIG_ADD, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" CONFIG_ADD set: %x\n", config_add));
|
||||
|
||||
/* Read the current config addr filter mode */
|
||||
add_filter_mod = read_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0);
|
||||
|
||||
/* Not set the relevant bits and write back into the register:
|
||||
* 31 (promiscuous mode) = 1 not working, but thats ok!
|
||||
*/
|
||||
add_filter_mod |= (1 << 31);
|
||||
write_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0, add_filter_mod);
|
||||
|
||||
add_filter_mod = read_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" ADD_FILTER_MOD set: %x\n", add_filter_mod));
|
||||
}
|
||||
|
||||
sleep(3);
|
||||
|
||||
/* Start address */
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer %p (%lx phys)\n", rckemacif->rx_buffer, virt_to_phys((uint32_t)rckemacif->rx_buffer)));
|
||||
|
||||
/**** Receiver configuration ****/
|
||||
|
||||
uint64_t addr_offset = (tile_offset + (uint64_t) virt_to_phys((uint32_t) rckemacif->rx_buffer)) >> 5;
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_START_ADDRESS, core, (uint32_t) addr_offset);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer set to @%x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_START_ADDRESS, core)));
|
||||
|
||||
/* Get buffer write offset */
|
||||
write_offset = read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_WRITE_OFFSET, core);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer write offset at: %d\n", write_offset));
|
||||
|
||||
/* Set buffer read offset to write offset */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, core, write_offset);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer read offset set to: %d\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, core)));
|
||||
rckemacif->rx_read_offset = write_offset;
|
||||
|
||||
/* Size */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_SIZE, core, rckemacif->rx_buffer_max);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Size set to %d\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_SIZE, core)));
|
||||
|
||||
/* Threshold */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_THRESHOLD, core, 0x01);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Threshold set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_THRESHOLD, core)));
|
||||
|
||||
/* Route */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_MODE, core, (z << 24) | (((y << 4) | x) << 16) | mode);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Mode set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_MODE, core)));
|
||||
|
||||
// determine mac address
|
||||
uint32_t mac1 = *((volatile uint32_t*)(FPGA_BASE+0x7E00));
|
||||
uint32_t mac2 = *((volatile uint32_t*)(FPGA_BASE+0x7E04));
|
||||
uint64_t mac = (((unsigned long long)mac1) << 32) + (unsigned long long) mac2;
|
||||
if (mac == 0x00)
|
||||
mac = MAC_ADDRESS;
|
||||
/* Calculate mac address of core depending on selected emac device */
|
||||
mac = mac + (1 << num_emac) * 0x100 + core;
|
||||
|
||||
for (i=0; i<6; i++)
|
||||
mynetif->hwaddr[5-i] = (mac >> (i*8)) & 0xFF;
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: MAC address "));
|
||||
for (i=0; i<6; i++)
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("%02x ", mynetif->hwaddr[i]));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
|
||||
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI, core, MAC_HI(mac));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" MAC1 set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI, core)));
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO, core, MAC_LO(mac));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" MAC2 set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO, core)));
|
||||
|
||||
/* Activate network port by setting enable bit */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_ENABLE, core, 0x01);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Port enable set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_ENABLE, core)));
|
||||
|
||||
/**** Transfer configuration ****/
|
||||
|
||||
/* Start address */
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer %p (%lx phys)\n", rckemacif->tx_buffer, virt_to_phys((uint32_t)rckemacif->tx_buffer)));
|
||||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_START_ADDRESS, core, (uint32_t) (((uint64_t) virt_to_phys((uint32_t)rckemacif->tx_buffer) + tile_offset) >> 5));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer set to @%x\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_START_ADDRESS, core)));
|
||||
|
||||
/* Get buffer read offset */
|
||||
read_offset = read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_READ_OFFSET, core);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer read offset at: %d\n", read_offset));
|
||||
|
||||
/* Set buffer write offset to read offset */
|
||||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_WRITE_OFFSET, core, read_offset);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer write offset set to: %d\n", read_emac(num_emac, EMAC_TX_CONTROL+ EMAC_TX_BUFFER_WRITE_OFFSET, core)));
|
||||
rckemacif->tx_write_offset = read_offset;
|
||||
|
||||
/* Size */
|
||||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_SIZE, core, rckemacif->tx_buffer_max);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Size set to %d\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_SIZE, core)));
|
||||
|
||||
/* Route */
|
||||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_MODE, core, mode);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Mode set to %x\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_MODE, core)));
|
||||
|
||||
/* Activate network port by setting enable bit */
|
||||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_NETWORK_PORT_ENABLE, core, 0x01);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Port enable set to %x\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_NETWORK_PORT_ENABLE, core)));
|
||||
|
||||
// set interrupt handler (INTR/LINT0)
|
||||
irq_install_handler(125, rckemacif_handler);
|
||||
|
||||
/* Enable interrupt */
|
||||
tmp = *((volatile int*) (FPGA_BASE + IRQ_MASK + core * 2 * 4));
|
||||
*((volatile int*) (FPGA_BASE + IRQ_MASK + core * 2 * 4)) = tmp & ~(1 << num_emac);
|
||||
*((volatile int*) (FPGA_BASE + IRQ_CONFIG + core * 4)) = EMAC_IRQ_CONFIG;
|
||||
|
||||
/*
|
||||
* Initialize the snmp variables and counters inside the struct netif.
|
||||
* The last argument should be replaced with your link speed, in units
|
||||
* of bits per second.
|
||||
*/
|
||||
NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 1000 /* speed */);
|
||||
|
||||
/* administrative details */
|
||||
netif->name[0] = 'e';
|
||||
netif->name[1] = 'n';
|
||||
netif->num = 0;
|
||||
/* downward functions */
|
||||
netif->output = etharp_output;
|
||||
netif->linkoutput = rckemacif_output;
|
||||
/* maximum transfer unit */
|
||||
netif->mtu = 1500;
|
||||
/* broadcast capability */
|
||||
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
|
||||
/* hardware address length */
|
||||
netif->hwaddr_len = 6;
|
||||
|
||||
rckemacif->ethaddr = (struct eth_addr *)netif->hwaddr;
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
#endif
|
||||
61
drivers/net/rckemac.h
Normal file
61
drivers/net/rckemac.h
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright 2011 Stefan Lankes, Chair for Operating Systems,
|
||||
* RWTH Aachen University
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* This file is part of MetalSVM.
|
||||
*/
|
||||
|
||||
#ifndef __HAVE_RCKEMAC_H__
|
||||
#define __HAVE_RCKEMAC_H__
|
||||
|
||||
#include <metalsvm/stddef.h>
|
||||
#include <metalsvm/mailbox.h>
|
||||
|
||||
#if defined(CONFIG_LWIP) && defined(CONFIG_ROCKCREEK)
|
||||
|
||||
/*
|
||||
* Helper struct to hold private data used to operate your ethernet interface.
|
||||
*/
|
||||
typedef struct rckemacif {
|
||||
struct eth_addr *ethaddr;
|
||||
/* Add whatever per-interface state that is needed here. */
|
||||
uint8_t* rx_buffer;
|
||||
uint32_t rx_buffer_max;
|
||||
uint32_t rx_read_offset;
|
||||
uint8_t* tx_buffer;
|
||||
uint32_t tx_buffer_max;
|
||||
uint32_t tx_write_offset;
|
||||
void* irq_address;
|
||||
uint32_t core;
|
||||
uint32_t num_emac;
|
||||
mailbox_ptr_t mbox;
|
||||
} rckemacif_t;
|
||||
|
||||
/*
|
||||
* Wait for incoming messages.
|
||||
*
|
||||
* poll = 0 : wait blocks until a message is received
|
||||
* poll != 0: non-blocking wait
|
||||
*/
|
||||
err_t rckemacif_wait(struct netif* netif, uint32_t poll);
|
||||
|
||||
/*
|
||||
* Initialize the eMAC network driver
|
||||
*/
|
||||
err_t rckemacif_init(struct netif* netif);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -37,20 +37,37 @@
|
|||
#include <netif/etharp.h>
|
||||
#endif
|
||||
#include <net/rtl8139.h>
|
||||
#include <net/rckemac.h>
|
||||
#ifdef CONFIG_ROCKCREEK
|
||||
#include <asm/RCCE.h>
|
||||
#include <asm/RCCE_lib.h>
|
||||
#endif
|
||||
|
||||
void echo_init(void);
|
||||
void ping_init(void);
|
||||
|
||||
static volatile int done = 0;
|
||||
|
||||
/*
|
||||
* Note that linker symbols are not variables, they have no memory allocated for
|
||||
* maintaining a value, rather their address is their value.
|
||||
*/
|
||||
extern const void bss_start;
|
||||
extern const void bss_end;
|
||||
|
||||
int lowlevel_init(void)
|
||||
{
|
||||
// initialize .bss section
|
||||
memset((void*)&bss_start, 0x00, ((size_t) &bss_end - (size_t) &bss_start));
|
||||
|
||||
koutput_init();
|
||||
|
||||
//kprintf("Now, the BSS section (0x%x - 0x%x) is initialized.\n", (size_t) &bss_start, (size_t) &bss_end);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_LWIP) && defined(CONFIG_PCI)
|
||||
#if defined(CONFIG_LWIP) && (defined(CONFIG_PCI) || defined(CONFIG_ROCKCREEK))
|
||||
static tid_t netid;
|
||||
|
||||
int STDCALL network_task(void* arg)
|
||||
|
|
@ -62,10 +79,15 @@ int STDCALL network_task(void* arg)
|
|||
|
||||
kputs("Network task is started\n");
|
||||
|
||||
#ifdef CONFIG_ROCKCREEK
|
||||
/* Set network address variables */
|
||||
//IP4_ADDR(&gw, 192,168,1,254);
|
||||
//IP4_ADDR(&ipaddr, 192,168,1,100);
|
||||
//IP4_ADDR(&netmask, 255,255,255,0);
|
||||
IP4_ADDR(&gw, 192,168,4,254);
|
||||
IP4_ADDR(&ipaddr, 192,168,4,RCCE_ue()+1);
|
||||
IP4_ADDR(&netmask, 255,255,255,0);
|
||||
|
||||
/* Bring up the network interface */
|
||||
if (!netif_add(&netif, &ipaddr, &netmask, &gw, NULL, rckemacif_init, ethernet_input)) {
|
||||
#else
|
||||
/* Clear network address because we use DHCP to get an ip address */
|
||||
IP4_ADDR(&gw, 0,0,0,0);
|
||||
IP4_ADDR(&ipaddr, 0,0,0,0);
|
||||
|
|
@ -73,17 +95,15 @@ int STDCALL network_task(void* arg)
|
|||
|
||||
/* Bring up the network interface */
|
||||
if (!netif_add(&netif, &ipaddr, &netmask, &gw, NULL, rtl8139if_init, ethernet_input)) {
|
||||
#endif
|
||||
kputs("Unable to add network interface\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
netif_set_default(&netif);
|
||||
netif_set_up(&netif);
|
||||
|
||||
if (netif_is_up(&netif)) {
|
||||
kputs("Network interface is not up\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_ROCKCREEK
|
||||
kprintf("Starting DHCPCD...\n");
|
||||
dhcp_start(&netif);
|
||||
|
||||
|
|
@ -92,17 +112,24 @@ int STDCALL network_task(void* arg)
|
|||
rtl8139if_wait(&netif, 1);
|
||||
udelay(500000);
|
||||
}
|
||||
#endif
|
||||
|
||||
// start echo and ping server
|
||||
echo_init();
|
||||
ping_init();
|
||||
|
||||
while(!done) {
|
||||
#ifdef CONFIG_PCI
|
||||
rtl8139if_wait(&netif, 0);
|
||||
#elif defined(CONFIG_ROCKCREEK)
|
||||
rckemacif_wait(&netif, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef CONFIG_ROCKCREEK
|
||||
dhcp_release(&netif);
|
||||
dhcp_stop(&netif);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -122,7 +149,7 @@ int network_init(void)
|
|||
lwip_init();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LWIP) && defined(CONFIG_PCI)
|
||||
#if defined(CONFIG_LWIP) && (defined(CONFIG_PCI) || defined(CONFIG_ROCKCREEK))
|
||||
return create_kernel_task(&netid, network_task, NULL);
|
||||
#else
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -53,6 +53,10 @@
|
|||
#include <lwip/timers.h>
|
||||
#include <lwip/inet_chksum.h>
|
||||
|
||||
#if LWIP_SOCKET
|
||||
#define PING_USE_SOCKETS 1
|
||||
#endif
|
||||
|
||||
#if PING_USE_SOCKETS
|
||||
#include <lwip/sockets.h>
|
||||
#include <lwip/inet.h>
|
||||
|
|
@ -68,7 +72,7 @@
|
|||
|
||||
/** ping target - should be a "ip_addr_t" */
|
||||
#ifndef PING_TARGET
|
||||
#define PING_TARGET (netif_default?netif_default->gw:ip_addr_any)
|
||||
#define PING_TARGET (netif_default?netif_default->gw:ip_addr_any)
|
||||
#endif
|
||||
|
||||
/** ping receive timeout - in milliseconds */
|
||||
|
|
|
|||
|
|
@ -137,10 +137,5 @@ int test_init(void)
|
|||
//create_user_task(NULL, "/bin/jacobi", argv);
|
||||
//create_user_task(NULL, "/bin/jacobi", argv);
|
||||
|
||||
#ifdef CONFIG_LWIP
|
||||
// use ping to test LWIP
|
||||
ping_send_now();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
5
link.ld
5
link.ld
|
|
@ -13,9 +13,6 @@ SECTIONS
|
|||
.text ALIGN(4096) : AT(ADDR(.text)) {
|
||||
*(.text)
|
||||
}
|
||||
.rdata ALIGN(4096) : AT(ADDR(.rdata)) {
|
||||
*(.rdata)
|
||||
}
|
||||
.rodata ALIGN(4096) : AT(ADDR(.rodata)) {
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
|
|
@ -23,8 +20,10 @@ SECTIONS
|
|||
.data ALIGN(4096) : AT(ADDR(.data)) {
|
||||
*(.data)
|
||||
}
|
||||
bss_start = .;
|
||||
.bss ALIGN(4096) : AT(ADDR(.bss)) {
|
||||
*(.bss)
|
||||
}
|
||||
bss_end = .;
|
||||
kernel_end = .;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
C_source := err.c
|
||||
C_source := api_lib.c api_msg.c err.c netbuf.c netifapi.c sockets.c tcpip.c
|
||||
MODULE := lwip_src_api
|
||||
|
||||
include $(TOPDIR)/Makefile.inc
|
||||
|
|
|
|||
|
|
@ -3,6 +3,9 @@
|
|||
|
||||
#include <asm/tasks.h>
|
||||
#include <metalsvm/mailbox.h>
|
||||
#include <metalsvm/errno.h>
|
||||
|
||||
#define EWOULDBLOCK EAGAIN /* Operation would block */
|
||||
|
||||
typedef sem_t sys_mutex_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -9,21 +9,15 @@
|
|||
*/
|
||||
#define NO_SYS 0
|
||||
|
||||
/**
|
||||
* NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1
|
||||
* Mainly for compatibility to old versions.
|
||||
*/
|
||||
#define NO_SYS_NO_TIMERS 0
|
||||
|
||||
/**
|
||||
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
|
||||
*/
|
||||
#define LWIP_SOCKET 0
|
||||
#define LWIP_SOCKET 1
|
||||
|
||||
/**
|
||||
* LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
|
||||
*/
|
||||
#define LWIP_NETCONN 0
|
||||
#define LWIP_NETCONN 1
|
||||
|
||||
/**
|
||||
* LWIP_DHCP==1: Enable DHCP module.
|
||||
|
|
@ -35,34 +29,27 @@
|
|||
*/
|
||||
#define DHCP_DOES_ARP_CHECK 0
|
||||
|
||||
/**
|
||||
* ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
|
||||
* updated with the source MAC and IP addresses supplied in the packet.
|
||||
* You may want to disable this if you do not trust LAN peers to have the
|
||||
* correct addresses, or as a limited approach to attempt to handle
|
||||
* spoofing. If disabled, lwIP will need to make a new ARP request if
|
||||
* the peer is not already in the ARP table, adding a little latency.
|
||||
* The peer *is* in the ARP table if it requested our address before.
|
||||
* Also notice that this slows down input processing of every IP packet!
|
||||
*/
|
||||
#define ETHARP_TRUST_IP_MAC 1
|
||||
|
||||
/**
|
||||
* LWIP_TCP==1: Turn on TCP.
|
||||
*/
|
||||
#define LWIP_TCP 1
|
||||
|
||||
/**
|
||||
* TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
|
||||
* Define to 0 if your device is low on memory.
|
||||
*/
|
||||
#ifndef TCP_QUEUE_OOSEQ
|
||||
#define TCP_QUEUE_OOSEQ 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* TCP_SND_BUF: TCP sender buffer space (bytes).
|
||||
*/
|
||||
#ifndef TCP_SND_BUF
|
||||
#define TCP_SND_BUF 2048
|
||||
#endif
|
||||
|
||||
/**
|
||||
* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
|
||||
* as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
|
||||
*/
|
||||
#ifndef TCP_SND_QUEUELEN
|
||||
#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
|
||||
|
|
@ -74,22 +61,22 @@
|
|||
*/
|
||||
#define LWIP_MULTICAST_PING 1
|
||||
|
||||
/**
|
||||
* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
|
||||
* (requires NO_SYS==0)
|
||||
*/
|
||||
#define MEMP_NUM_SYS_TIMEOUT 7
|
||||
|
||||
/**
|
||||
* LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c
|
||||
*/
|
||||
#define LWIP_HAVE_LOOPIF 0
|
||||
#define LWIP_HAVE_LOOPIF 1
|
||||
|
||||
/**
|
||||
* LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
|
||||
* address equal to the netif IP address, looping them back up the stack.
|
||||
*/
|
||||
#define LWIP_NETIF_LOOPBACK 0
|
||||
|
||||
/**
|
||||
* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
|
||||
* (requires NO_SYS==0)
|
||||
*/
|
||||
#define MEMP_NUM_SYS_TIMEOUT 7
|
||||
#define LWIP_NETIF_LOOPBACK 1
|
||||
|
||||
/**
|
||||
* LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
*
|
||||
* Set whole address space as occupied
|
||||
*/
|
||||
static uint8_t bitmap[BITMAP_SIZE] = {[0 ... BITMAP_SIZE-1] = 0xFF};
|
||||
static uint8_t bitmap[BITMAP_SIZE]; // = {[0 ... BITMAP_SIZE-1] = 0xFF};
|
||||
static spinlock_t bitmap_lock = SPINLOCK_INIT;
|
||||
static size_t alloc_start;
|
||||
atomic_int32_t total_pages = ATOMIC_INIT(0);
|
||||
|
|
@ -94,6 +94,9 @@ int mmu_init(void)
|
|||
unsigned int i;
|
||||
size_t addr;
|
||||
|
||||
// at first, set default value of the bitmap
|
||||
memset(bitmap, 0xFF, sizeof(uint8_t)*BITMAP_SIZE);
|
||||
|
||||
#ifdef CONFIG_MULTIBOOT
|
||||
if (mb_info && (mb_info->flags & MULTIBOOT_INFO_MEM_MAP)) {
|
||||
size_t end_addr;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue