reorganized 64bit paging initialization
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403c529e8b
commit
3be25b99d2
1 changed files with 128 additions and 120 deletions
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@ -88,11 +88,11 @@ SECTION .data
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; create default page tables for the 64bit kernel
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global boot_pml4
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ALIGN 4096 ; of course, the page tables have to be page aligned
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NOPTS equ 512
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MAP_ENTRIES equ 512
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boot_pml4 times 512 DQ 0
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boot_pdpt times 512 DQ 0
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boot_pd times 512 DQ 0
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boot_pt times (NOPTS*512) DQ 0
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boot_pt times (MAP_ENTRIES*512) DQ 0
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SECTION .text
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ALIGN 8
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@ -101,17 +101,16 @@ global smp_entry
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smp_entry:
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; initialize cpu features
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call cpu_init
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; initialize page table
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; initialize cr3 register
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mov edi, boot_pml4
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mov cr3, edi
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; we need to enable PAE modus
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; enable PAE
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; switch to the compatibility mode (which is part of long mode)
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; enable longmode (compatibility mode)
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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@ -122,6 +121,7 @@ smp_entry:
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or eax, 1 << 31 | 1 << 0 ; Set the PG-bit, which is the 31nd bit, and the PE-bit, which is the 0th bit.
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mov cr0, eax ; According to the multiboot spec the PE-bit has to be set by bootloader already!
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; jump to 64-bit longmode
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mov edi, [esp+4] ; set argumet for smp_start
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lgdt [GDT64.Pointer] ; Load the 64-bit global descriptor table.
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jmp GDT64.Code:smp_start64 ; Set the code segment and enter 64-bit long mode.
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@ -129,36 +129,89 @@ smp_entry:
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jmp $ ; endless loop
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%endif
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search_apic:
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; search MP Floating Pointer Structure
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search_mps:
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push ebp
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mov ebp, esp
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push ecx
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xor eax, eax
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mov ecx, [ebp+8]
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L1:
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.l1:
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cmp [ecx], DWORD 0x5f504d5f ; MP_FLT_SIGNATURE
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jne L2
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jne .l2
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mov al, BYTE [ecx+9]
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cmp eax, 4
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ja L2
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ja .l2
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mov al, BYTE [ecx+11]
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cmp eax, 0
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jne L2
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jne .l2
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mov eax, ecx
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jmp L3
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jmp .l3
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L2:
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.l2:
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add ecx, 4
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cmp ecx, [ebp+12]
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jb L1
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jb .l1
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xor eax, eax
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L3:
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.l3:
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pop ecx
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pop ebp
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ret
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check_longmode:
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; check for cpuid instruction
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pushfd
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pop eax
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mov ecx, eax
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xor eax, 1 << 21
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push eax
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popfd
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pushfd
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pop eax
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push ecx
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popfd
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xor eax, ecx
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jz .unsupported
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; check for extended cpu features (cpuid > 0x80000000)
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb .unsupported ; It is less, there is no long mode.
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; check if longmode is supported
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mov eax, 0x80000001
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cpuid
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test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
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jz .unsupported ; They aren't, there is no long mode.
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ret
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.unsupported:
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jmp $
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check_lapic:
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push eax
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push ebx
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push ecx
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push edx
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mov eax, 1
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cpuid
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and edx, 0x200
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cmp edx, 0
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je .unsupported
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; map lapic at 0xFEE00000 below the kernel
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mov edi, kernel_start - 0x1000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, 0xFEE00000 ; LAPIC base address
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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.unsupported:
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pop edx
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pop ecx
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pop ebx
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pop eax
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ret
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cpu_init:
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mov eax, cr0
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; enable caching, disable paging and fpu emulation
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@ -182,112 +235,30 @@ stublet:
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push ebx
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; initialize cpu features
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call cpu_init
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; do we have the instruction cpuid?
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pushfd
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pop eax
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mov ecx, eax
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xor eax, 1 << 21
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push eax
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popfd
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pushfd
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pop eax
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push ecx
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popfd
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xor eax, ecx
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jz Linvalid
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; cpuid > 0x80000000?
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb Linvalid ; It is less, there is no long mode.
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; do we have a long mode?
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mov eax, 0x80000001
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cpuid
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test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
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jz Linvalid ; They aren't, there is no long mode.
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; check if longmode is supported
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call check_longmode
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; check if lapic is available
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call check_lapic
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; initialize page table
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mov edi, boot_pml4
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mov cr3, edi
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; So lets make PML4T[0] point to the PDPT and so on:
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mov DWORD [edi], boot_pdpt ; Set the double word at the destination index to pdpt.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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mov edi, boot_pdpt
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mov DWORD [edi], boot_pd ; Set the double word at the destination index to pd.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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mov edi, boot_pd
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mov ebx, boot_pt
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mov ecx, NOPTS
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L0:
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mov DWORD [edi], ebx ; Set the double word at the destination index to pt.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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add edi, 8
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add ebx, 0x1000
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loop L0
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%ifdef CONFIG_VGA
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; map the VGA address into the virtual address space
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mov edi, 0xB8000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, 0xB8000
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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%endif
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; map multiboot structure into the virtual address space
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mov edi, [esp]
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and edi, 0xFFFFF000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, [esp]
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and ebx, 0xFFFFF000
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or ebx, 0x00000003
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mov DWORD [edi], ebx
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; check if lapic is available
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push eax
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push ebx
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push ecx
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push edx
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mov eax, 1
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cpuid
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and edx, 0x200
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cmp edx, 0
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je no_lapic
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; map lapic at 0xFEE00000 below the kernel
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mov edi, kernel_start - 0x1000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, 0xFEE00000
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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no_lapic:
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pop edx
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pop ecx
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pop ebx
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pop eax
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; search APIC
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; find MP Floating Pointer Structure
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push DWORD 0x100000
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push DWORD 0xF0000
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call search_apic
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call search_mps
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add esp, 8
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cmp eax, 0
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jne La
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jne map_mps
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push DWORD 0xA0000
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push DWORD 0x9F000
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call search_apic
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call search_mps
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add esp, 8
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cmp eax, 0
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je Lb
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La:
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; map MP Floating Pointer Structure
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cmp eax, 0
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je map_kernel
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map_mps:
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; map MP Floating Pointer Structure
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mov DWORD [apic_mp], eax
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mov edi, eax
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and edi, 0xFFFFF000
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@ -298,7 +269,7 @@ La:
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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; map mp_config
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; map mp_config
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mov edi, [eax+4]
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and edi, 0xFFFFF000
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shr edi, 9 ; (edi >> 12) * 8
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@ -308,7 +279,27 @@ La:
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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Lb:
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%ifdef CONFIG_VGA
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map_vga:
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mov edi, 0xB8000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, 0xB8000
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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%endif
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map_multiboot:
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mov edi, [esp]
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and edi, 0xFFFFF000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, [esp]
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and ebx, 0xFFFFF000
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or ebx, 0x00000003
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mov DWORD [edi], ebx
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map_kernel:
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mov edi, kernel_start
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shr edi, 9 ; (kernel_start >> 12) * 8
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add edi, boot_pt
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@ -319,18 +310,37 @@ Lb:
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shr ecx, 12
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inc ecx
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Lc:
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mov DWORD [edi], ebx ; Set the double word at the destination index to the B-register.
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.l1:
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mov DWORD [edi], ebx ; Set the double word at the destination index to the B-register.
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add edi, 8
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add ebx, 0x1000
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loop Lc
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loop .l1
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; we need to enable PAE modus
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init_paging:
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mov edi, boot_pml4
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mov cr3, edi
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; So lets make PML4T[0] point to the PDPT and so on:
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mov DWORD [edi], boot_pdpt ; Set the double word at the destination index to pdpt.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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mov edi, boot_pdpt
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mov DWORD [edi], boot_pd ; Set the double word at the destination index to pd.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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mov edi, boot_pd
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mov ebx, boot_pt
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mov ecx, MAP_ENTRIES
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.l1:
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mov DWORD [edi], ebx ; Set the double word at the destination index to pt.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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add edi, 8
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add ebx, 0x1000
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loop .l1
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; enable PAE
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; switch to the compatibility mode (which is part of long mode)
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; enable longmode (compatibility mode)
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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@ -341,13 +351,11 @@ Lc:
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or eax, 1 << 31 | 1 << 0 ; Set the PG-bit, which is the 31nd bit, and the PE-bit, which is the 0th bit.
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mov cr0, eax
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; jump to 64-bit longmode
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pop ebx ; restore pointer to multiboot structure
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lgdt [GDT64.Pointer] ; Load the 64-bit global descriptor table.
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jmp GDT64.Code:start64 ; Set the code segment and enter 64-bit long mode.
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Linvalid:
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jmp $
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[BITS 64]
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start64:
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; initialize segment registers
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