diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 2cb343e3..2bbc2855 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -33,14 +33,6 @@
 #include <asm/idt.h>
 #include <asm/isrs.h>
 #include <asm/apic.h>
-#include <asm/RCCE.h>
-
-#define FPGA_BASE 0xf9000000
-#define IRQ_STATUS				0xD000
-#define IRQ_MASK				0xD200
-#define IRQ_RESET				0xD400
-#define IRQ_REQUEST				0xD600
-#define IRQ_CONFIG				0xD800
 
 /* 
  * These are our own ISRs that point to our special IRQ handler
@@ -244,25 +236,8 @@ void irq_handler(struct state *s)
 
 	// at first, we check our work queues
 	if( s->int_no == 124 ) {	
-		int my_ue = RCCE_ue();
 		kprintf( "hello from rem_interrupt\n" );
 		check_workqueues();
-	
-		/* determine interrupt source */
-		int i ;
-		volatile uint64_t* irq_status = (volatile uint64_t*)(FPGA_BASE + IRQ_STATUS + my_ue*8);
-		for( i=0; i<100; ++i) kprintf( "test" );
-		irq_status = (volatile uint64_t*)(FPGA_BASE + IRQ_STATUS + my_ue*8);
-		kprintf( "my_ue = %d\n", my_ue );
-		kprintf( "irq_status_addr: %x\n", irq_status );
-		kprintf( "irq_status: %x\n", *irq_status );
-
-		/* reset status register */
-		volatile uint64_t* irq_reset = (volatile uint64_t*)(FPGA_BASE + IRQ_RESET + my_ue*8);
-		*irq_reset = ~(0);
-
-		kprintf( "irq_status: %x\n", *irq_status );
-
 	}
 
 	/* 
diff --git a/arch/x86/scc/icc.c b/arch/x86/scc/icc.c
index a55c4cd8..50d60dcd 100644
--- a/arch/x86/scc/icc.c
+++ b/arch/x86/scc/icc.c
@@ -230,8 +230,6 @@ int icc_send_gic_irq(int core_num) {
 	volatile uint64_t* irq_request = (volatile uint64_t*)(FPGA_BASE+IRQ_REQUEST+my_ue*8);
 	uint64_t bit_pos;
 
-	kprintf( "sizeof(unint64_t) = %d\n", sizeof(uint64_t) );
-
 	// determine bit position and set according bit
 	bit_pos = (1 << core_num);
 	kprintf( "bit_pos = 0x%x\n", bit_pos );
@@ -458,12 +456,44 @@ int icc_mail_noise() {
 
 void icc_mail_check(void)
 {
-	iRCCE_MAIL_HEADER* header = NULL;
+	//iRCCE_MAIL_HEADER* header	= NULL;
+	int source, i;
+	volatile uint64_t* irq_status_reg	= NULL; 
+	volatile uint64_t* irq_reset_reg 	= NULL;
+	uint64_t irq_status			= 0;
+
+	/* print status information */
+	kprintf( "my_ue = %d\n", my_ue );
+	kprintf( "irq_status_addr: %x\n", irq_status );
+	
+	for( i=0; i<2; ++i ) {
+		/* read status register */
+		irq_status_reg = (volatile uint64_t*)(FPGA_BASE + IRQ_STATUS + my_ue*8);
+		irq_status = *irq_status_reg;
+		kprintf( "irq_status: %x\n", irq_status );
+		
+		/* determine interrupt sources */
+		for( source = 0; irq_status != 0; irq_status >>= 1, ++source ) {
+			if( irq_status & 0x1 ) {
+				kprintf( "check mail for source %d\n", source );
+			}
+		} 
+	}	
+
+	/* reset status register */
+	irq_reset_reg = (volatile uint64_t*)(FPGA_BASE + IRQ_RESET + my_ue*8);
+	*irq_reset_reg = ~(0);
+
+	kprintf( "irq_status: %x\n", *irq_status_reg );
+
+
+/*
 	int res;
 	while( (res = iRCCE_mail_recv(&header)) == iRCCE_SUCCESS ) {
 		icc_mail_check_tag(header);
 		iRCCE_mail_release( &header );
 	}
+	*/
 }
 
 #endif