From 6995bb29e31480ccf9c7497c93f1d5fb01d0a147 Mon Sep 17 00:00:00 2001 From: Generic account for RWTHAachen Students Date: Wed, 10 Aug 2011 22:44:16 -0700 Subject: [PATCH] gic irqs seem to work now --- arch/x86/kernel/irq.c | 25 +++++++++++++++---------- arch/x86/scc/icc.c | 41 ++++++++++++++++------------------------- 2 files changed, 31 insertions(+), 35 deletions(-) diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index e75b2a75..2cb343e3 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -42,8 +42,6 @@ #define IRQ_REQUEST 0xD600 #define IRQ_CONFIG 0xD800 -static int my_ue; - /* * These are our own ISRs that point to our special IRQ handler * instead of the regular 'fault_handler' function @@ -220,8 +218,6 @@ int irq_init(void) isrs_install(); irq_install(); - my_ue = RCCE_ue(); - return 0; } @@ -246,18 +242,27 @@ void irq_handler(struct state *s) /* This is a blank function pointer */ void (*handler) (struct state * s); - if( s->int_no != 123 ) kprintf( "irq_num = %d\n", s->int_no ); - // at first, we check our work queues if( s->int_no == 124 ) { + int my_ue = RCCE_ue(); kprintf( "hello from rem_interrupt\n" ); check_workqueues(); /* determine interrupt source */ - volatile int* irq_status = (volatile int*)(FPGA_BASE + IRQ_STATUS + my_ue*8); - kprintf( "irq_status_1: %x\n", *irq_status ); - irq_status += 4; - kprintf( "irq_status_2: %x\n", *irq_status ); + int i ; + volatile uint64_t* irq_status = (volatile uint64_t*)(FPGA_BASE + IRQ_STATUS + my_ue*8); + for( i=0; i<100; ++i) kprintf( "test" ); + irq_status = (volatile uint64_t*)(FPGA_BASE + IRQ_STATUS + my_ue*8); + kprintf( "my_ue = %d\n", my_ue ); + kprintf( "irq_status_addr: %x\n", irq_status ); + kprintf( "irq_status: %x\n", *irq_status ); + + /* reset status register */ + volatile uint64_t* irq_reset = (volatile uint64_t*)(FPGA_BASE + IRQ_RESET + my_ue*8); + *irq_reset = ~(0); + + kprintf( "irq_status: %x\n", *irq_status ); + } /* diff --git a/arch/x86/scc/icc.c b/arch/x86/scc/icc.c index 578ca657..a55c4cd8 100644 --- a/arch/x86/scc/icc.c +++ b/arch/x86/scc/icc.c @@ -97,7 +97,7 @@ int icc_init(void) { int i, z, tmp; uint64_t start, end, ticks, freq = 533; - uint32_t cr4, msg = 0; + uint32_t cr4; kputs("Initialize Rock Creek!\n"); @@ -172,16 +172,12 @@ int icc_init(void) // unmask interrupts - volatile int* irq_mask = (volatile int*)(FPGA_BASE + IRQ_MASK + my_ue*8); - *irq_mask &= 0; - irq_mask += 4; + volatile uint64_t* irq_mask = (volatile uint64_t*)(FPGA_BASE + IRQ_MASK + my_ue*8); *irq_mask &= 0; // reset interrupt reg - volatile int* irq_reset = (volatile int*)(FPGA_BASE + IRQ_RESET + my_ue*8); - *irq_reset = 0xffff; - irq_reset += 4; - *irq_reset = 0xffff; + volatile uint64_t* irq_reset = (volatile uint64_t*)(FPGA_BASE + IRQ_RESET + my_ue*8); + *irq_reset = ~(0); // set remote interrupts to LINT 0 volatile int* irq_config = (volatile int*)(FPGA_BASE + IRQ_CONFIG + my_ue*4); @@ -230,21 +226,17 @@ int icc_halt(void) #define CORE_B 4 // receiver -int icc_send_spec_irq(int core_num) { - volatile int* addr = (volatile int*)(FPGA_BASE+IRQ_REQUEST+8*core_num); - unsigned int bit_pos; - // determine bit position and set according bit - if( my_ue < 32 ) { - bit_pos = 1 << my_ue; - } - else { - bit_pos = 1 << (my_ue - 32); - } - - bit_pos = 0x8001; - kprintf( "bit_pos = 0x%x\n", bit_pos ); +int icc_send_gic_irq(int core_num) { + volatile uint64_t* irq_request = (volatile uint64_t*)(FPGA_BASE+IRQ_REQUEST+my_ue*8); + uint64_t bit_pos; - *addr = bit_pos; + kprintf( "sizeof(unint64_t) = %d\n", sizeof(uint64_t) ); + + // determine bit position and set according bit + bit_pos = (1 << core_num); + kprintf( "bit_pos = 0x%x\n", bit_pos ); + kprintf( "irq_req_addr = %x\n", irq_request ); + *irq_request = bit_pos; return 0; } @@ -252,9 +244,8 @@ int icc_send_spec_irq(int core_num) { int icc_irq_ping() { - if( my_ue != 0 ) return -1; - - icc_send_spec_irq(1); + if( my_ue == 2 ) return -1 ; + icc_send_gic_irq(2); kprintf( "my_ue = %d\n", my_ue ); kprintf( "sending irq to 1!\n"); return 0;