- set correct task flag

- cosmetical changes

apps/tests.c

@@ -17,8 +17,6 @@
  * This file is part of MetalSVM. 
  */
 
-//#define SVM_WB
-
 #include <metalsvm/stddef.h>
 #include <metalsvm/stdio.h>
 #include <metalsvm/time.h>
@@ -114,8 +112,9 @@ static int mail_noise(void*arg) {
 	return 0;
 }
 
-#define N	1024
+//#define N	1024
-//#define N 	514
+//#define N 	512
+#define N	128
 #define LAZY
 #define L2_ENABLE
 
@@ -193,9 +192,13 @@ static int svm_test(void *arg)
 
 #ifdef LAZY
 	svm_flags = SVM_LAZYRELEASE;
+	kputs("Use Lazy Release consistency!\n");	
+#else
+	kputs("Use Strong Release consistency!\n");
 #endif
 
 #ifdef L2_ENABLE
+	kputs("Use Level 2 Cache!\n");
 	svm_flags |= SVM_L2;
 #endif
 

arch/x86/mm/page.c

@@ -784,7 +784,7 @@ int arch_paging_init(void)
 	kprintf("Map configuration registers at 0x%x\n", viraddr);
 
 	// map SCC's message passing buffers
-	viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+16*1024*1024) >> PAGE_SHIFT, MAP_KERNEL_SPACE|MAP_MPE);
+	viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+64*1024*1024) >> PAGE_SHIFT, MAP_KERNEL_SPACE|MAP_MPE);
 	kprintf("Map message passing buffers at 0x%x\n", viraddr);
 
 	// map the FPGA registers

arch/x86/mm/svm.c

@@ -167,12 +167,15 @@ static atomic_int32_t size_counter = ATOMIC_INIT(0);
 
 void* svmmalloc(size_t size, uint32_t consistency)
 {
+	task_t* task = per_core(current_task);
 	size_t phyaddr, viraddr, i;
 	uint32_t flags;
 	uint32_t map_flags = MAP_KERNEL_SPACE;
 
 	if( !(consistency & SVM_L2) )
 		map_flags |= MAP_MPE;
+	else
+		task->flags |= TASK_L2;
 
 	if (consistency & SVM_STRONG)
 		map_flags |= MAP_SVM_STRONG;
@@ -319,7 +322,8 @@ int svm_emit_page(size_t phyaddr, int ue)
 	} else {
 		size_t viraddr;
 
-		svm_flush(phyaddr);
+		svm_flush(0);
+		//svm_flush(phyaddr);
 		page_owner[pageid] = ue;
 
 		emit[ue]++;
@@ -367,10 +371,8 @@ void svm_flush( size_t phyaddr )
 
 	size_t step = 0;
 	size_t stride = L2_LINESIZE;
-	size_t range;
+	size_t range = L2_WBSTRIDE;
 
-	size_t dummy;
-	
 	size_t viraddr;
 
 	uint32_t index1, index2;
@@ -380,7 +382,6 @@ void svm_flush( size_t phyaddr )
 	/* flush entire Cache if phyaddr == 0 */
 	if(!phyaddr) {
 		if( task->flags & TASK_L2 ){
-			range = L2_WBSTRIDE;
 			goto flush_l2;
 		} else {
 			goto flush_l1;
@@ -404,6 +405,7 @@ void svm_flush( size_t phyaddr )
 		if( pgt->entries[index2] & PG_MPE ) {
 			goto flush_l1;
 		} else {
+			phyaddr = phyaddr % L2_WBSTRIDE;
 			range = PAGE_SIZE;
 			goto flush_l2;
 		}
@@ -414,8 +416,9 @@ void svm_flush( size_t phyaddr )
 	 */
 
 flush_l1:
-
+	kputs("flush L1\n");
 	*(int *)RCCE_fool_write_combine_buffer = 1;
+	//__asm__ volatile ( "wbinvd;\n\t" );
 	flush_cache();
 	return;
 
@@ -424,17 +427,18 @@ flush_l2:
 	 *  FLUSH L2 CACHE:
 	 *  disable iterrupts due to pseudo LRU behavior of L2 cache
 	 */
-
+	flags = irq_nested_disable();
 	/* toggle between dummy areas */
-	dummy = dummy_base + dummy_offset;
+	phyaddr += dummy_base + dummy_offset;
+	kprintf("flush-l2: phyaddr 0x%x\n", phyaddr);
 	if(dummy_offset)
 		dummy_offset = 0;
 	else
 		dummy_offset = L2_CAPACITY;
 	
-	flags = irq_nested_disable();
+	flush_cache();
 	for( step = 0; step < range; step += stride )
-		svm_purge_set( ( ( phyaddr + step ) % L2_WBSTRIDE ) + dummy );
+		svm_purge_set( phyaddr + step );
 	irq_nested_enable(flags);
 	return;