only check irq status reg if irq_no = 124
This commit is contained in:
parent
f7be10461b
commit
7bf0cf184c
4 changed files with 50 additions and 32 deletions
|
@ -54,7 +54,7 @@ enum icc_mail_requests {
|
|||
int icc_init(void);
|
||||
int icc_halt(void);
|
||||
int icc_send_irq(int ue);
|
||||
void icc_mail_check(void);
|
||||
void icc_mail_check(int irq);
|
||||
int icc_mail_ping(void);
|
||||
int icc_irq_ping(void);
|
||||
int icc_mail_ping_irq(void);
|
||||
|
|
|
@ -234,10 +234,13 @@ void irq_handler(struct state *s)
|
|||
/* This is a blank function pointer */
|
||||
void (*handler) (struct state * s);
|
||||
|
||||
// at first, we check our work queues
|
||||
// if( s->int_no == 124 ) {
|
||||
// evaluate only irq status register if int_no = 124
|
||||
if( s->int_no == 124 ) {
|
||||
check_workqueues_rem_irq();
|
||||
}
|
||||
else {
|
||||
check_workqueues();
|
||||
// }
|
||||
}
|
||||
|
||||
/*
|
||||
* Find out if we have a custom handler to run for this
|
||||
|
|
|
@ -215,15 +215,15 @@ int icc_send_irq(int ue)
|
|||
|
||||
int icc_halt(void)
|
||||
{
|
||||
icc_mail_check();
|
||||
icc_mail_check(0);
|
||||
HALT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define ROUNDS 1000
|
||||
#define CORE_A 1 // sender
|
||||
#define CORE_B 4 // receiver
|
||||
#define ROUNDS 100000
|
||||
#define CORE_A 0 // sender
|
||||
#define CORE_B 10 // receiver
|
||||
|
||||
|
||||
int icc_send_gic_irq(int core_num) {
|
||||
|
@ -348,7 +348,7 @@ int icc_mail_ping( void )
|
|||
|
||||
int icc_mail_ping_irq( void )
|
||||
{
|
||||
/* return if not core 0 */
|
||||
/* return if not core A */
|
||||
if( my_ue != CORE_A ) return 0;
|
||||
|
||||
uint32_t flags;
|
||||
|
@ -379,7 +379,11 @@ int icc_mail_ping_irq( void )
|
|||
} while( res != iRCCE_SUCCESS );
|
||||
|
||||
/* release mail */
|
||||
iRCCE_mail_recv(&recv_header);
|
||||
do {
|
||||
if( recv_header ) iRCCE_mail_release(&recv_header);
|
||||
res = iRCCE_mail_recv(&recv_header);
|
||||
} while( (recv_header->source != rem_rank)
|
||||
&& (recv_header->tag == PING_RESP) );
|
||||
iRCCE_mail_release(&recv_header);
|
||||
|
||||
/* start timer in first round */
|
||||
|
@ -415,8 +419,8 @@ int icc_mail_noise() {
|
|||
for( ;; ) {
|
||||
/* send a mail to each UE */
|
||||
for( j=0; j<num_ranks; ++j ) {
|
||||
if( (j == CORE_A) || (j == CORE_B) )
|
||||
continue;
|
||||
// if( (j == CORE_A) || (j == CORE_B) )
|
||||
// continue;
|
||||
|
||||
/* recv mails */
|
||||
iRCCE_mail_check(iRCCE_MAILBOX_ALL);
|
||||
|
@ -443,42 +447,47 @@ int icc_mail_noise() {
|
|||
return 0;
|
||||
}
|
||||
|
||||
void icc_mail_check(void)
|
||||
/*
|
||||
* Routine to check mailboxes. If irq = 1 is passed only those boxes are checked that
|
||||
* refere to the cores with set bit in status register.
|
||||
*
|
||||
*/
|
||||
|
||||
void icc_mail_check(int irq)
|
||||
{
|
||||
iRCCE_MAIL_HEADER* header = NULL;
|
||||
int source, i, res;
|
||||
volatile uint64_t* irq_status_reg = NULL;
|
||||
volatile uint64_t* irq_reset_reg = NULL;
|
||||
uint64_t irq_status = 0;
|
||||
uint64_t source_pos;
|
||||
uint32_t flags;
|
||||
|
||||
/* print status information */
|
||||
// kprintf( "my_ue = %d\n", my_ue );
|
||||
// kprintf( "irq_status_addr: %x\n", irq_status_reg );
|
||||
|
||||
/* disable interrupts */
|
||||
flags = irq_nested_disable();
|
||||
|
||||
/* read status register */
|
||||
irq_status_reg = (volatile uint64_t*)(FPGA_BASE + IRQ_STATUS + my_ue*8);
|
||||
irq_status = *irq_status_reg;
|
||||
if( irq == 1 ) {
|
||||
/* read status register */
|
||||
irq_status_reg = (volatile uint64_t*)(FPGA_BASE + IRQ_STATUS + my_ue*8);
|
||||
irq_status = *irq_status_reg;
|
||||
|
||||
|
||||
/* determine interrupt sources */
|
||||
irq_status >>= 6; // shift emac bits
|
||||
/* determine interrupt sources */
|
||||
irq_status >>= 6; // shift emac bits
|
||||
|
||||
for( source = 0; irq_status != 0; irq_status >>= 1, ++source ) {
|
||||
if( (irq_status & 0x1) != 0 ) {
|
||||
res = iRCCE_mail_check(source);
|
||||
for( source = 0; irq_status != 0; irq_status >>= 1, ++source ) {
|
||||
if( (irq_status & 0x1) != 0 ) {
|
||||
res = iRCCE_mail_check(source);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* reset status register */
|
||||
irq_reset_reg = (volatile uint64_t*)(FPGA_BASE + IRQ_RESET + my_ue*8);
|
||||
*irq_reset_reg = ~(0);
|
||||
|
||||
/* reset status register */
|
||||
irq_reset_reg = (volatile uint64_t*)(FPGA_BASE + IRQ_RESET + my_ue*8);
|
||||
*irq_reset_reg = ~(0);
|
||||
}
|
||||
else {
|
||||
iRCCE_mail_check(iRCCE_MAILBOX_ALL);
|
||||
}
|
||||
|
||||
/* empty mail queue */
|
||||
while( (res = iRCCE_mail_recv(&header)) == iRCCE_SUCCESS ) {
|
||||
|
|
|
@ -141,10 +141,16 @@ int sys_execve(const char* fname, char** argv, char** env);
|
|||
static inline void check_workqueues(void)
|
||||
{
|
||||
#ifdef CONFIG_ROCKCREEK
|
||||
icc_mail_check();
|
||||
icc_mail_check(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void check_workqueues_rem_irq(void)
|
||||
{
|
||||
#ifdef CONFIG_ROCKCREEK
|
||||
icc_mail_check(1);
|
||||
#endif
|
||||
}
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
Loading…
Add table
Reference in a new issue