diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
index 740355ed..5f0e208e 100644
--- a/arch/x86/kernel/apic.c
+++ b/arch/x86/kernel/apic.c
@@ -267,7 +267,7 @@ int apic_calibration(void)
 	while(get_clock_tick() - ticks < 3)
 		;
 
-	diff = 0xFFFFFFFF - *((uint32_t*) (lapic+APIC_CCR));
+	diff = 0xFFFFFFFF - lapic_read(APIC_CCR);
 
 	lapic_write(APIC_DCR, 0xB);		// set it to 1 clock increments
 	lapic_write(APIC_LVT_T, 0x2007B);	// connects the timer to 123 and enables it
@@ -288,6 +288,10 @@ int apic_calibration(void)
 	if (!has_apic())
 		return -ENXIO;
 
+	map_region(per_core(current_task), lapic, lapic, 1, MAP_KERNEL_SPACE|MAP_NO_CACHE);
+	if (ioapic)
+		map_region(per_core(current_task), (size_t)ioapic, (size_t)ioapic, 1, MAP_KERNEL_SPACE|MAP_NO_CACHE);
+	
 	lapic_write(APIC_DCR, 0xB);		// set it to 1 clock increments
 	lapic_write(APIC_LVT_T, 0x2007B);	// connects the timer to 123 and enables it
 	lapic_write(APIC_ICR, 0xFFFFFFFF);
@@ -300,14 +304,14 @@ int apic_calibration(void)
 		ticks = end > start ? end - start : start - end;
 	} while(ticks < 3*scc_info.tile_frequency*1000000 / TIMER_FREQ);
 
-	diff = 0xFFFFFFFF - *((uint32_t*) (lapic+APIC_CCR));
+	diff = 0xFFFFFFFF - lapic_read(APIC_CCR);
 
 	lapic_write(APIC_DCR, 0xB);		// set it to 1 clock increments
 	lapic_write(APIC_LVT_T, 0x2007B);	// connects the timer to 123 and enables it
 	lapic_write(APIC_ICR, diff / 3);
 #endif
 
-	kprintf("APIC calibration detects an ICR of 0x%x\n", diff / 3);
+	kprintf("APIC calibration determines an ICR of 0x%x\n", diff / 3);
 
 	irq_disable();
 #if MAX_CORES > 1