add MSR and X2APIC support
This commit is contained in:
Stefan Lankes
parent
e0a112bc2a
commit
84945aee64
4 changed files with 112 additions and 52 deletions
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@ -191,7 +191,6 @@ int apic_init(void);
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void apic_eoi(void);
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uint32_t apic_cpu_id(void);
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int apic_calibration(void);
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int has_apic(void);
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int apic_is_enabled(void);
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int apic_enable_timer(void);
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int apic_disable_timer(void);
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@ -41,13 +41,17 @@ extern "C" {
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// feature list 1
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#define CPU_FEATURE_FPU (1 << 0)
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#define CPU_FEATURE_MSR (1 << 5)
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#define CPU_FEATURE_APIC (1 << 9)
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#define CPU_FEATURE_MMX (1 << 23)
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#define CPU_FEATURE_FXSR (1 << 24)
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#define CPU_FEATURE_SSE (1 << 25)
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#define CPU_FEATURE_SSE2 (1 << 26)
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// feature list 2
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#define CPU_FEATURE_X2APIC (1 << 21)
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#define CPU_FEATURE_AVX (1 << 28)
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#define CPU_FEATURE_HYPERVISOR (1 << 31)
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typedef struct {
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uint32_t feature1, feature2;
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@ -63,6 +67,16 @@ inline static uint32_t has_fpu(void)
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return (cpu_info.feature1 & CPU_FEATURE_FPU);
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}
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inline static uint32_t has_msr(void)
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{
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return (cpu_info.feature1 & CPU_FEATURE_MSR);
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}
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inline static uint32_t has_apic(void)
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{
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return (cpu_info.feature1 & CPU_FEATURE_APIC);
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}
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inline static uint32_t has_fxsr(void)
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{
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return (cpu_info.feature1 & CPU_FEATURE_FXSR);
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@ -78,11 +92,21 @@ inline static uint32_t has_sse2(void)
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return (cpu_info.feature1 & CPU_FEATURE_SSE2);
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}
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inline static uint32_t has_x2apic(void)
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{
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return (cpu_info.feature2 & CPU_FEATURE_X2APIC);
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}
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inline static uint32_t has_avx(void)
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{
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return (cpu_info.feature2 & CPU_FEATURE_AVX);
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}
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inline static uint32_t on_hypervisor(void)
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{
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return (cpu_info.feature2 & CPU_FEATURE_HYPERVISOR);
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}
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/** @brief Read out time stamp counter
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*
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* The rdtsc asm command puts a 64 bit time stamp value
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@ -171,6 +195,22 @@ inline static uint64_t rdmsr(uint32_t msr) {
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return ((uint64_t)high << 32) | low;
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}
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/** @brief Write a value to a Machine-Specific Registers (MSR)
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*
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* The asm instruction wrmsr which stands for "Write to model specific register"
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* is used here.
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*
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* @param msr The MSR identifier
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* @param value Value, which will be store in the MSR
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*/
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inline static void wrmsr(uint32_t msr, uint64_t value)
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{
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uint32_t low = value & 0xFFFFFFFF;
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uint32_t high = value >> 32;
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asm volatile("wrmsr" :: "a"(low), "c"(msr), "d"(high));
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}
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/** @brief Read cr0 register
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* @return cr0's value
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*/
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@ -335,11 +375,11 @@ static inline size_t lsb(size_t i)
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inline static int system_init(void)
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{
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gdt_install();
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cpu_detection();
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apic_init();
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#ifdef CONFIG_PCI
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pci_init();
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#endif
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cpu_detection();
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return 0;
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}
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@ -78,12 +78,21 @@ spinlock_t bootlock = SPINLOCK_INIT;
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// forward declaration
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static int lapic_reset(void);
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static inline uint32_t lapic_read(uint32_t addr)
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static uint32_t lapic_read_default(uint32_t addr)
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{
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return *((volatile uint32_t*) (lapic+addr));
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}
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static inline void lapic_write(uint32_t addr, uint32_t value)
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static uint32_t lapic_read_msr(uint32_t addr)
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{
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return rdmsr(0x800 + (addr >> 4));
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}
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typedef uint32_t (*lapic_read_func)(uint32_t addr);
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static lapic_read_func lapic_read = lapic_read_default;
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static void lapic_write_default(uint32_t addr, uint32_t value)
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{
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#ifdef CONFIG_X86_32
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/*
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@ -96,6 +105,15 @@ static inline void lapic_write(uint32_t addr, uint32_t value)
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#endif
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}
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static void lapic_write_msr(uint32_t addr, uint32_t value)
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{
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wrmsr(0x800 + (addr >> 4), value);
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}
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typedef void (*lapic_write_func)(uint32_t addr, uint32_t value);
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static lapic_write_func lapic_write = lapic_write_default;
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static inline uint32_t ioapic_read(uint32_t reg)
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{
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ioapic->reg = reg;
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@ -147,11 +165,6 @@ static inline uint32_t apic_lvt_entries(void)
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return 0;
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}
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int has_apic(void)
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{
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return (lapic != 0);
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}
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int apic_is_enabled(void)
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{
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return (lapic && initialized);
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@ -355,11 +368,14 @@ void smp_start(uint32_t id)
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i = read_cr0();
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i = i | (1 << 31);
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write_cr0(i);
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#endif
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if (lapic && has_x2apic()) // enable x2APIC support
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wrmsr(0x1B, lapic | 0xC00);
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// reset APIC and set id
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lapic_reset(); // sets also the timer interrupt
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apic_set_cpu_id(id);
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#endif
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/*
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* we turned on paging
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@ -498,7 +514,7 @@ int map_apic(void)
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{
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uint32_t i;
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if (!has_apic())
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if (!lapic)
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return -ENXIO;
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#ifdef CONFIG_X86_32
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@ -507,6 +523,7 @@ int map_apic(void)
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return -ENXIO;
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#else
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if (lapic != (size_t)&kernel_start - 0x1000) {
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kprintf("Upps! Kernel has to remap LAPIC!\n");
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lapic = map_region(0 /*lapic*/, lapic, 1, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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if (BUILTIN_EXPECT(!lapic, 0))
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return -ENXIO;
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@ -540,13 +557,11 @@ int apic_calibration(void)
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uint32_t flags;
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#ifndef CONFIG_ROCKCREEK
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uint64_t ticks, old;
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uint32_t diff;
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#else
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uint64_t start, end, ticks;
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uint32_t diff;
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#endif
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if (!has_apic())
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if (!lapic)
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return -ENXIO;
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#ifndef CONFIG_ROCKCREEK
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@ -566,8 +581,7 @@ int apic_calibration(void)
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while(get_clock_tick() - ticks < 3)
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HALT;
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diff = 0xFFFFFFFFUL - lapic_read(APIC_CCR);
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icr = diff / 3;
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icr = (0xFFFFFFFFUL - lapic_read(APIC_CCR)) / 3;
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flags = irq_nested_disable();
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lapic_reset();
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@ -597,8 +611,7 @@ int apic_calibration(void)
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ticks = end > start ? end - start : start - end;
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} while(ticks*TIMER_FREQ < 3*RC_REFCLOCKMHZ*1000000UL);
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diff = 0xFFFFFFFFUL - lapic_read(APIC_CCR);
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icr = diff / 3;
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icr = (0xFFFFFFFFUL - lapic_read(APIC_CCR)) / 3;
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lapic_reset();
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@ -755,39 +768,26 @@ found_mp:
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ncores = count;
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check_lapic:
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#ifdef CONFIG_X86_32
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if (apic_config) {
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if (apic_config)
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lapic = apic_config->lapic;
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} else {
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uint32_t edx, dummy=0;
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cpuid(0x1, &dummy, &dummy, &dummy, &edx);
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if (edx & (1 << 9))
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lapic = 0xFEE00000;
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}
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#else
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if (apic_config) {
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if (apic_config->lapic == 0xFEE00000) {
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// On a x64 system, we already map the lapic below the kernel
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lapic = (size_t)&kernel_start - 0x1000;
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} else {
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lapic = apic_config->lapic;
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}
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} else {
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uint32_t edx, dummy=0;
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cpuid(0x1, &dummy, &dummy, &dummy, &edx);
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if (edx & (1 << 9)) {
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// On a x64 system, we already map the lapic below the kernel
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lapic = (size_t)&kernel_start - 0x1000;
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}
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}
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#endif
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else if (has_apic())
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lapic = 0xFEE00000;
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if (!lapic)
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goto out;
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if (has_x2apic()) {
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kprintf("Enable X2APIC support!\n");
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wrmsr(0x1B, lapic | 0xD00);
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lapic_read = lapic_read_msr;
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lapic_write = lapic_write_msr;
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}
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kprintf("Found APIC at 0x%x\n", lapic);
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#ifdef CONFIG_X86_64
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// On a x64 system, we already map the lapic below the kernel
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lapic = (size_t)&kernel_start - 0x1000;
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#endif
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kprintf("Maximum LVT Entry: 0x%x\n", apic_lvt_entries());
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kprintf("APIC Version: 0x%x\n", apic_version());
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@ -92,8 +92,12 @@ int cpu_detection(void)
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{
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uint32_t a, b;
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size_t cr4;
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uint8_t first_time = 0;
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cpuid(1, &a, &b, &cpu_info.feature2, &cpu_info.feature1);
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if (!cpu_info.feature1) {
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first_time = 1;
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cpuid(1, &a, &b, &cpu_info.feature2, &cpu_info.feature1);
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}
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cr4 = read_cr4();
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if (has_fxsr())
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@ -102,28 +106,45 @@ int cpu_detection(void)
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cr4 |= 0x400; // set the OSXMMEXCPT bit
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write_cr4(cr4);
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if (has_sse())
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if (first_time && has_sse())
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wmb = sfence;
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if (has_sse2()) {
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if (first_time && has_sse2()) {
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rmb = lfence;
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mb = mfence;
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}
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if (has_avx())
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if (first_time && has_avx())
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kprintf("The CPU owns the Advanced Vector Extensions (AVX). However, MetalSVM doesn't support AVX!\n");
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if (has_fpu()) {
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kputs("Found and initialized FPU!\n");
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if (first_time)
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kputs("Found and initialized FPU!\n");
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asm volatile ("fninit");
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}
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if (has_fxsr()) {
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if (first_time && has_fxsr()) {
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save_fpu_state = save_fpu_state_fxsr;
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restore_fpu_state = restore_fpu_state_fxsr;
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fpu_init = fpu_init_fxsr;
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}
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if (first_time && on_hypervisor()) {
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uint32_t c, d;
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char vendor_id[13];
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kprintf("MetalSVM is running on a hypervisor!\n");
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cpuid(0x40000000, &a, &b, &c, &d);
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memcpy(vendor_id, &b, 4);
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memcpy(vendor_id+4, &c, 4);
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memcpy(vendor_id+8, &d, 4);
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vendor_id[12] = '\0';
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kprintf("Hypervisor Vendor Id: %s\n", vendor_id);
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kprintf("Maximum input value for hypervisor CPUID info: 0x%x\n", a);
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}
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return 0;
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}
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