fix bug in the determination of the link speed
This commit is contained in:
Stefan Lankes
parent
e2550fbdb2
commit
9575ffb769
2 changed files with 73 additions and 15 deletions
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@ -38,7 +38,7 @@
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#define RX_BUF_LEN (2048)
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#define TX_BUF_LEN (1792)
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#define INT_MASK (E1000_IMS_RXO|E1000_IMS_RXT0|E1000_IMS_RXDMT0|E1000_IMS_RXSEQ|E1000_IMS_LSC)
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#define INT_MASK (E1000_ICR_TXDW|E1000_ICR_TXQE|E1000_IMS_RXO|E1000_IMS_RXT0|E1000_IMS_RXDMT0|E1000_IMS_RXSEQ|E1000_IMS_LSC)
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#define INT_MASK_NO_RX (E1000_IMS_LSC)
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typedef struct {
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@ -353,7 +353,7 @@ err_t e1000if_init(struct netif* netif)
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pci_info_t pci_info;
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e1000if_t* e1000if = NULL;
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uint32_t tmp32;
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uint16_t tmp16, speed;
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uint16_t tmp16, speed, cold = 0x40;
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uint8_t tmp8, is64bit, mem_type, prefetch;
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static uint8_t num = 0;
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@ -400,6 +400,8 @@ err_t e1000if_init(struct netif* netif)
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// reset device
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e1000_write(e1000if->bar0, E1000_CTRL, E1000_CTRL_RST);
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e1000_flush(e1000if->bar0);
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/* Wait for reset to complete */
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udelay(10);
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e1000if->irq = pci_info.irq;
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e1000if->rx_desc = mem_allocation(NUM_RX_DESCRIPTORS*sizeof(rx_desc_t), MAP_KERNEL_SPACE|MAP_NO_CACHE);
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@ -441,6 +443,11 @@ err_t e1000if_init(struct netif* netif)
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e1000_flush(e1000if->bar0);
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kprintf("e1000if_init: Device Control Register 0x%x\n", e1000_read(e1000if->bar0, E1000_CTRL));
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/* make sure transmits are disabled while setting up the descriptors */
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tmp32 = e1000_read(e1000if->bar0, E1000_TCTL);
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e1000_write(e1000if->bar0, E1000_TCTL, tmp32 & ~E1000_TCTL_EN);
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e1000_flush(e1000if->bar0);
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// setup the transmit descriptor ring buffer
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e1000_write(e1000if->bar0, E1000_TDBAL, (uint32_t)((uint64_t)virt_to_phys((size_t)e1000if->tx_desc) & 0xFFFFFFFF));
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e1000_write(e1000if->bar0, E1000_TDBAH, (uint32_t)((uint64_t)virt_to_phys((size_t)e1000if->tx_desc) >> 32));
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@ -454,8 +461,21 @@ err_t e1000if_init(struct netif* netif)
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e1000_write(e1000if->bar0, E1000_TDT, 0);
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e1000if->tx_tail = 0;
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tmp32 = e1000_read(e1000if->bar0, E1000_STATUS);
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if (tmp32 & E1000_STATUS_SPEED_1000)
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speed = 1000;
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else if (tmp32 & E1000_STATUS_SPEED_100)
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speed = 100;
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else
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speed = 10;
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if ((!(tmp32 & E1000_STATUS_FD)) && (speed == 1000))
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cold = 0x200;
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LWIP_DEBUGF(NETIF_DEBUG, ("e1000if_init: speed = %u mbps\n", speed));
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LWIP_DEBUGF(NETIF_DEBUG, ("e1000if_init: Full-Duplex %u\n", tmp32 & E1000_STATUS_FD));
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// set the transmit control register (padshortpackets)
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e1000_write(e1000if->bar0, E1000_TCTL, (E1000_TCTL_EN | E1000_TCTL_PSP | (0x40 << 12) | (0x10 << 4)));
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e1000_write(e1000if->bar0, E1000_TCTL, (E1000_TCTL_EN | E1000_TCTL_PSP | (cold << 12) | (0x10 << 4)));
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e1000_flush(e1000if->bar0);
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// set IEEE 802.3 standard IPG value
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@ -470,6 +490,12 @@ err_t e1000if_init(struct netif* netif)
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((uint8_t*) &tmp32)[tmp8] = mynetif->hwaddr[tmp8+4];
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e1000_write(e1000if->bar0, E1000_RA+4, tmp32 | (1 << 31)); // set also AV bit to check incoming packets
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/* Zero out the other receive addresses. */
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for (tmp8=1; tmp8<16; tmp8++) {
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e1000_write(e1000if->bar0, E1000_RA+8*tmp8, 0);
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e1000_write(e1000if->bar0, E1000_RA+8*tmp8+4, 0);
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}
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LWIP_DEBUGF(NETIF_DEBUG, ("e1000if_init: MAC address "));
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tmp32 = e1000_read(e1000if->bar0, E1000_RA);
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for(tmp8=0; tmp8<4; tmp8++) {
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@ -490,6 +516,11 @@ err_t e1000if_init(struct netif* netif)
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// set IRQ handler
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irq_install_handler(e1000if->irq+32, e1000if_handler);
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/* make sure receives are disabled while setting up the descriptors */
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tmp32 = e1000_read(e1000if->bar0, E1000_RCTL);
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e1000_write(e1000if->bar0, E1000_RCTL, tmp32 & ~E1000_RCTL_EN);
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e1000_flush(e1000if->bar0);
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// clear IMS & IMC registers
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e1000_write(e1000if->bar0, E1000_IMS, 0xFFFF);
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e1000_flush(e1000if->bar0);
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@ -524,20 +555,12 @@ err_t e1000if_init(struct netif* netif)
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e1000_write(e1000if->bar0, E1000_RDT, 0);
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e1000if->rx_tail = 0;
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// set the receieve control register (promisc ON)
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e1000_write(e1000if->bar0, E1000_RCTL, (E1000_RCTL_EN|/*E1000_RCTL_LPE|*/E1000_RCTL_BAM|E1000_RCTL_SZ_2048|
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E1000_RCTL_SECRC|E1000_RCTL_RDMTS_HALF|E1000_RCTL_MO_0|E1000_RCTL_UPE|E1000_RCTL_MPE));
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// set the receieve control register
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e1000_write(e1000if->bar0, E1000_RCTL, (E1000_RCTL_EN|/*E1000_RCTL_LPE|*/E1000_RCTL_LBM_NO|E1000_RCTL_BAM|E1000_RCTL_SZ_2048|
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E1000_RCTL_SECRC|E1000_RCTL_RDMTS_HALF|E1000_RCTL_MO_0/*|E1000_RCTL_UPE|E1000_RCTL_MPE*/));
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e1000_flush(e1000if->bar0);
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tmp32 = e1000_read(e1000if->bar0, E1000_CTRL);
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if (tmp32 & E1000_CTRL_SPD_1000)
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speed = 1000;
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else if (tmp32 & E1000_CTRL_SPD_100)
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speed = 100;
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else
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speed = 10;
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LWIP_DEBUGF(NETIF_DEBUG, ("e1000if_init: speed = %u mbps\n", speed));
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LWIP_DEBUGF(NETIF_DEBUG, ("e1000if_init: status = 0x%x\n", e1000_read(e1000if->bar0, E1000_STATUS)));
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/*
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* Initialize the snmp variables and counters inside the struct netif.
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@ -35,6 +35,7 @@
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#define E1000_STATUS 0x00008 /* Device Status - RO */
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#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
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#define E1000_EERD 0x00014 /* EEPROM Read - RW */
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#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
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#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
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#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
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#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
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@ -95,6 +96,40 @@
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#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
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#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
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/* Device Status */
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#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
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#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
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#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
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#define E1000_STATUS_FUNC_SHIFT 2
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#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
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#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
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#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
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#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
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#define E1000_STATUS_SPEED_MASK 0x000000C0
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#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
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#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
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#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
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by EEPROM/Flash */
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#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
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#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
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#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
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#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
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#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
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#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
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#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
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#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
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#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
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#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
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#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
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#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
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#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
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#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
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#define E1000_STATUS_FUSE_8 0x04000000
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#define E1000_STATUS_FUSE_9 0x08000000
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#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
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#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
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/* Transmit Control */
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#define E1000_TCTL_RST 0x00000001 /* software reset */
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#define E1000_TCTL_EN 0x00000002 /* enable tx */
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