From 9918db81ec41a359db255e4511c46cb8cd06454b Mon Sep 17 00:00:00 2001 From: Stefan Lankes Date: Tue, 5 Apr 2011 01:55:02 -0700 Subject: [PATCH] fix bugs in initialization of RCCE at first, we have to enable paging and to disable caching for the configuration registers --- arch/x86/include/asm/processor.h | 19 ------- arch/x86/mm/page.c | 14 ++++++ arch/x86/scc/RCCE_admin.c | 4 +- arch/x86/scc/scc_init.c | 85 +++++++------------------------- 4 files changed, 34 insertions(+), 88 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index a8e1daaf..27294236 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -32,22 +32,6 @@ extern "C" { #endif #ifdef CONFIG_ROCKCREEK -/*#define SCC_PMEM_REGIONS 2 - -typedef struct { - uint32_t low; - uint32_t high; -} mem_region_t; - -typedef struct { - uint32_t pid; - uint32_t tile_frequency; // in MHz - uint32_t router_frequency; // in MHz - mem_region_t private_mem[SCC_PMEM_REGIONS]; -} scc_info_t; - -extern scc_info_t scc_info;*/ - int scc_init(void); #endif @@ -158,9 +142,6 @@ uint32_t read_eip(void); inline static int system_init(void) { -#ifdef CONFIG_ROCKCREEK - scc_init(); -#endif gdt_install(); apic_init(); #ifdef CONFIG_PCI diff --git a/arch/x86/mm/page.c b/arch/x86/mm/page.c index 6711bc47..114f2a66 100644 --- a/arch/x86/mm/page.c +++ b/arch/x86/mm/page.c @@ -30,6 +30,10 @@ #include #include #include +#ifdef CONFIG_ROCKCREEK +#include +#include +#endif /* * Virtual Memory Layout of the standard configuration @@ -675,6 +679,16 @@ int arch_paging_init(void) } #endif +#ifdef CONFIG_ROCKCREEK + // map SCC's configuration registers + viraddr = map_region(CRB_X0_Y0, CRB_X0_Y0, (CRB_OWN-CRB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE|MAP_NO_CACHE); + kprintf("Map configuration registers at 0x%x\n", viraddr); + + // map SCC's configuration registers + viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE); + kprintf("Map message passing buffers at 0x%x\n", viraddr); +#endif + /* enable paging */ write_cr3((uint32_t) &boot_pgd); i = read_cr0(); diff --git a/arch/x86/scc/RCCE_admin.c b/arch/x86/scc/RCCE_admin.c index 4316b216..8b4cbccc 100644 --- a/arch/x86/scc/RCCE_admin.c +++ b/arch/x86/scc/RCCE_admin.c @@ -51,7 +51,7 @@ // GLOBAL VARIABLES USED BY THE LIBRARY //...................................................................................... int RCCE_NP; // number of participating cores -int RC_REFCLOCKMHZ=533; // baseline CPU frequency (MHz) +int RC_REFCLOCKMHZ; // baseline CPU frequency (MHz) int RC_MY_COREID; // physical ID of calling core int RC_COREID[RCCE_MAXNP]; // array of physical core IDs for all participating // cores, sorted by rank @@ -232,7 +232,7 @@ int RCCE_init( unsigned int RCCE_SHM_BUFFER_offset ,result, rd_slot_nbr, wr_slot_nbr; #endif void *nothing = NULL; - + #ifdef SCC // Copperridge specific initialization... InitAPI(0); //fflush(0) diff --git a/arch/x86/scc/scc_init.c b/arch/x86/scc/scc_init.c index b3ef5cbd..0e3a2197 100644 --- a/arch/x86/scc/scc_init.c +++ b/arch/x86/scc/scc_init.c @@ -27,22 +27,23 @@ #ifdef CONFIG_ROCKCREEK -#define CCR_INTR_ACTIVE 0x02 - -//scc_info_t scc_info; -static char* rcce_argv[] = {"MetalSVM", "1", "533", "0"}; +/* + * Workaround to create a suitable argv array + */ +static char* argv_strings[] = {"MetalSVM", "1", "533", "0"}; +static char* argv[4] = {[0 ... 3] = NULL}; +static char** rcce_argv = argv; static int rcce_argc = 4; /* - * This is a modified MPB program, which is part of the RCCE distribution (src/mpb.c). + * This is the modified MPB program, which is part of the RCCE distribution (src/mpb.c). + * + * This function clears the local MPB and resets the test&set register. */ -static int scc_reset(void) +static int scc_clear(void) { int tmp, x, y, z, offset; - - // Initialize API - InitAPI(0); - + // Find out who I am... tmp=ReadConfigReg(CRB_OWN+MYTILEID); x=(tmp>>3) & 0x0f; // bits 06:03 @@ -69,14 +70,12 @@ static int scc_reset(void) int scc_init(void) { -// uint32_t x, y, z; -// uint32_t tmp; int num_ranks; - int my_rank; - - return 0; + int i, my_rank; kprintf("Initialize Rock Creek!\n"); + for(i=0; i>3) & 0x0f; // bits 06:03 - y=(tmp>>7) & 0x0f; // bits 10:07 - z=(tmp ) & 0x07; // bits 02:00 - scc_info.pid = PID(x, y, z); - kprintf("SCC Processor Id: %u (%u,%u,%u)\n", scc_info.pid, x, y, z); -*/ - /* default values for 16 GB system */ - /*scc_info.private_mem[0].low = 0x00; - scc_info.private_mem[0].high = 0x13FFFFFF; - scc_info.private_mem[1].low = 0xFF000000; - scc_info.private_mem[1].high = 0xFFFFFFFF; -*/ -// tmp = *((uint32_t*) (CRB_OWN+GCBCFG)); -// tmp = (tmp & 0x3FFFFFF) >> 7; - //kprintf("Own GCBCFG is 0x%x\n", tmp); -/* if (tmp == 0x70E1) { - scc_info.tile_frequency = 800; - scc_info.router_frequency = 1600; - } else { - scc_info.tile_frequency = 533; - scc_info.router_frequency = 800; - } -*/ - -/* kprintf("The default tile frequency is %u MHz\nThe default router frequency is %u MHz\n", - scc_info.tile_frequency, scc_info.router_frequency); - - if (z == 0) - tmp = *((uint32_t*) (CRB_OWN+GLCFG0)); - else if (z == 1) - tmp = *((uint32_t*) (CRB_OWN+GLCFG1)); - else - tmp = 0; -*/ - /* set INTR to enable maskable interrupts */ -/* tmp = tmp | CCR_INTR_ACTIVE; - if (z == 0) - *((uint32_t*) (CRB_OWN+GLCFG0)) = tmp; - else if (z == 1) - *((uint32_t*) (CRB_OWN+GLCFG1)) = tmp; -*/ - /* reload core configuration */ -/* tmp = 0; - if (z == 0) - tmp = *((uint32_t*) (CRB_OWN+GLCFG0)); - else if (z == 1) - tmp = *((uint32_t*) (CRB_OWN+GLCFG1)); - kprintf("Core Configuration %u: 0x%x\n", z, tmp); -*/ + //RCCE_barrier(&RCCE_COMM_WORLD); kputs("Now, the SCC is initialized!\n");