add function icc_wait, which waits for a specific mail tag

This commit is contained in:
Stefan Lankes 2011-11-07 11:25:54 -08:00
parent ec0c1e5381
commit a5503ad23a
2 changed files with 32 additions and 4 deletions

View file

@ -43,6 +43,7 @@ enum icc_mail_requests {
PING_REQ=1,
PING_RESP,
SVM_REQUEST,
SVM_RESP,
NOISE,
};
@ -53,6 +54,7 @@ int icc_mail_ping(void);
int icc_send_gic_irq(int core_num);
int icc_mail_ping_irq(void);
int icc_mail_noise(void);
void icc_wait(int tag);
#endif

View file

@ -26,6 +26,7 @@
#include <asm/SCC_API.h>
#include <asm/icc.h>
#include <asm/svm.h>
#include <asm/limits.h>
#define IRQ_STATUS 0xD000
#define IRQ_MASK 0xD200
@ -35,7 +36,6 @@
#include <net/rckemac.h>
bootinfo_t* bootinfo = (bootinfo_t*) SCC_BOOTINFO;
/* PSE bit for Pentium+ equals MPE (message buffer enable) flag in RCK! So, use it to create _PAGE_MPB symbol... */
@ -100,6 +100,8 @@ static inline void icc_mail_check_tag(iRCCE_MAIL_HEADER* mail) {
case SVM_REQUEST:
svm_emit_page(((size_t*) mail->payload)[1], ((size_t*) mail->payload)[0]);
break;
case SVM_RESP:
break;
case NOISE:
// kprintf( "XXX " );
default:
@ -488,9 +490,7 @@ int icc_mail_noise(void) {
}
/*
* Routine to check mailboxes. If irq = 1 is passed only those boxes are checked that
* refere to the cores with set bit in status register.
*
* Routine to check mailboxes.
*/
void icc_mail_check(void)
@ -516,4 +516,30 @@ void icc_mail_check(void)
irq_nested_enable(flags);
}
void icc_wait(int tag)
{
iRCCE_MAIL_HEADER* header = NULL;
uint32_t flags, done = 0;
/* disable interrupts */
flags = irq_nested_disable();
do {
iRCCE_mail_check(iRCCE_MAILBOX_ALL);
/* empty mail queue */
while( iRCCE_mail_recv(&header) == iRCCE_SUCCESS ) {
icc_mail_check_tag(header);
if (header->tag == tag)
done = 1;
iRCCE_mail_release( &header );
NOP8;
NOP8;
NOP8;
}
} while(!done);
/* enable interrupts */
irq_nested_enable(flags);
}
#endif