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- add macros for cache flushing and memory barriers

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git-svn-id: http://svn.lfbs.rwth-aachen.de/svn/scc/trunk/MetalSVM@145 315a16e6-25f9-4109-90ae-ca3045a26c18
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stefan 2010-09-07 21:10:59 +00:00
parent 2819d27885
commit bb075ea130
1 changed files with 15 additions and 1 deletions
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16
arch/x86/include/asm/processor.h
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@ -32,13 +32,27 @@
extern "C" {
#endif
static inline uint64_t rdtsc()
static inline uint64_t rdtsc(void)
{
uint64_t x;
asm volatile ("rdtsc" : "=A" (x));
return x;
}
#define flush_cache() asm volatile ("wbinvd" : : : "memory")
#define invalid_cache() asm volatile ("invd")
/* Force strict CPU ordering */
#ifdef CONFIG_ROCKCREEK
#define mb() asm volatile ("lock; addl $0,0(%%esp)" ::: "memory")
#define rmb() asm volatile ("lock; addl $0,0(%%esp)" ::: "memory")
#define wmb() asm volatile ("lock; addl $0,0(%%esp)" ::: "memory")
#else
#define mb() asm volatile("mfence" ::: "memory")
#define rmb() asm volatile("lfence" ::: "memory")
#define wmb() asm volatile("sfence" ::: "memory")
#endif
#define get_return_value(ret) asm volatile ("movl %%eax, %0" : "=r"(ret))
#define NOP1 asm volatile ("nop")