- add APIC support for the SCC
- seems to work, only the APIC timer doesn't work! git-svn-id: http://svn.lfbs.rwth-aachen.de/svn/scc/trunk/MetalSVM@273 315a16e6-25f9-4109-90ae-ca3045a26c18
This commit is contained in:
stefan
parent
1cfc42c5a6
commit
bc67c946af
7 changed files with 155 additions and 45 deletions
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@ -87,6 +87,8 @@ typedef struct {
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typedef struct {
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uint32_t pid;
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uint32_t tile_frequency; // in MHz
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uint32_t router_frequency; // in MHz
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mem_region_t private_mem[SCC_PMEM_REGIONS];
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} scc_info_t;
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@ -34,7 +34,7 @@
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#define APIC_TPR 0x0080 // Task Priority Regster
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#define APIC_EOI 0x00B0 // EOI Register
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#define APIC_SVR 0x00F0 // Spurious Interrupt Vector Register
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#define APIC_LVT_T 0x0320 // LVT Thermal Sensor Register (P4/Xeon only)
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#define APIC_LVT_T 0x0320 // LVT Timer Register
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#define APIC_LVT_PMC 0x0340 // LVT Performance Monitoring Counters Register
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#define APIC_LINT0 0x0350 // LVT LINT0 Register
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#define APIC_LINT1 0x0360 // LVT LINT1 Register
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@ -45,8 +45,14 @@
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static apic_mp_t* apic_mp = NULL;
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static apic_config_table_t* apic_config = NULL;
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static uint32_t lapic = 0;
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static uint32_t ncores = 1;
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static inline void apic_write(uint32_t addr, uint32_t value)
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{
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asm volatile ("movl (%%eax), %%edx; movl %%ebx, (%%eax)" :: "a"(addr), "b"(value) : "%edx");
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}
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#ifndef CONFIG_MULTIBOOT
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static unsigned int* search_apic(unsigned int base, unsigned int limit) {
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unsigned int *ptr;
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@ -65,7 +71,8 @@ static unsigned int* search_apic(unsigned int base, unsigned int limit) {
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*/
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void apic_eoi(void)
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{
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*((uint32_t*) (apic_config->lapic+APIC_EOI)) = 0;
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if (lapic)
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apic_write(lapic+APIC_EOI, 0);
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}
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/*
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@ -74,6 +81,7 @@ void apic_eoi(void)
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*/
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int apic_calibration(void)
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{
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#ifndef CONFIG_ROCKCREEK
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uint64_t ticks, old;
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uint32_t diff;
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@ -86,23 +94,55 @@ int apic_calibration(void)
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while((ticks = get_clock_tick()) - old == 0)
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;
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*((uint32_t*) (apic_config->lapic+APIC_DCR)) = 0xB; // set it to 1 clock increments
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*((uint32_t*) (apic_config->lapic+APIC_LVT_T)) = 0x20030; // connects the timer to 48 and enables it
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*((uint32_t*) (apic_config->lapic+APIC_ICR)) = 0xFFFFFFFF;
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apic_write(lapic+APIC_DCR, 0xB); // set it to 1 clock increments
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apic_write(lapic+APIC_LVT_T, 0x20030); // connects the timer to 48 and enables it
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apic_write(lapic+APIC_ICR), 0xFFFFFFFF);
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/* wait 3 time slices to determine a ICR */
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while(get_clock_tick() - ticks < 3)
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;
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diff = 0xFFFFFFFF - *((uint32_t*) (apic_config->lapic+APIC_CCR));
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diff = 0xFFFFFFFF - *((uint32_t*) (lapic+APIC_CCR));
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*((uint32_t*) (apic_config->lapic+APIC_DCR)) = 0xB; // set it to 1 clock increments
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*((uint32_t*) (apic_config->lapic+APIC_LVT_T)) = 0x20030; // connects the timer to 48 and enables it
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*((uint32_t*) (apic_config->lapic+APIC_ICR)) = diff / 3;
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apic_write(lapic+APIC_DCR, 0xB); // set it to 1 clock increments
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apic_write(lapic+APIC_LVT_T, 0x20030); // connects the timer to 48 and enables it
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apic_write(lapic+APIC_ICR, diff / 3);
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// Now, MetalSVM is able to use the APIC => Therefore, we disable the PIC
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outportb(0xA1, 0xFF);
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outportb(0x21, 0xFF);
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#else
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/*
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* On the SCC, we already know the processor frequency
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* and possess no PIC timer. Therfore, we use the rdtsc to
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* to calibrate the APIC timer.
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*/
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uint64_t start, end, ticks;
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uint32_t diff;
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if (!has_apic())
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return -ENXIO;
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apic_write(lapic+APIC_DCR, 0xB); // set it to 1 clock increments
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apic_write(lapic+APIC_LVT_T, 0x20030); // connects the timer to 48 and enables it
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apic_write(lapic+APIC_ICR, 0xFFFFFFFF);
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/* wait 3 time slices to determine a ICR */
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start = rdtsc();
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do {
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flush_pipeline();
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end = rdtsc();
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ticks = end > start ? end - start : start - end;
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} while(ticks < 3*scc_info.tile_frequency*1000000 / TIMER_FREQ);
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diff = 0xFFFFFFFF - *((uint32_t*) (lapic+APIC_CCR));
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apic_write(lapic+APIC_DCR, 0xB); // set it to 1 clock increments
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apic_write(lapic+APIC_LVT_T, 0x20030); // connects the timer to 48 and enables it
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apic_write(lapic+APIC_ICR, diff / 3);
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#endif
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kprintf("APIC calibration detects an ICR of 0x%x\n", diff / 3);
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return 0;
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}
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@ -110,7 +150,7 @@ int apic_calibration(void)
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static int apic_probe(void)
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{
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size_t addr;
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uint32_t i, count, dummy;
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uint32_t i, count;
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// searching MP signature in the reserved memory areas
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#ifdef CONFIG_MULTIBOOT
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@ -133,28 +173,28 @@ static int apic_probe(void)
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mmap++;
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}
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}
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found_mp:
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#else
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apic_mp = (apic_mp_t*) search_apic(0xF0000, 0x100000);
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if (!apic_mp)
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apic_mp = (apic_mp_t*) search_apic(0x9F000, 0xA0000);
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#endif
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found_mp:
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if (!apic_mp)
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goto out;
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goto no_mp;
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kprintf("System uses Multiprocessing Specification 1.%d\n", apic_mp->version);
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kprintf("MP features 1: %d\n", apic_mp->features[0]);
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if (apic_mp->features[0]) {
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kputs("Currently, MetalSVM supports only multiprocessing via the MP config tables!\n");
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goto out;
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goto no_mp;
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}
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apic_config = (apic_config_table_t*) apic_mp->mp_config;
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if (!apic_config || strncmp((void*) &apic_config->signature, "PCMP", 4) !=0) {
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kputs("Invalid MP config table\n");
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goto out;
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goto no_mp;
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}
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addr = (size_t) apic_config;
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@ -172,34 +212,45 @@ found_mp:
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if (count > MAX_CORES) {
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kputs("Found too many cores! Increase the macro MAX_CORES!\n");
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goto out;
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goto no_mp;
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}
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ncores = count;
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i = *((uint32_t*) (apic_config->lapic+APIC_VERSION));
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kprintf("Found APIC at 0x%x\n", apic_config->lapic);
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check_lapic:
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if (apic_config) {
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lapic = apic_config->lapic;
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} else {
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uint32_t eax, edx, dummy;
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cpuid(0x1, &eax, &dummy, &dummy, &edx);
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if (edx & (1 << 9))
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lapic = 0xFEE00000;
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kprintf("Processor familiy %u, model %u, stepping %u\n", (eax>>8)&0xF, (eax>>4)&0xF, eax&0xF);
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}
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if (!lapic)
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goto out;
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i = *((uint32_t*) (lapic+APIC_VERSION));
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kprintf("Found APIC at 0x%x\n", lapic);
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kprintf("Maximum LVT Entry: 0x%x\n", (i >> 16) & 0xFF);
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kprintf("APIC Version: 0x%x\n", i & 0xFF);
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cpuid(0x1, &i, &dummy, &dummy, &dummy);
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if (!(i & (1 << 5))) {
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kputs("Unable to use Machine-Specific Registers (MSR)\n");
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goto out;
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}
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if (!(rdmsr(0x1B) & (1 << 11))) {
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kputs("Unable to use APIC Global Enable flag!\n");
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goto out;
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}
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return 0;
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out:
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apic_mp = NULL;
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apic_config = NULL;
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lapic = 0;
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ncores = 1;
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return -ENXIO;
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no_mp:
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apic_mp = NULL;
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apic_config = NULL;
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ncores = 1;
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goto check_lapic;
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}
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int apic_init(void)
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@ -210,18 +261,18 @@ int apic_init(void)
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if (!ret)
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return ret;
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*((uint32_t*) (apic_config->lapic+APIC_TPR)) = 0x20; // inhibit softint delivery
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*((uint32_t*) (apic_config->lapic+APIC_LVT_T)) = 0x10000; // disable timer interrupt
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*((uint32_t*) (apic_config->lapic+APIC_LVT_PMC)) = 0x10000; // disable performance counter interrupt
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*((uint32_t*) (apic_config->lapic+APIC_LINT0)) = 0x31; // connect LINT0 to idt entry 49
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*((uint32_t*) (apic_config->lapic+APIC_LINT1)) = 0x32; // connect LINT1 to idt entry 50
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*((uint32_t*) (apic_config->lapic+APIC_LVT_ER)) = 0x33; // connect error to idt entry 51
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*((uint32_t*) (apic_config->lapic+APIC_SVR)) = 0x134; // enable the apic and connect to the idt entry 52
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apic_write(lapic+APIC_TPR, 0x00); // allow all interrupts
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apic_write(lapic+APIC_LVT_T, 0x10000); // disable timer interrupt
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apic_write(lapic+APIC_LVT_PMC, 0x10000);// disable performance counter interrupt
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apic_write(lapic+APIC_LINT0, 0x31); // connect LINT0 to idt entry 49
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apic_write(lapic+APIC_LINT1, 0x32); // connect LINT1 to idt entry 50
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apic_write(lapic+APIC_LVT_ER, 0x33); // connect error to idt entry 51
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apic_write(lapic+APIC_SVR, 0x17F); // enable the apic and connect to the idt entry 207
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return 0;
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}
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int has_apic(void)
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{
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return ((apic_mp != NULL) && (apic_config != NULL));
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return (lapic != 0);
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}
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@ -718,7 +718,7 @@ apic_svr:
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0
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push byte 52
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push byte 127
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jmp irq_common_stub
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@ -51,7 +51,7 @@ extern void apic_lint1(void);
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extern void apic_error(void);
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extern void apic_svr(void);
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#define MAX_HANDLERS 32
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#define MAX_HANDLERS 256
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/*
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* This array is actually an array of function pointers. We use
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@ -93,6 +93,7 @@ int irq_uninstall_handler(unsigned int irq)
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*/
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static int irq_remap(void)
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{
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#ifndef CONFIG_ROCKCREEK
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outportb(0x20, 0x11);
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outportb(0xA0, 0x11);
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outportb(0x21, 0x20);
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@ -103,6 +104,7 @@ static int irq_remap(void)
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outportb(0xA1, 0x01);
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outportb(0x21, 0x0);
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outportb(0xA1, 0x0);
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#endif
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return 0;
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}
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@ -158,7 +160,7 @@ static int irq_install(void)
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IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
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idt_set_gate(51, (unsigned)apic_error, KERNEL_CODE_SELECTOR,
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IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
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idt_set_gate(52, (unsigned)apic_svr, KERNEL_CODE_SELECTOR,
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idt_set_gate(127, (unsigned)apic_svr, KERNEL_CODE_SELECTOR,
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IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
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}
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@ -194,6 +196,11 @@ void irq_handler(struct state *s)
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/* This is a blank function pointer */
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void (*handler) (struct state * s);
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if (s->int_no - 32 > MAX_HANDLERS) {
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apic_eoi();
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return;
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}
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/*
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* Find out if we have a custom handler to run for this
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* IRQ and then finally, run it
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@ -22,6 +22,7 @@
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#include <metalsvm/tasks.h>
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#include <asm/irqflags.h>
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#include <asm/isrs.h>
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#include <asm/apic.h>
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#include <asm/idt.h>
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/*
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@ -172,9 +173,12 @@ void fault_handler(struct state *s)
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kputs(" Exception.\n");
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/* Now, we signalize that we have handled the interrupt */
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outportb(0x20, 0x20);
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irq_enable();
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if (has_apic())
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apic_eoi();
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else
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outportb(0x20, 0x20);
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irq_enable();
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abort();
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}
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}
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@ -18,25 +18,29 @@
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*/
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#include <metalsvm/stdio.h>
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#include <metalsvm/errno.h>
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#include <asm/scc.h>
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#include <asm/io.h>
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#ifdef CONFIG_ROCKCREEK
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#define CCR_INTR_ACTIVE 0x02
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scc_info_t scc_info;
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int scc_init(void)
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{
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int tmp, x, y, z;
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uint32_t x, y, z;
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uint32_t tmp;
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kprintf("Initialize Rock Creek!\n");
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tmp = *((int*) (CRB_OWN+MYTILEID));
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tmp = *((uint32_t*) (CRB_OWN+MYTILEID));
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x=(tmp>>3) & 0x0f; // bits 06:03
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y=(tmp>>7) & 0x0f; // bits 10:07
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z=(tmp ) & 0x07; // bits 02:00
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scc_info.pid = PID(x, y, z);
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kprintf("SCC Processor Id: %d (%d,%d,%d)\n", scc_info.pid, x, y, z);
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kprintf("SCC Processor Id: %u (%u,%u,%u)\n", scc_info.pid, x, y, z);
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/* default values for 16 GB system */
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scc_info.private_mem[0].low = 0x00;
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@ -44,6 +48,42 @@ int scc_init(void)
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scc_info.private_mem[1].low = 0xFF000000;
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scc_info.private_mem[1].high = 0xFFFFFFFF;
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tmp = *((uint32_t*) (CRB_OWN+GCBCFG));
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tmp = (tmp & 0x3FFFFFF) >> 7;
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//kprintf("Own GCBCFG is 0x%x\n", tmp);
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if (tmp == 0x70E1) {
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scc_info.tile_frequency = 800;
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scc_info.router_frequency = 1600;
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} else {
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scc_info.tile_frequency = 533;
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scc_info.router_frequency = 800;
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}
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kprintf("The default tile frequency is %u MHz\nThe default router frequency is %u MHz\n",
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scc_info.tile_frequency, scc_info.router_frequency);
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if (z == 0)
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tmp = *((uint32_t*) (CRB_OWN+GLCFG0));
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else if (z == 1)
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tmp = *((uint32_t*) (CRB_OWN+GLCFG1));
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else
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tmp = 0;
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/* set INTR to enable maskable interrupts */
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tmp = tmp | CCR_INTR_ACTIVE;
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if (z == 0)
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*((uint32_t*) (CRB_OWN+GLCFG0)) = tmp;
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else if (z == 1)
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*((uint32_t*) (CRB_OWN+GLCFG1)) = tmp;
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/* reload core configuration */
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tmp = 0;
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if (z == 0)
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tmp = *((uint32_t*) (CRB_OWN+GLCFG0));
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else if (z == 1)
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tmp = *((uint32_t*) (CRB_OWN+GLCFG1));
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kprintf("Core Configuration %u: 0x%x\n", z, tmp);
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return 0;
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}
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@ -87,6 +87,11 @@ int timer_init(void)
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irq_install_handler(0, timer_handler);
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irq_install_handler(16, timer_handler);
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/*
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* The Rock Creek processor doesn't posseess an tradional PIC.
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* Therefore, we have not to configure the PIC timer.
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*/
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#ifndef CONFIG_ROCKCREEK
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outportb(0x43, 0x34);
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/* before we write to 0x40, we wait some time */
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start = rdtsc();
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@ -98,6 +103,7 @@ int timer_init(void)
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while(rdtsc() - start < 1000000)
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;
|
||||
outportb(0x40, LATCH(TIMER_FREQ) >> 8); /* high byte */
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue