From f0e4a2b8335dd29aa3f2b0a9772c1a02036edecb Mon Sep 17 00:00:00 2001 From: Stefan Lankes Date: Tue, 5 Apr 2011 23:43:44 -0700 Subject: [PATCH 1/4] add the support of the memory type MPBT => seesection "10.1.2 Internal Cache Changes" of SCC External Architecture Specification (R1.1) --- arch/x86/include/asm/page.h | 1 + arch/x86/include/asm/processor.h | 10 ++++++++++ arch/x86/mm/page.c | 8 ++++++-- arch/x86/scc/scc_init.c | 8 ++++++++ include/metalsvm/stdlib.h | 4 +++- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/page.h b/arch/x86/include/asm/page.h index 553a2584..6f62bc32 100644 --- a/arch/x86/include/asm/page.h +++ b/arch/x86/include/asm/page.h @@ -48,6 +48,7 @@ #define PG_ACCESSED (1 << _PAGE_BIT_ACCESSED) #define PG_DIRTY (1 << _PAGE_BIT_DIRTY) #define PG_PSE (1 << _PAGE_BIT_PSE) +#define PG_MPE PG_PSE #define PG_GLOBAL (1 << _PAGE_BIT_GLOBAL) #define PG_RESERVED (1 << _PAGE_BIT_RESERVED) #define PG_PAT (1 << _PAGE_BIT_PAT) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 27294236..b79a4b60 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -113,6 +113,16 @@ static inline void write_cr3(uint32_t val) { asm volatile("mov %0, %%cr3" : : "r"(val)); } +static inline uint32_t read_cr4(void) { + uint32_t val; + asm volatile("mov %%cr4, %0" : "=r"(val)); + return val; +} + +static inline void write_cr4(uint32_t val) { + asm volatile("mov %0, %%cr4" : : "r"(val)); +} + static inline void tlb_flush_one_page(uint32_t addr) { asm volatile("invlpg (%0)" : : "r"(addr) : "memory"); diff --git a/arch/x86/mm/page.c b/arch/x86/mm/page.c index 114f2a66..993ccc3d 100644 --- a/arch/x86/mm/page.c +++ b/arch/x86/mm/page.c @@ -339,6 +339,10 @@ size_t map_region(size_t viraddr, size_t phyaddr, uint32_t npages, uint32_t flag if (flags & MAP_NO_CACHE) pgt->entries[index] |= PG_PCD; +#ifdef CONFIG_ROCKCREEK + if (flags & MAP_MPE) + pgt->entries[index] |= PG_MPE; +#endif if (flags & MAP_USER_SPACE) atomic_int32_inc(&task->user_usage); @@ -684,8 +688,8 @@ int arch_paging_init(void) viraddr = map_region(CRB_X0_Y0, CRB_X0_Y0, (CRB_OWN-CRB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE|MAP_NO_CACHE); kprintf("Map configuration registers at 0x%x\n", viraddr); - // map SCC's configuration registers - viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE); + // map SCC's message passing buffers + viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE|MAP_MPE); kprintf("Map message passing buffers at 0x%x\n", viraddr); #endif diff --git a/arch/x86/scc/scc_init.c b/arch/x86/scc/scc_init.c index 0e3a2197..02b6057f 100644 --- a/arch/x86/scc/scc_init.c +++ b/arch/x86/scc/scc_init.c @@ -27,6 +27,9 @@ #ifdef CONFIG_ROCKCREEK +/* PSE bit for Pentium+ equals MPE (message buffer enable) flag in RCK! So, use it to create _PAGE_MPB symbol... */ +#define _CR4_MPE 0x00000800 + /* * Workaround to create a suitable argv array */ @@ -83,6 +86,11 @@ int scc_init(void) num_ranks = RCCE_num_ues(); kprintf("Got rank %d of %d ranks\n", my_rank, num_ranks); + /* Enable Messagepassing in CR4 */ + uint32_t cr4 = read_cr4(); + cr4 = cr4 | _CR4_MPE; + write_cr4(cr4); + i = ReadConfigReg(CRB_OWN+GLCFG0); kprintf("glcfg0 0x%x\n", i); diff --git a/include/metalsvm/stdlib.h b/include/metalsvm/stdlib.h index 6a74fac6..ca6d3d91 100644 --- a/include/metalsvm/stdlib.h +++ b/include/metalsvm/stdlib.h @@ -36,7 +36,9 @@ extern "C" { #define MAP_HEAP (1 << 5) #define MAP_CODE (1 << 6) #define MAP_READONLY (1 << 7) - +#ifdef CONFIG_ROCKCREEK +#define MAP_MPE (1 << 8) +#endif void NORETURN abort(void); void* kmalloc(size_t); void* mem_allocation(size_t sz, uint32_t flags); From 683f8cca1eae1bb6d9330b822d7c3a4aea470e51 Mon Sep 17 00:00:00 2001 From: Stefan Lankes Date: Wed, 6 Apr 2011 05:38:44 -0700 Subject: [PATCH 2/4] add macro to simplify the using of th hlt instruction --- arch/x86/include/asm/processor.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index b79a4b60..9e44bf1d 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -145,10 +145,11 @@ static inline uint32_t read_eflags(void) uint32_t read_eip(void); -#define NOP1 asm volatile ("nop") -#define NOP2 asm volatile ("nop;nop") -#define NOP4 asm volatile ("nop;nop;nop;nop") -#define NOP8 asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop") +#define NOP1 asm volatile ("nop") +#define NOP2 asm volatile ("nop;nop") +#define NOP4 asm volatile ("nop;nop;nop;nop") +#define NOP8 asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop") +#define HALT asm volatile ("hlt"); inline static int system_init(void) { From d3ad7e1c665e0871bd72e8c40d2125847a00da12 Mon Sep 17 00:00:00 2001 From: Stefan Lankes Date: Fri, 8 Apr 2011 07:24:47 -0700 Subject: [PATCH 3/4] move the call of scc_init to main function --- kernel/main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/main.c b/kernel/main.c index eae0ec05..3cf4aa07 100644 --- a/kernel/main.c +++ b/kernel/main.c @@ -89,6 +89,9 @@ int main(void) #endif multitasking_init(); mmu_init(); +#ifdef CONFIG_ROCKCREEK + scc_init(); +#endif initrd_init(); irq_enable(); From 0fbf2df5ac200f8f25802c41322a13cb942a08e4 Mon Sep 17 00:00:00 2001 From: Stefan Lankes Date: Fri, 8 Apr 2011 10:45:26 -0700 Subject: [PATCH 4/4] use inline assembler to load the IDT --- arch/x86/kernel/entry.asm | 9 +-------- arch/x86/kernel/idt.c | 7 ++----- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/entry.asm b/arch/x86/kernel/entry.asm index a9d85364..f24b33dd 100644 --- a/arch/x86/kernel/entry.asm +++ b/arch/x86/kernel/entry.asm @@ -103,14 +103,7 @@ gdt_flush: flush2: ret -; Loads the IDT defined in '_idtp' into the processor. -; This is declared in C as 'extern void idt_load();' -global idt_load -extern idtp -idt_load: - lidt [idtp] - ret - +; determines the current instruction pointer (after the jmp) global read_eip read_eip: pop eax ; Get the return address diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index 20f620a1..0f231931 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -43,10 +43,7 @@ typedef struct { * "Unhandled Interrupt" exception */ static idt_entry_t idt[256] = {[0 ... 255] = {0, 0, 0, 0, 0}}; -idt_ptr_t idtp; - -/* This exists in 'start.asm', and is used to load our IDT */ -extern void idt_load(void); +static idt_ptr_t idtp; /* * Use this function to set an entry in the IDT. Alot simpler @@ -81,5 +78,5 @@ void idt_install(void) IDT_FLAG_PRESENT|IDT_FLAG_RING3|IDT_FLAG_32BIT|IDT_FLAG_TRAPGATE); /* Points the processor's internal register to the new IDT */ - idt_load(); + asm volatile("lidt %0" : : "m" (idtp)); }