...

arch/x86/scc/icc.c

@@ -26,6 +26,9 @@
 #include <asm/SCC_API.h>
 #include <asm/icc.h>
 
+#include <net/mmnif.h>
+
+
 bootinfo_t* bootinfo = (bootinfo_t*) SCC_BOOTINFO;
 static int num_ues, my_ue;
 
@@ -79,6 +82,8 @@ static void intr_handler(struct state *s)
 	// reset appropriate bit in the core configuration register
 	int tmp, z;
 
+	mmnif_irqhandler();
+
 	z = Z_PID(RC_COREID[my_ue]);
 	tmp=ReadConfigReg(CRB_OWN + (z==0 ? GLCFG0 : GLCFG1));
 	tmp &= ~2;
@@ -142,7 +147,7 @@ int icc_init(void)
 		kprintf("failed! (0x%x)\n", msg);
 #endif
 
-#if 1
+#if 0
 	char* str = RCCE_shmalloc(128);
 	if (my_ue == 1) {
 		memset(str, 0x00, 128);

drivers/net/mmnif.c

@@ -110,7 +110,7 @@ static int local_crb = 0xF8000000;
 static int crb = 0xE0000000;
 
 /* just set and reset the irq */
-static int pulse_irq = 1;
+static int pulse_irq = 0;
 
 /* Mask of the interrupt bits */
 #define RCK_INTR_MASK       0x00000002

drivers/net/mmnif.h

@@ -27,4 +27,6 @@ int mmnif_close();
 int mmnif_poll(void* e);
 int mmnif_worker(void* e);
 
-#endif
+void mmnif_irqhandler();
+
+#endif