stv0g/metalsvm
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

testing remote interrupts

Browse source
This commit is contained in:
Simon Pickartz 2011-08-09 14:54:30 -07:00
parent 736d221022
commit d7175a72a9
3 changed files with 53 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
arch/x86/kernel/irq.c
View file

@ -238,17 +238,17 @@ void irq_handler(struct state *s)
// at first, we check our work queues
if( s->int_no == 124 ) {
kprintf( "hello from rem_interrupt\n" );
check_workqueues();
}
int status_reg1 = FPGA_BASE + 0x0D008;
int cont1 = *((int*)status_reg1);
int comp = 1;
int status_reg1 = FPGA_BASE + 0xD008;
int comp = (1<<5);
int core_num = -1;
if( cont1 & comp ) {
if( *((volatile int*)status_reg1) & comp ) {
kprintf( "Interrupt from core 1\n" );
}
check_workqueues();
// }
/*
* Find out if we have a custom handler to run for this
* IRQ and then finally, run it

2
arch/x86/scc/iRCCE_mailbox.c
View file

@ -42,7 +42,7 @@
#include <asm/irqflags.h>
// forward declaration
int iRCCE_mailbox_close_one(int rank, int check);
static int iRCCE_mailbox_close_one(int rank, int check);
//------------------------------------------------------------------------------
// FUNCTION: iRCCE_mailbox_print_header

54
arch/x86/scc/icc.c
View file

@ -26,6 +26,14 @@
#include <asm/SCC_API.h>
#include <asm/icc.h>
#define IRQ_STATUS 0xD000
#define IRQ_MASK 0xD200
#define IRQ_RESET 0xD400
#define IRQ_REQUEST 0xD600
#define IRQ_CONFIG 0xD800
bootinfo_t* bootinfo = (bootinfo_t*) SCC_BOOTINFO;
static int num_ues, my_ue;
@ -162,6 +170,29 @@ int icc_init(void)
// set interrupt handler (INTR/LINT0)
irq_install_handler(124, intr_handler);
// unmask interrupts
int irq_mask = FPGA_BASE + IRQ_MASK + my_ue*8;
*(int*)irq_mask &= 0;
irq_mask += 4;
*(int*)irq_mask &= 0;
// reset interrupt reg
int irq_reset = FPGA_BASE + IRQ_RESET + my_ue*8;
*(int*)irq_reset &= 0;
irq_reset += 4;
*(int*)irq_reset &= 0;
kprintf( "irq_request = %x\n", *(int*)(FPGA_BASE + IRQ_REQUEST + my_ue*8));
//int irq_request = FPGA_BASE + IRQ_REQUEST + my_ue*8;
//*(int*) irq_request = 1;
kprintf( "irq_request = %x\n", *(int*)(FPGA_BASE + IRQ_REQUEST + my_ue*8));
kprintf( "irq_mask = %x\n", *(int*)(FPGA_BASE + IRQ_MASK + my_ue*8) );
kprintf( "LUT = %x\n", *(int*)(FPGA_BASE + IRQ_CONFIG + my_ue*4) );
kprintf( "reset_reg = %x\n", *(int*)(FPGA_BASE + IRQ_RESET + my_ue*8) );
kprintf( "status_reg = %x\n", *(int*)(FPGA_BASE + IRQ_STATUS + my_ue*8) );
kputs("Now, the SCC is initialized!\n");
return 0;
@ -201,14 +232,22 @@ int icc_halt(void)
int icc_send_spec_irq(int core_num) {
int addr = FPGA_BASE+0x0D608;
int tmp;
tmp=ReadConfigReg(addr);
unsigned int addr = FPGA_BASE+IRQ_REQUEST+8*my_ue;
// determine bit position and set according bit
if( my_ue < 32 ) {
unsigned int tmp;
kprintf( "*addr = %x\n", addr ) ;
tmp = ReadConfigReg(addr);
tmp |= 2;
kprintf( "tmp = %x\n", tmp );
SetConfigReg(addr, tmp);
kprintf( "request_reg_addr = %x\n", addr );
kprintf( "request_reg = %x\n", *(unsigned int*)addr );
}
else {
}
kprintf( "tmp = %x\n", tmp );
tmp |= 1;
kprintf( "tmp = %x\n", tmp );
SetConfigReg(addr, tmp);
return 0;
}
@ -218,7 +257,6 @@ int icc_irq_ping()
if( my_ue != 0 ) return -1;
icc_send_spec_irq(1);
icc_send_irq(1);
kprintf( "sending irq to 1!\n");
return 0;
}